JPH07262783A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce noise of power source. CONSTITUTION:Control circuits for the load of a data line 26a, 26b, 27a, 27b for selectively controlling the impedance of the load element of the corresponding data line are provided based on a column selecting signal for selecting a column system and a write-enable signal for instructing to write data in a memory cell. The change of current is reduced by decreasing the number of P channel MOS transistors which are simultaneously driven and the noise of power source caused by driving the load element of a data line is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for reducing power source noise at the time of writing data to the semiconductor memory device, for example, a technique effectively applied to SRAM (Static Random Access Memory). .

[0002]

2. Description of the Related Art SRAM as an example of a semiconductor memory device
(Static random access memory) includes a memory cell array in which a plurality of static memory cells are arranged in a matrix. A memory cell array is usually formed by a unit called a plurality of memory mats or a plurality of memory blocks. Select terminals of memory cells are connected to word lines in each row direction (row direction), and data input / output terminals of memory cells are connected to complementary data lines (also called complementary bit lines) in each column direction (column direction). To be done. Each complementary data line is commonly connected to the complementary common data line via a column switch which is coupled to the complementary data line in a one-to-one relationship.

An address signal input from the outside is transmitted to a row address decoder or a column address decoder via an address buffer arranged corresponding to the address signal. Based on the decode output of the row address decoder,
When the word line corresponding to the input address signal is driven to the selection level, all the memory cells connected to this word line are selected. Further, the column switch is turned on based on the decode output of the column address decoder, and the selected memory cell is electrically connected to the complementary common data line. When write data is externally applied, the complementary common data line is driven according to the write data, and charge information corresponding to the data is stored in a predetermined memory cell via the complementary data line selected by the column address.

An example of a document describing SRAM is "LSI Handbook (starting from page 500)" issued by Ohmsha on November 30, 1984.

[0005]

A data line load element for precharging the data line is coupled to the data line,
The data line is precharged to a predetermined potential level via the data line load element. Considering the case where the data line is pulled down to a low level for data writing, it is advantageous to increase the impedance of the data line load element in terms of speeding up writing. However, if the impedance of the data line load elements is changed all at once for each memory mat or memory block, the SRAM
Depending on the configuration, the number of data line load elements becomes enormous, so that the transient voltage when driving the data line load elements causes the power supply voltage level to fluctuate momentarily. This fluctuation causes power supply noise and adversely affects the operation of each unit. A low power supply voltage is advantageous for speeding up the memory, but especially as a data line load element, a MOS is used.
When a transistor is used, the amplitude of the voltage applied to the gate of the data line load MOS transistor becomes small under a low power supply voltage. Therefore, in order to obtain the necessary data line amplitude, the gate width of the data line load MOS transistor is reduced. Needs to be increased. When the gate width of the MOS transistor becomes large as described above, the gate capacitance becomes large, so that a larger transient current will flow due to the impedance control as described above. Further, during the high speed write operation, the transient current flows in a short time, so that the power supply noise is further increased.

An object of the present invention is to provide a technique for reducing power source noise.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, in order to selectively control the impedance of the corresponding data line load element based on the column select signal for selecting the column system and the write enable signal for instructing the data write to the memory cell. The semiconductor memory device is configured by providing the data line load control circuit of.

In addition to the column select signal for selecting the column and the write enable signal for instructing the data write to the memory cell, the write data to the memory cell is also taken into consideration and the corresponding data is taken into consideration. A data line load control circuit for selectively controlling the impedance of the line load element is provided.

At this time, based on a plurality of write recovery elements for performing write recovery, a write recovery signal for instructing this write recovery operation, and a write enable signal for instructing data writing to the memory cell. Thus, a write recovery control circuit for selectively controlling the operation of the corresponding write recovery element can be provided.

Further, as a write recovery control circuit for selectively controlling the operation of the write recovery element, a write recovery signal for instructing a write recovery operation and a write for instructing data writing to the memory cell. In addition to the enable signal, the write data to the memory cell can be considered.

[0013]

According to the above means, the data line load control circuit does not control the data line load element impedances in units of memory mats or memory blocks all at once, but on the basis of the column selection signal and the write enable signal. Selectively control the corresponding data line load element.
This reduces the number of simultaneous drive elements of the data line load elements, and achieves reduction of power supply noise caused by driving the data line load elements by reducing the transient current. At this time, in addition to the column selection signal and the write enable signal, the write data to the memory cell is also referred to so as to selectively control the impedance of the corresponding data line load element. The number of load elements is further reduced to reduce the change in current when driving the data line load elements.

The write recovery control circuit selectively controls the operation of the corresponding write recovery element based on the write recovery signal and the write enable signal, which results in a change in current during write recovery immediately after data writing. To reduce power supply noise.
At this time, in addition to the write recovery signal and the write enable signal, the write data to the memory cell is also referred to so as to selectively control the impedance of the corresponding write recovery element. The number of elements is further reduced to reduce the change in current during write recovery.

[0015]

FIG. 5 shows a computer system including an SRAM which is an embodiment of the present invention. This system includes a CPU (Central Processing Unit) 401, a DRAM control unit 403, an SRAM 406, a system bus 400,
A ROM (Read Only Memory) 405, a peripheral device control unit 407, a display system 410, and the like are connected so that signals can be exchanged with each other. The CPU 401 is the logical core of the present system, and is mainly used for addressing, reading and writing of information, data operation, instruction sequence, acceptance of interrupts, activation of information exchange between a storage device and an input / output device, and the like. It has a function and is composed of various units such as an arithmetic control unit, a bus control unit, and a memory access control unit. A DRAM 402 controlled by the DRAM control unit 403 as an internal storage device, an SRAM 406 used as a main memory, a backup control unit 404 for controlling backup of the SRAM 406, and a ROM 4
05 is provided. The ROM 405 stores a program that does not require rewriting. The peripheral device control unit 407
Is not particularly limited, but functions as an interface of a peripheral device such as an external storage device 408, which is a magnetic storage device, and an input device, which is a keyboard (KB) 409. The display system 410 includes a VRAM (Video Random Access Memory) and its control circuit, and the display data transferred via the system bus 400 is synchronized with the CRT display device 412. It is output to 412. Further, a power supply unit 411 is provided, and various voltages generated here are supplied to each unit of the present system.

FIG. 6 shows the overall structure of the SRAM 406. This SRAM is not particularly limited,
32 kiloword x 32 bit 1M bit SRAM
And is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. In FIG. 6, 31 is a memory cell array in which a plurality of static memory cells are arranged in a matrix,
Select terminals of memory cells are coupled to word lines in each row direction, and data input / output terminals of memory cells are coupled to complementary data lines (also referred to as complementary bit lines) in each column direction. A column system peripheral circuit 34 includes a plurality of data line load circuits coupled to complementary data lines, a differential amplifier circuit for amplifying memory cell data, and a column system peripheral circuit 34 for selecting a column system. A column selection circuit and the like are included. Each complementary data line has a one-to-one correspondence with the complementary data line.
Are commonly connected to the complementary common data line via a plurality of column switches coupled together.

Addresses X0 to X7 input from the outside
Is transmitted to the X decoder and driver 30 via a buffer (not shown) arranged correspondingly. Further, the addresses Y0 to Y6 are transmitted to the Y decoder and driver 32 via a buffer (not shown) arranged corresponding to the addresses. Based on the output signal of the X decoder and driver 30, the word line corresponding to the input address signal is driven to the selection level. When a predetermined word line is driven, all the memory cells connected to this word line are selected. Further, the Y decoder and driver 32 turns on the column switch corresponding to the address signal supplied thereto, and brings the corresponding complementary data line into conduction with the complementary common data line. The memory cell data is output by the output circuit 3
It is made possible to output to the outside through 5. This output data is
Although not particularly limited, it has a 32-bit configuration and Do0 to Do0
This is indicated by Do31. A write control signal WTP for controlling the write pulse width and write data Di0 to Di31 are input to the write circuit 33. When write data Di0 to Di31 is applied from the outside, the complementary common data line is driven according to the write data, whereby the charge information corresponding to the data is supplied to a predetermined memory cell via the complementary data line selected by the address signal. Is accumulated.

FIG. 1 shows the memory cell array 50 of FIG.
6 and a detailed configuration example of the vicinity thereof are shown. In FIG. 1, only the circuits corresponding to the pair of complementary common data lines 20 and 21 are shown, but in reality, circuits having the same configuration are
It is formed corresponding to the number of simultaneous output bits (32 bits in the case of the present embodiment). Also, a set of common data lines 20,
A plurality of sets of complementary data lines are provided corresponding to No. 21, but in FIG.
12a and 13a and complementary data lines 12b and 1
The complementary data line indicated by 3b is representatively shown.
The complementary data lines 12a and 13a are connected via the column switch 22a, and the complementary data lines 12b and 13b are connected via the column switch 22b.
It is designed to be connected to 21. Column switch 2
Reference numerals 2a and 22b respectively constitute a part of the column peripheral circuit 34 shown in FIG. 6, and their operations are selectively controlled by the column selection signals 6a and 6b output from the Y decoder and driver 32, respectively. The common data lines 20 and 21 are connected to the write circuit 3 shown in FIG.
The write driver 5 belonging to 3 is coupled, and the complementary common data lines 20 and 21 are driven by the write driver 5. Data input / output terminals of representatively shown memory cells 1a and 1b are coupled to complementary data lines 12a and 13a. Select terminals of the memory cells 1a and 1b are coupled to the word line 3 in each row direction. When the word line 3 corresponding to the input address signal is driven to the selection level based on the output signals of the X decoder and the word driver 30 shown in FIG. 6, all the memory cells 1a and 1b coupled to this word line are driven. Is selected. When the column selection signal 6a or 6b is set by the Y decoder and driver 32 shown in FIG. 6, the corresponding column switch 22a or 22b is turned on, so that the complementary data lines 12a, 13a or 12b, 13b become common data. Connected to lines 20,21. When write data is applied through the write driver 5, the complementary common data lines 20 and 21 are driven according to the write data, and charges corresponding to the data are supplied to a predetermined memory cell via the complementary data line selected by the address signal. Information is accumulated. The data read from the memory cells 1a and 1b to the complementary data lines 12a, 13a and 12b, 13b are amplified by the differential amplifier circuits 2a and 2b, respectively, and then output to the outside via the output circuit 35. To be done.
Although not particularly limited, the differential amplifier circuits 2a and 2b are formed by differentially connecting bipolar transistors, and their operations are controlled by the column selection signals 6a and 6b, respectively. For example, the differential amplifier circuit 2a is selectively activated when the column selection signal 6a is set to the high level, and the differential amplifier circuit 2b is selected when the column selection signal 6b is set to the high level. Are activated.

The complementary data lines 12a and 13a have
Data line load circuits 24a and 25a for precharging the complementary data lines 12a and 13a are provided. Similarly, complementary data lines 12b and 13b are provided with data for precharging the complementary data lines 12b and 13b. Line load elements 24b and 25b are provided. The data line load circuits 24a, 25a, 24b, 25b are not particularly limited, but are two p-channel type MOS transistors connected in parallel with each other. For example, as a typical configuration example of the data line load elements 24b and 25a is shown, p-channel type MOS transistors 8a and p
The data line load element 24b is formed by connecting in parallel with the channel type MOS transistor 48a, and the data line load element 2 is formed by connecting the p-channel type MOS transistor 9a and the p-channel type MOS transistor 49a in parallel.
5a is formed. In the data line load circuit 24a,
The drain electrodes of the p-channel MOS transistors 8a and 48a are coupled to the data line 12a, and the source electrodes are coupled to the power supply Vdh. Further, the gate electrode of the p-channel type MOS transistor 48a is coupled to the power supply Vdl. In the data line load element 25a, the drain electrodes of the p-channel MOS transistors 9a and 49a are coupled to the data line 13a, and the source electrode thereof is the power supply Vdh.
Be combined with. Further, the gate electrode of the p-channel type MOS transistor 49a is coupled to the power supply Vdl. Here, when the high potential side power source voltage of ECL (emitter coupled logic) is 0 V and the low potential side power source Vee is -4 V,
The electric potential of the power source Vdh is set to -1.5 V,
The potential of dl is -3.3V, which is lowered to improve the memory operation speed. On the other hand, the gate electrodes of the p-channel type MOS transistors 8a and 9a are coupled to the data line load control circuits 26a and 26b, respectively. The data line load control circuit 26a outputs the data line load circuit 24a based on the column selection signal 6a, the write enable signal 7 for instructing the data writing to the memory cell, and the write data Di to the memory cell. The impedance is selectively controlled and is not particularly limited, but the column selection signal 6a, the write enable signal 7,
It is constituted by a logical product circuit for obtaining a logical product with write data Di to the memory cell. Similarly, the data line load control circuit 27a receives the column selection signal 6a, the write enable signal 7 for instructing the data writing to the memory cell, and the write data Di * (the logical inversion signal of Di) to the memory cell. Based on the data line load element 25a
Of the column select signal 6a, the write enable signal 7, and the write data Di * to the memory cell. That is, the p-channel MOS transistor 8a is controlled by the logical product output of the column selection signal 6a, the write enable signal 7, and the write data Di to the memory cell, and the p-channel MOS transistor 9a is controlled by the column selection signal 6a. , The write enable signal 7, and the write data Di * to the memory cell are controlled by the logical product output.

The data line load elements 24b and 25b coupled to the data lines 12b and 13b have the same structure as the data line load circuits 24a and 25a. In addition, the data line load control circuit 2 for controlling the data line load element 24b
6b includes a logical product circuit for obtaining a logical product of the column selection signal 6b, the write enable signal 7 for instructing the data writing to the memory cell, and the write data Di to the memory cell, and the data line Load element 25b
The data line load control circuit 27b for controlling the write operation obtains the logical product of the column selection signal 6b, the write enable signal 7 for instructing the data writing to the memory cell, and the write data Di * to the memory cell. It is composed of an AND circuit for.

FIG. 2 shows the operation timing of the main part of the circuit of this embodiment. In FIG. 1, the word line 3 is driven to the selection level, the memory cell 1a is selected by the column selection signal 6a, and the data line 12a side is pulled down to low level by the write data Di, so that the data is written in the memory cell 1a. Consider the case of writing.

The common data line 2 by the write driver 5
When 0 is pulled down to the write level, the write enable signal 7 is set to high level. Input data Di
Is set to the high level, the column selection signal 6a is set to the high level, and the write enable signal 7 is set to the high level, the output control signal 28a is changed to the low level until the logical product condition of the data line load control circuit 26a is satisfied. Is changed to high level. As a result, the p-channel type MOS transistor 8a serving as the data line load element is turned off, and the impedance between the source and drain thereof increases. p-channel MOS transistor 48a
Is fixed to the ON state at all times to prevent the floating of the data line, but the p-channel type MOS transistor 8a connected in parallel to it is turned off. As a result, the impedance of the data line load circuit 24a becomes p-channel. It becomes larger than that when the type MOS transistor 8a is on. As such, the data line load circuit 24a
Since the impedance of the data line 12a becomes large, the data line 12a can be easily pulled down to the low level.
It is possible to speed up the data writing such that 2a is set to the low level. In such data writing, since the data line 13a paired with the data line 12a is not pulled down to the low level, it is not necessary to change the impedance of the data line load circuit 25a coupled to this data line 13a. Therefore, in this embodiment, in the data line load circuit control, by checking the input data for writing, the impedance of the data line load circuit corresponding to the other data line of the complementary data line pair is not changed. I have to. That is, in the case of the above example, in the data line load control circuit 27a, the output control signal 29a, which is the logical product of Di * (the logical inversion signal of Di) is at the low level, remains at the low level. Therefore, the corresponding p-channel type MOS
The transistor 9a remains in the ON state.
When the column selection signal 6a is set to the high level and the column switch 22a is turned on, the other column switches sharing the common data lines 20 and 21 are not turned on. For example, when the column selection signal 6a is set to the high level, the column selection signal 6b is set to the low level, so that the data line load control circuit 26b,
Since the output control signals 28b and 29b of 27b are at low level, the impedances in the data line load circuits 24b and 25b are not changed. That is, the p-channel type MOS transistors included in the data line load circuits 24b and 25b continue to maintain the ON state because the control signals 28b and 29b are at the low level.

Next, consider the case where the write enable signal 7 is changed from the high level to the low level. As described above, the memory cell 1a is selected by the column selection signal 6a, and the data line 12 is further selected by the write data Di.
When data is written in the memory cell 1a by pulling the a side to the low level, the common data line 20,
Data line 12a of the plurality of data lines sharing 21
Since the impedance of only the data line load circuit 24a is controlled to be high in order to easily pull down only the data line load circuit 24a to the low level, when the write enable signal 7 changes from the high level to the low level, the data line load circuit 24a
The impedance of only a is controlled to be low. That is, when the write enable signal 7 is changed from the high level to the low level, the output control signal 28a of the data line load control circuit 26a is changed from the high level to the low level, which turns off the p-channel type MOS transistor 8a. From the ON state to the ON state, and the logic of the output control signal of the other data line load control circuits such as the data line load control circuits 27a, 26b and 27b is not changed.

According to the above embodiment, the following operational effects can be obtained. (1) As shown in FIG. 2, the data line load control circuit 2
At the timing a when the output control signal 28a of 6a rises, a transient current for charging the p-channel type MOS transistor 8a as the data line load element flows from the high potential side power supply, and therefore noise is generated in the high potential side power supply. Cheap. At the timing b when the output control signal 28b falls, contrary to the above case, a transient current for discharging the accumulated charge of the p-channel type MOS transistor 8a as the data line load element flows into the low potential side power source. Therefore, noise is likely to occur in the power supply on the low potential side. Here, in the method of simultaneously changing the impedance of the data line load elements in units of memory mats or memory blocks, in the data write operation to the memory cells, power supply noise is generated by the transient current when driving the data line load. In particular, since the amplitude of the voltage applied to the gate of the data line load MOS transistor is small under a low power supply voltage, it is necessary to increase the gate width of the data line load MOS transistor to obtain the required data line amplitude. As a result, the gate capacitance becomes large and a larger transient current flows.

On the other hand, according to the above-described embodiment, in the data writing, by controlling the impedance of the data line load circuit corresponding to only the data line which needs to be pulled down to the low level, the result can be obtained. In addition, since the number of p-channel type MOS transistors as the data line load elements simultaneously driven at the time of data writing can be significantly reduced, it is possible to simultaneously drive the p
The sum of the gate capacitances of the channel type MOS transistors can be significantly reduced, and as a result, the transient current for driving the data line load can be reduced, so that the power supply noise can be reduced. That is, although the voltage is lowered in order to improve the operation speed of the memory and the gate width of the p-channel type MOS transistor as the data line load element is increased in order to obtain the required data line amplitude, they are simultaneously driven. Since the number of data line load elements is reduced, power supply noise due to impedance control of the data line load circuit can be reduced. Further, the current consumption can be reduced by greatly reducing the number of p-channel type MOS transistors as data line load elements that are simultaneously driven when writing data.

(2) Then, since a high speed write operation can be performed under such a low power supply voltage and the power supply noise can be suppressed, the data mounted with such an SRAM as a main memory or a cache memory. In the processing device, the reliability of the stored data can be improved by improving the memory access speed by the CPU 401 and reducing noise.

FIG. 3 shows an SRA which is another embodiment of the present invention.
A configuration example of the main part of M is shown. In addition, in FIG.
Those having the same function as shown in FIG. In this embodiment, a p-channel MOS transistor is used as a data line load element as in the case of the above embodiment, and the data line is immediately pulled up to the potential of the read state immediately after writing, so-called write recovery. Write recovery circuit 42a for performing
43a, 42b, 43b and the write recovery circuit 4
Recovery control circuits 40a, 41a, 40b, 41b for controlling 2a, 43a, 42b, 43b are provided. The write recovery circuit is not particularly limited,
It is composed of bipolar transistors that can operate at high speed. As typically shown, the write recovery circuit 4
The emitter electrodes of the npn-type bipolar transistors 44a and 45a forming the transistors 2a and 43a are coupled to the data lines 12a and 13a, respectively, and the collector electrodes are coupled to the high potential side power source (ground line). The write recovery control circuit is composed of a logical product circuit for obtaining a logical product of the write recovery signal 4, the column selection signal 6a or 6b, and the data Di or Di *.

FIG. 4 shows the operation timing of the main part of the circuit of this embodiment. The complementary data lines 12a and 13a include
Data line load circuits 24a and 25a for precharging the complementary data lines 12a and 13a are provided, and similarly, complementary data lines 12b and 13b are used to precharge the complementary data lines 12b and 13b. The data line load elements 24b and 25b are provided, and by controlling the impedance of the data line load circuit corresponding to only the data line that needs to be pulled down to a low level during data writing, The reduction of the number of p-channel type MOS transistors as the data line load elements simultaneously driven at the time of data writing is the same as that of the above-mentioned embodiment.

The write recovery circuits 42a, 43a, 42b, 43b for rapidly raising the data line to the potential of the read state immediately after data writing are respectively provided with output signals of the recovery control circuits 40a, 41a, 40b, 41b. 46a, 47a, 46b and 47b are input. The write recovery signal 4 is generated in response to the rising edge of the write enable signal 7 in order to quickly pull up the data line to the potential of the read state. The column selection signal 6a is selected, and the data line 12 for writing the input data Di
Since a is lowered to the low level, only the output control signal 46a of the recovery control circuit 40a is changed. As a result, only the bipolar transistor 44a as the write recovery circuit 42a coupled to the data line 12a is turned on for the write recovery operation. That is, immediately after the data writing for pulling the data line 12a to the low level is performed, the write recovery is required only for the data line 12a, and the other data lines 13a, 12b, 13b, etc. are required for the write recovery. Therefore, the write recovery control circuits 40a, 41a,
Even though the write recovery signal 4 is set to the high level for 40b and 41b, the write recovery control circuits 41a, 40b and 41b do not turn on the bipolar transistor as the write recovery element. This is because the input data Di * is low level in the write recovery control circuit 41a, the column selection signal 6b is low level in the write recovery control circuit 40b, and the column selection signal 6b and input data are in the write recovery control circuit 41b. This is because both Di * are low level. Similarly, when data writing is performed such that the data line 13a is pulled down to a low level, only the write recovery circuit 43a coupled to the data line 13a is turned on and the other write recovery circuits are turned on. Not done.

When a huge number of write recovery elements are driven at the same time for write recovery immediately after data writing, as in the case of impedance control of the data line load circuit, a transient current flows, causing power supply noise. May occur. However, in the present embodiment, since the logical product of the write recovery signal, the column selection signal, and the input data line is obtained in order to drive the bipolar transistor as the write recovery element, immediately after writing the data. , Only the bipolar transistor corresponding to the data line selected for writing data can raise the corresponding data line to the potential of the read state at high speed, and the other bipolar transistor as the write recovery element is turned on. Not driven. In this way, by selectively driving the bipolar transistors for the write recovery, the number of simultaneously driven bipolar transistors in the write recovery can be reduced. Therefore, the write recovery can be performed for each memory mat or memory block. The transient current resulting from the write recovery operation can be reduced as compared with the case where the bipolar transistors as the protection elements are driven and controlled all at once. Therefore, similarly to the case of driving the data line load element described above, the power supply noise can be suppressed by reducing the instantaneous fluctuation of the power supply voltage level due to the transient current. That is, in the circuit of the present embodiment, the data line load driven simultaneously is controlled by controlling the impedance of the data line load circuit corresponding to only the data line that needs to be pulled down to a low level in data writing. Since the transient current is suppressed by reducing the number of p-channel type MOS transistors as elements, and in the write recovery, the transient current is suppressed by reducing the number of bipolar transistors simultaneously driven. It is possible to control the impedance of the data line load circuit and reduce the power supply noise caused by the write recovery operation.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention. Yes.

For example, in the above embodiment, the data line load control circuits 26a, 27a, 26b, 27b are designed to receive the input data Di, Di *, but this can be omitted. That is, in the above-mentioned embodiment, a 3-input logical product circuit is applied as the data line load control circuits 26a, 27a, 26b, 27b, but this is a 2-input logical product circuit and the input data Di and Di * are taken in. May be omitted. In this case, write enable signal 7
AND the column selection signal 6a (or 6b) is obtained. By involving the column selection signal in the data line load control, at least the data line load element corresponding to the data line in the column non-selected state is selected. Since impedance control is not required, even in that case, the number of simultaneously driven data line load elements is reduced, and the sum of the gate capacitances of the simultaneously driven p channel type MOS transistors can be reduced. As in the case of the above embodiment, the power supply noise can be reduced by reducing the transient current for driving the data line load.

In the above embodiment, the logical product of the write recovery signal, the column selection signal and the input data line is obtained in order to drive the bipolar transistor as the write recovery element. When the product is obtained, the input data Di and Di * may be omitted. For example, the write recovery control circuits 40a, 41a, 40b, 41b shown in FIG.
Can be configured by a 2-input AND circuit, and a logical product of the write recovery signal and the column selection signal can be obtained. Even in that case, since the column selection signal is involved in the write recovery control, it is not necessary to control the operation of at least the write recovery element corresponding to the data line in the column non-selected state. By reducing the number of elements, the power supply noise can be reduced by reducing the transient current for driving the data line load, as in the case of the above embodiment.

In the above embodiment, the write port and the read port are separated, but the write port and the read port can be used in common. That is, also in the reading of the memory cell data, the memory data read to the data line is transmitted to the common data lines 20 and 21 through the column switch, and the external output of the memory cell data is performed through the external terminal for both input and output. You may do it. Also in such a configuration, as described above, by selectively controlling the impedance of the data line load element and selectively controlling the operation of the write recovery element, the same operation as in the case of the above embodiment is performed. The effect can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip SRAM which is the field of application which is the background of the invention has been described. However, the present invention is not limited to this, and a single It can also be applied to an SRAM incorporated in a data processing device such as a chip microcomputer.

The present invention can be applied on the condition that at least a data line load element for precharging the data line is included.

[0037]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the data line load control circuit selectively controls the corresponding data line load element based on the column selection signal and the write enable signal to change the current when driving the data line load element. Can be reduced to reduce power supply noise caused by driving the data line load element. In addition to the column select signal and the write enable signal, the write data to the memory cell is also referred to, and the impedance of the corresponding data line load element is selectively controlled to selectively control the data line. The number of load elements can be further reduced to reduce the change in current when driving the data line load elements.

Then, when the write recovery is performed immediately after the data writing, the write recovery control circuit is provided to selectively control the operation of the corresponding write recovery element based on the write recovery signal and the write enable signal. The current change at the time of write recovery is reduced and the power supply noise is reduced. At this time, in addition to the write recovery signal and the write enable signal, the write data to the memory cell is also referred to, and the impedance of the corresponding write recovery element is selectively controlled to selectively control the write. By further reducing the number of recovery elements, it is possible to reduce the change in current during write recovery.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an SRAM according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of a main part of the SRAM.

FIG. 3 is a configuration block diagram of a main part of an SRAM which is another embodiment of the present invention.

FIG. 4 is an operation timing chart of a main part of an SRAM which is another embodiment of the present invention.

FIG. 5 is a block diagram of a configuration example of a data processing device including the SRAM.

FIG. 6 is an overall configuration block diagram of the SRAM.

[Explanation of symbols]

 1a memory cell 1b memory cell 2a differential amplifier circuit 2b differential amplifier circuit 3 word line 5 write driver 8a p-channel type MOS transistor 9a p-channel type MOS transistor 12a data line 12b data line 13a data line 13b data line 20 common data line 21 common data line 22a column switch 22b column switch 24a data line load circuit 24b data line load circuit 25a data line load circuit 25b data line load circuit 26a data line load control circuit 26b data line load control circuit 27a data line load control circuit 27b data Line load control circuit 30 X decoder and driver 31 Memory cell array 32 Y decoder and driver 33 Write circuit 34 Column system peripheral circuit 35 Output circuit 40a Write recovery control circuit 41a write recovery control circuit 40b write recovery control circuit 41b write recovery control circuit 42a write recovery circuit 43a write recovery circuit 42b write recovery circuit 43b write recovery circuit 44a bipolar transistor 45a bipolar transistor 48a p-channel MOS transistor 49a p-channel MOS transistor 402 DRAM 403 DRAM control unit 404 Backup control unit 405 ROM 406 SRAM 407 Peripheral device control unit 408 External storage device 409 Keyboard 410 Display system 411 Power supply unit 412 Display device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuo Tanba 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Sosuke Tsuji, 5-20-1 Mizumizuhonmachi, Kodaira-shi, Tokyo Hitate Super LSI Engineering Co., Ltd.

Claims (4)

[Claims] 1. A plurality of data lines coupled to data input / output terminals of a memory cell, and a plurality of data line load elements provided corresponding to the data lines for precharging the corresponding data lines. And a column switch for selectively coupling the data line to a common data line based on a column selection signal for column system selection, in the semiconductor memory device,
A semiconductor memory including a data line load control circuit for selectively controlling impedance of a corresponding data line load element based on a write enable signal for instructing data write to the memory cell. apparatus. 2. A plurality of data lines coupled to the data input / output terminals of the memory cell, and a plurality of data line load elements provided corresponding to the data lines and precharging the corresponding data lines. A semiconductor memory device including a column switch for selectively coupling the plurality of data lines to a common data line based on a column selection signal for selecting a column system,
A data line load control circuit for selectively controlling the impedance of the corresponding data line load element based on the write enable signal for instructing the data writing to the memory cell and the write data to the memory cell. A semiconductor memory device comprising: 3. A plurality of write lines provided corresponding to the plurality of data lines and for performing write recovery by driving the data lines to a potential level in a memory cell data read state immediately after writing data to the memory cells. Based on the write recovery element, the write recovery signal for instructing this write recovery operation, and the write enable signal for instructing the data writing to the memory cell, the operation control of the corresponding write recovery element is selectively performed. 3. The semiconductor memory device according to claim 1, further comprising a write recovery control circuit for performing the operation. 4. A plurality of write circuits provided corresponding to the plurality of data lines and for performing write recovery by driving the data lines to a potential level in a memory cell data read state immediately after writing data to the memory cells. Based on the write recovery element, a write recovery signal for instructing this write recovery operation, a write enable signal for instructing data write to the memory cell, and write data to the memory cell, a corresponding write operation is performed. 3. The semiconductor memory device according to claim 1, further comprising a write recovery control circuit for selectively controlling the operation of the recovery element.