JPH07141885A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the high speed of an operation, to attain a stable operation with high reliability, to increase number of writing bits larger than that of reading bits and to increase latitude of design. CONSTITUTION:In the case of writing data from data input lines DIN, DINI through writing transistors 2 into a cell 1 selected by a word line WL among cells 1 connected with a same bit pair BL NBL since only a first column decoder is present between a common data line pair DL, NDL and the bit line pair BL, NBL the floated voltages of low potential data are suppressed and then writings of data are performed surely. Further, the number of writing data bits can be formed larger than that of output data bits by enabling writing transistors 2 to write data having numbers of bits corresponding to the common data line pair DL, NDL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a random access type semiconductor memory device having two or more hierarchical column decoders.

[0002]

2. Description of the Related Art In a random access memory (RAM) capable of writing and reading data at random, memory cells are arranged in a two-dimensional (matrix) form, and memory cells at intersections of selected word lines and bit lines are arranged. In addition, it has a function of writing data given from the outside and reading data from this memory cell through a sense amplifier.

That is, when writing data, a word line is first selected by an address signal input from the outside, and a memory cell connected to the word line is selected. Here, the data inputted from the outside is outputted to the bit line pair selected by the write circuit through the common data line and written in the memory cell.

On the other hand, when reading data, a word line is first selected by an address signal input from the outside, and a memory cell connected to the word line is selected. Next, the selected memory cell outputs the data corresponding to the data stored in itself to the bit line pair. The data output on the bit line is transmitted on the common bit line pair via the column decoder, amplified by the sense amplifier, and output to the outside.

Here, a conventional semiconductor memory device will be described by taking a 4MSRAM as an example. FIG. 3 is a partial circuit configuration diagram of a conventional semiconductor memory device. As shown in the figure, a plurality of cells 1, 1, ... For storing data are connected to a bit line pair composed of a bit line BL and a bit line NBL (inverted signal line of the bit line BL). As the cell 1, for example, static type memory cells shown in FIG. 6 are used, and they are arranged in a matrix to form a memory cell array. In this memory cell array, a plurality of memory cells 1, 1, ... Which are arranged in the same column are connected to bit lines BL, NBL, and a plurality of memory cells arranged in the same row are arranged. A plurality of word lines WL (1), W
It will be selected by L (2), .... In the figure,
One bit line pair and two word lines WL (1), WL
Only (2) is shown. Now, the cell 1 (1) is selected by the word line WL (1). The column decode signals CD and CD are connected to the bit line pair to which the cell (1) is connected.
The first column decoder FCD to which I (inverted signal of the column decode signal CD) is applied, and the column decode signal C
A second column decoder SCD to which DP and CDPI (inverted signal of column decode signal CDP) are applied is connected. The bit lines BL and NBL are connected to the data line pair including the common data lines DL and NDL via the first column decoder FCD and the second column decoder SCD. The common data lines DL and NDL include a data input line DIN and a data input line DINI (data input line DIN
The write transistor 2 to which the inverted signal of 1) is input is connected.

The semiconductor memory device of FIG. 3 has 8 input / output bits. A double word line system is adopted as a word line selection system, and 512 main lines selected by addresses X1 to X9 are provided. Further, the section is divided into 32, and one section is composed of columns of 16 × 8 bits = 128. Then, as shown in FIG. 3, the column selection is performed by the first and second column decoders FC configured hierarchically.
D, SCD. That is, the first column decoder FCD is arranged in units of four columns, and the second column decoder is also arranged in units of four columns. That is, one of 16 columns is selected by the column decode signals CD, CDI and the column decode signals CDP, CDPI. With this configuration, the column selection is hierarchically performed by the first and second column decoders FCD and SCD, so that the number of column decode signals is reduced, the layout of the sense amplifier is facilitated, and the pattern area is reduced. There are advantages. For example, in the case of a one-stage column decoder, 32 decode signals are required, but one 2
If 6 columns are hierarchically selected, 16 column decode signals are enough. At this time, since the gate capacitance attached to the column decode signal line is reduced, the access time is shortened.

Here, the operation of writing data to the cell 1 (1) will be described. First, when the word line WL (1) is selected, the cell 1 (1) connected to it is selected. Also, one of the 16 columns is selected by the column decode signals CD, CDI of the first column decoder FCD and the column decode signals CDP, CDPI of the second column decoder SCD. A data input line DIN, which is generated according to write data input from the outside,
A set of write data input to DINI is shown in FIG.
As shown in the waveform diagram of (A), one is applied as a high potential and the other is applied as a low potential. Here, when the logical product signal of the section decode signal SD and the write signal WE is given, the write transistor 2 is selected. The write transistor 2 applies a high potential and a low potential to the data line pair of the common data lines DL and NDL, respectively, based on the data of the data input lines DIN and DINI. This common data line D
The data of L and NDL are transmitted to the bit lines BL and NBL via the first column decoder and the second column decoder.

As described above, the bit lines BL, NBL
When the data is applied to the cell 1, the data is written to the cell 1 (1) selected by the word line WL (1).

On the other hand, for reading data, the cell 1 (1) and the bit lines BL and NBL are selected by the same process, and the data from the cell 1 (1) is derived to the common data lines DL and NDL. Data is read through the sense amplifier.

[0010]

Here, to consider the data write operation, the data input lines DIN and DI will be described.
The data of NI is the write transistor 2 and the first and second column decoders FCD and SCD which are on.
Is transmitted to one of the bit lines BL and NBL via the line and applied to the cell 1. However, since the write transistor 2 and the transistors of the first and second column decoders have ON resistance, the potential on the low potential side of the line pair of the bit lines BL and NBL is the potential on the low potential side of the data input lines DIN and DINI. Will be much higher than That is, as shown in FIG. 4B, the low potential of the data transmitted to the bit lines BL and NBL is higher by ΔV1 than the low potential of the data supplied to the data input lines DIN and DINI.

When the potential on the low potential side of the bit line pair becomes high as described above, there is a problem that it becomes difficult to write data to the cell 1 because the cell 1 has asymmetry due to the influence of parasitic resistance. Occurs.

As described above, when the conventional semiconductor memory device is provided with two or more stages of column decoders, the on-resistance of the transistors of the column decoder raises the potential on the low potential side and the data is stored in the cell 1. There is a drawback that writing becomes difficult, which not only hinders improvement in access speed, but also causes a decrease in reliability.

Further, in the conventional semiconductor memory device, the number of input / output bits is the same (for example, both are 8 bits), and the number of input bits is different from the number of output bits. It is difficult to design a large number of configurations, and there is a problem that the degree of freedom in design for improving the access speed is low.

The present invention solves the above problems of the prior art,
It is an object of the present invention to obtain a semiconductor memory device which enables higher speed operation and stable and highly reliable operation, which allows the number of write bits to be larger than the number of read bits and has a high degree of freedom in design.

[0015]

A semiconductor memory device of the present invention includes a plurality of word lines for selecting a plurality of memory cells in the same row of a memory cell array arranged in a matrix and a plurality of word lines in the same column of the memory cell array. One of a plurality of bit line pairs, which are commonly connected to a plurality of memory cells and exchange data with the memory cells selected by the word line, and a predetermined number of the bit line pairs. Selectively corresponding to one of the plurality of first common data line pairs.
A first column decoder connectable to one of the memory cells and a first common data line pair, and to a selected memory cell based on data externally input via each data input line pair. A plurality of writing means for writing data, a second column decoder capable of selectively connecting one of the plurality of first common data line pairs to a second common data line pair, and the second column decoder A sense amplifier connected to the two common data line pairs and reading data from the selected memory cell via the first common data line pair and the second common data line pair. .

[0016]

When writing data, since only one column decoder (first column decoder) is interposed between the first common data line pair and the bit line pair, floating of the voltage of the low potential data is suppressed. Is surely written. Further, since the writing means can write the data of the bit number corresponding to the first common data line pair, the bit number of the write data can be made larger than the output data bit number.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention. As shown in the figure,
The first column decoder FCD to which the column decode signals CD and CDI are input is a bit line B to which the cell 1 is connected.
It is connected between L and NBL and common data lines DL and NDL to which the write transistor 2 is connected. On the other hand, the second column decoder to which the column decode signals CDP and CDPI are input is connected to the second common data lines SDL and SNDL connected to the common data lines DL and NDL. The logical product signal of the section decode signal SD, the column decode signal CDP, and the write signal WE is applied to the write transistor 2. Incidentally, although not shown, the second common data line SD
A sense amplifier for sensing and amplifying data from the cell 1 (see FIG. 6) is connected to L and SNDL. Besides, similarly to the configuration of FIG. 3, the first column decoder FCD to which the column decode signals CD and CDI are applied selects the bit lines BL and NBL from four bit line pairs including the bit lines BL and NBL. It is a thing. The second column decoder to which the column decode signals CDP and CDPI are applied is provided with the common data lines DL and ND from the four data line pairs including the common data lines DL and NDL.
This is to select L. Although not shown in FIG. 1, the number of write transistors 2 is four times that of the conventional circuit, but the column decode signals CD
I, CDP / CDPI and data input lines DIN / DI
Since the number of NIs is the same, the circuit of FIG. 1 can be realized with a layout pattern area almost the same as that of the conventional example.

The operation of the above-described structure will be described below.

First, the writing of data will be described. First, the word line WL (1) is selected, and the cell 1 (1) connected to this word line WL (1) is selected. Next, the second common data lines SDL, SNDL are selected by the column decode signals CDP, CDPI provided to the second column decoder SCD, and the common data lines DL, N are selected.
Connected to DL. At this time, the writing transistor 2 is turned on. Further, the bit lines BL and NBL are connected to the common data lines DL and NDL by the column decode signals CD and CDI provided to the first column decoder FCD. At this time, the write transistor 2 and the cell 1 are connected, and the data input lines DIN, DI are externally supplied.
Common data lines DL, N based on the data input to NI
DL becomes high potential and low potential. Then, external data is written in the selected cell 1.

Now, as a result of the above operation, FIG.
As shown in FIG. 2A, since only the first column decoder exists when writing data with respect to the high potential and low potential of the data on the data input lines DIN and DINI, as shown in FIG. The rise of the potential on the low potential side of the common data lines DL and NDL due to the on resistance of the transistors can be suppressed to ΔV2, and writing to the cell 1 can be reliably performed. By the way, as can be seen by comparing FIG. 2B and FIG. 4B, the second column decoder does not exist in the potential rise ΔV2 on the low potential side as compared with the conventional low potential rise ΔV1. It has been sufficiently suppressed.

When reading data, cell 1
The bit lines BL and NBL connected to (1) are selected by the first column decoder FCD to select the common data lines DL and N
Connect to DL. Further, the common data lines DL and NDL are set to the second
Selected by the column decoder SCD and connected to the second common data lines SDL and SNDL. This makes cell 1
Connect (1) to a sense amplifier (not shown),
The data of the cell 1 (1) is amplified and led to the outside.

As described above, a plurality of column decoders arranged hierarchically are arranged in a distributed manner, and one column decoder is interposed between the write transistor 2 and the cell 1, so that the low potential of write data is obtained. It is possible to suppress the floating of the data and enable reliable writing of data at high speed.

FIG. 5 is a partial circuit configuration diagram of a semiconductor memory device according to another embodiment of the present invention. As shown in the figure, a plurality of memory cells are connected to the bit lines BL and NBL of the column including the cell 1. Memory cells are word lines W
It is selected by selecting L1, WL2 ... Second common data lines SDL and SNDL are connected to the sense amplifier 4, respectively. Since eight sets of sense amplifiers 4 are provided corresponding to 8-bit output, the number of common data line pairs is eight in total. The column decode signals CDP1, CDP1,
Four sets of second column decoders SCD which are selectively operated by CDPI1, CDP2, CDPI2, ... Connect to 4. That is, eight data line pairs are selected in the entire section. Incidentally, 32 sets of common data lines are provided in the entire section. By the way, the 32 common data line pairs are connected to the data input lines DIN1-1, DINI1.
Four sets of data are input via -1, DIN1-2, DINII1-2, and data input lines DIN2-1, DIN.
4 through I2-1, DIN2-2, DINI2-2 ...
4 sets of X6 = 24 are input in the same way as the data of the set is input.
A set of data is input and given to 32 sets of write circuits 3 provided corresponding to each common data line pair. Each write circuit 3 has column decode signals CD1 and CDI.
1, CD2, CDI2 ... Are provided to four sets of first column decoders FCD and are connected to a bit line pair including bit lines BL and NBL. That is, since different sets of data input lines are connected to the 32 sets of write circuits 3 and each of them corresponds to a common bit line pair, it is possible to write in 32 bit units.

The operation of the above-described structure will be described below.

First, in writing data, one of the word lines WL (1), WL (2) ... Is selected and the memory cells 1, 1, connected to the selected word line are selected.
... is selected. At this time, all the write transistors 2 in the selected section are turned on by the signal input to the write circuit 3. Further, the column decode signal CD supplied to the first column decoder FCD
1, CDI1, CD2, CDI2 ... Select one bit line pair connected to the common data line pair via the first column decoder FCD. Here, since there are four common data line pairs, four of the 16 columns will eventually be selected. And 4 in one section
8 = 32 columns are selected. At this time, when 32-bit data is input from the outside, the common data line pair is set to high potential and low potential based on the input data, and data is written to the selected memory cell. As described above, 32-bit data is simultaneously written.

On the other hand, when reading data, one of the four bit line pairs is selected by the first column decoder FCD and connected to the common data line. Similarly, one of the four common data lines is selected by the second column decoder SCD and connected to the second common data line. Then, since the data in the memory cell is amplified and read through the sense amplifier 4 connected to the second common data line, 8-bit data is eventually read.

As described above, since 32-bit data can be simultaneously written at the time of writing, the write operation can be speeded up and the memory cell can be accessed at high speed.

[0029]

As described above, according to the semiconductor memory device of the present invention, it is possible to surely write data in the memory cell array in which the column decoder is hierarchized, so that the access speed is increased and the reliability is increased. Since it is possible to increase the number of bits of write data with respect to the number of bits of read data, there is an effect that a higher speed operation can be realized.

[Brief description of drawings]

FIG. 1 is a partial circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the configuration of FIG.

FIG. 3 is a partial circuit configuration diagram of a conventional semiconductor memory device.

FIG. 4 is a waveform diagram for explaining the operation of the configuration of FIG.

FIG. 5 is a partial circuit configuration diagram of a semiconductor memory device according to another embodiment of the present invention.

FIG. 6 is an example of a static memory cell.

[Explanation of symbols]

 1 cell 2 write transistor 3 write circuit 4 sense amplifier BL, NBL bit line WL, WL1, WL2 word line DL, NDL common data line SDL, SNDL second common data line

Claims (3)

[Claims] 1. A plurality of word lines that select a plurality of memory cells in the same row of a memory cell array arranged in a matrix and a plurality of word lines that are commonly connected to a plurality of memory cells in the same column of the memory cell array. A plurality of bit line pairs for exchanging data with a memory cell selected by a line and one of a predetermined number of the bit line pairs are selectively selected. A first column decoder connectable to a corresponding one of the common data line pairs, and data input to the first common data line pairs from the outside via each data input line pair. A plurality of write means for writing data to the selected memory cell, and one of the plurality of first common data line pairs is selectively changed to a second common data line pair. Second connectable A column decoder, and a sense amplifier connected to the second common data line pair for reading data from the selected memory cell via the first common data line pair and the second common data line pair. A semiconductor memory device comprising: 2. The device according to claim 1, wherein the control of the writing means is performed by a control signal based on a decode signal input to the first column decoder. 3. The number of the data input line pairs is greater than the number of output buffers for outputting data to the outside.
The described device.