JP2002074965A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize supermultiple bit read-out operation of a semiconductor memory without increasing the chip size. SOLUTION: This memory is a semiconductor memory provided with a read- only data port, and also provided with an address decoder decoding an address signal and outputting a read-word signal corresponding to this signal, and a memory array having plural words selected by the read-word signal. Plural words of the memory array are simultaneously selected, data stored in this selected plural words are read out simultaneously through a read-only data port.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory capable of super-multi-bit parallel reading required for a driver of an LCD (Liquid Crystal Display) or the like.

[0002]

2. Description of the Related Art For example, in a display memory used in an LCD driver, it is necessary to simultaneously drive data of a column (segment) corresponding to a row (common).
Super multi-bit parallel read operation is required. However, since the number of bits per word is large in a semiconductor memory that requires a super-multi-bit parallel read operation, if memory cells corresponding to the number of bits of one word are arranged in one direction, the memory array becomes extremely elongated, Physically difficult to manufacture.

Due to the physical memory size restriction described above, the LCD driver implements a super-multi-bit parallel read operation by reading data from the display memory in a time-division manner and temporarily storing the previously read data in a register. are doing. Therefore, in applications that require a super-multi-bit parallel read operation, such as a display memory used in an LCD driver, a large number of extra circuits such as registers are required, resulting in an increase in chip area. .

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory which solves the problems of the prior art and realizes a super-multi-bit read operation without increasing the chip size. .

[0005]

In order to achieve the above object, the present invention provides a semiconductor memory having a read-only data port, which decodes an address signal and outputs a read word signal corresponding thereto. An address decoder and a memory array having a plurality of words selected by the read word signal, wherein a plurality of words of the memory array are simultaneously selected by the read word signal, and the plurality of words selected at the same time are selected. It is another object of the present invention to provide a semiconductor memory wherein stored data is simultaneously read out through the read-only data port.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a schematic diagram showing the configuration of an embodiment of a semiconductor memory according to the present invention. The semiconductor memory 10 shown in FIG.
As an example, it outputs two words of data simultaneously, and includes a memory array 12, a read / write address decoder 14, and a read-only address decoder 16. Further, the semiconductor memory 10 has two data ports as a data port, a read / write port and a read-only port.

In the illustrated example of the semiconductor memory 10, the read / write port is a data port used to read / write data from / to the memory array 12 from an MPU (central processing unit). In the case of the example shown,
The read / write port is connected to a bit line B provided corresponding to each bit string i (0 ≦ i ≦ n) of the memory array 12.
L (i) and bit bar line / BL (i) (n
+1) bit line pairs.

On the other hand, the read-only port is a data port used for performing super-multi-bit parallel reading of data from the memory array 12. In the illustrated example, in order to simultaneously read two words of data, a read bit line RBL0 (i) provided corresponding to each bit string i of the even words 0, 2,. Read bit lines RBL provided corresponding to bit strings i of odd words 1, 3,.
1 (i).

In the semiconductor memory 10, the memory array 12 has (m + 1) words.times. (N + 1) bits of memory cells MC arranged in an array. In the figure, memory cells MC of (n + 1) bits per word are arranged in a row in the horizontal direction, and (m +
1) Memory cells MC of a bit corresponding to each word are arranged in a line. In this embodiment, two vertically adjacent two
Word data is read simultaneously from the read-only port.

Subsequently, an address decoder 14 for both reading and writing decodes an address signal (not shown) for designating a word in the memory array 12 from which the MPU performs reading / writing, and outputs a corresponding word signal to a word line. WL (j) (0 ≦ j ≦ m). Word line WL
(J) is commonly connected to (n + 1) -bit memory cells MC constituting one word, and the MPU is connected to the bit line BL.
(I) and data reading / writing of one word is performed via the bit bar line / BL (i).

On the other hand, a read-only address decoder 1
6 is a memory array 12 for performing super-multi-bit parallel reading
And decodes an address signal (not shown) for designating a plurality of words and outputs a corresponding read word signal to the plurality of read word lines RWL (j). In this embodiment, one read word signal is distributed to two read word lines RWL, and the read bit lines RBL0 (i),
Data of a total of two words is read from RBL1 (i).

In the illustrated example, one read word signal is applied to two read word lines RWL (j) and RWL (j +
Although distributed to 1), the present invention is not limited to this, and a plurality of words may be specified at the same time by a read word signal that specifies a plurality of words to be read simultaneously. Further, FIG.
Although the AND gate and the inverter are conceptually shown, any conventionally known address decoder can be used.

Next, referring to FIG. 2, the memory cells MC constituting the memory array 12 will be described with reference to specific examples. FIGS. 2A and 2B are circuit diagrams each showing an embodiment of a memory cell applicable as a semiconductor memory according to the present invention. First, the memory cell MC1 shown in FIG. 1A includes an SRAM cell 18 and a read circuit 20a having a static configuration.

In the memory cell MC1, the SRAM cell 18 holds one-bit data, and has two inverters 22 and 24 connected in a ring by connecting their output terminals to the other input terminal. Each inverter 2
2 and 24 connected between the input terminals of the transistors 2 and 24 and the bit line BL and the bit bar line / BL.
8 is provided. The gates of these two transistors 26 and 28 are commonly connected to a word line WL.

The read circuit 20a converts the data held in the memory cell MC1 into a read bit line RBL.
And an inverter 30 and a transistor 32. The input terminal of the inverter 30 is connected to the output terminal of the inverter 24 constituting the SRAM cell 18. The transistor 32 is connected between the output terminal of the inverter 30 and the read bit line RBL, and has a gate connected to the read word line RWL.

In the memory cell MC1, the bit line BL and the bit bar line / BL are driven by data to be written by the MPU, and when the word line WL is set to the high level, the data is transferred to the SRAM cell 18 via the transistors 26 and 28. Written. On the other hand, if the word line WL is set to a high level without driving the bit line BL and the bit bar line / BL, the data held in the memory cell MC1 is transferred to the bit line BL and the bit bar line via the transistors 26 and 28. / BL.

The data held in the memory cell MC1 is read to the read bit line RBL by the read word line RBL.
This is performed by controlling WL. That is, when the read word line RWL goes to the high level in the active state, the transistor 32 of the read circuit 20a is turned on, and the data held in the SRAM cell 18 is read by the read bit via the inverter 30 and the transistor 32 in the on state. Read to line RBL.

On the other hand, the memory cell MC2 shown in FIG.
In the memory cell MC1 shown in FIG. 5A, a read circuit 20b having a dynamic configuration is used instead of the read circuit 20a having a static configuration. In other words, the configuration of the SRAM cell 18 is the same as that of the memory cell M
C1 and the memory cell MC2 are completely the same, and therefore, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted.

The read circuit 20b includes two transistors 32 and 34 connected in series between the read bit line RBL and the ground, as shown in FIG.
The output terminal of the inverter 24 constituting the SRAM cell 18 is connected to the gate of the transistor 34, and the read word line RWL is connected to the gate of the transistor 32. Although not shown, the read bit line R
The BL is provided with a precharge circuit.

In the illustrated memory cell MC2, an SRAM
Before the data held in the cell 18 is read from the read-only port, the read bit line RBL is precharged by the above-described precharge circuit.

When the read word line RWL changes to the active high level, the transistor 32 of the read circuit 20b turns on. At this time, depending on the level of the data held in the SRAM cell 18, the transistor 3
When 4 is on, the read bit line RBL is discharged via the transistors 32 and 34 and the low level is read. Conversely, when the transistor 34 is off, the precharged high level is read out to the read bit line RBL.

The specific configuration of the memory cell MC used in the semiconductor memory 10 of the present invention is not limited at all.
For example, in addition to RAM such as SRAM and DRAM, EPRO
All conventionally known memory cells having various configurations such as ROMs such as M and EEPROM can be applied. Further, the configuration of the read circuit is not limited at all, and any circuit configuration may be used as long as data stored in the memory cell MC can be output to the read-only port.

In the semiconductor memory 10 shown in FIG.
From the bit line BL (i) and the bit bar line / BL
Through (i), data reading / writing is performed for each word of the memory array 12 in units of one word. On the other hand, the reading of the data held in the memory array 12, that is, the super multi-bit parallel reading is performed by the read bit lines RBL0 (i) and RBL1 (i).
In this embodiment, the processing is performed in units of two words.

From the read-only address decoder 16, one read word signal is supplied to two read word lines R
Output to WL (j). As shown in FIG. 1, for example, a read word line RWL is generated by one read word signal.
(0) and RWL (1) are simultaneously selected, and the data stored in the two simultaneously selected words are read bit lines RBL0 (i) and RBL0 (i), respectively.
Output simultaneously via RBL1 (i).

The semiconductor memory of the present invention selects a plurality of words at the same time and reads out the data held in these simultaneously selected words via a read-only port, thereby achieving a super multi-bit parallel read. The operation is realized. Therefore, since the number of bits per word is the same as that of a conventional semiconductor memory, it can be physically manufactured by the current manufacturing technology, and there is no need for a separate circuit such as a register, so that the chip size does not increase.

The semiconductor memory of the present invention can be suitably used for applications requiring an ultra-multi-bit parallel read operation, such as an LCD driver. Note that the present invention is not limited to the LCD driver, but can be applied to any application requiring an ultra-multi-bit parallel read operation. In the embodiment, two words are selected and read at the same time, but the present invention is not limited to this.
If necessary, a plurality of words of two or more words may be selected at the same time.

The semiconductor memory of the present invention is basically as described above. As described above, the semiconductor memory of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. .

[0029]

As described above in detail, in the semiconductor memory of the present invention, a plurality of words in a memory array are simultaneously selected by a read word signal, and data stored in the plurality of simultaneously selected words is read. Are simultaneously read through a read-only data port. According to the semiconductor memory of the present invention, the number of bits per word may be the same as that of the conventional semiconductor memory, so that the semiconductor memory can be physically manufactured by the current manufacturing technology, and it is not necessary to separately provide a circuit such as a register. Therefore, it is possible to realize a semiconductor memory capable of performing a super-multi-bit parallel read operation without increasing the chip size.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a configuration of an embodiment of a semiconductor memory of the present invention.

FIGS. 2A and 2B are circuit diagrams each showing an embodiment of a memory cell applicable to a semiconductor memory according to the present invention; FIG.

[Explanation of symbols]

 Reference Signs List 10 semiconductor memory 12 memory array 14, 16 address decoder 18 SRAM cell 20a, 20b readout circuit 22, 24 inverter 26, 28, 34 transistor MC, MC1, MC2 memory cell WL word line RWL read word line BL bit line / BL bit bar Line RBL0, RBL1 Read bit line

Claims (1)

[Claims] 1. A semiconductor memory having a read-only data port, comprising: an address decoder for decoding an address signal and outputting a read word signal corresponding to the address signal; and a plurality of words selected by the read word signal. A plurality of words of the memory array are simultaneously selected by the read word signal, and data stored in the plurality of simultaneously selected words are simultaneously transmitted through the read-only data port. A semiconductor memory characterized by reading.