JPH0728435A - Display control system - Google Patents

Abstract

PURPOSE:To construct a display controller division displaying the image data by one picture to plural pictures without increasing a cost. CONSTITUTION:By an address conversion circuit 19, the address data storing the image data of individual flat display are converted, and are remapped on the address of one piece of frame memory 10 for displaying two sets of flat displays by one piece of frame memory 10. and for being seen from an application side so that one piece of frame memory 10 dealing with one piece of flat display is in one to one correspondence relation. The address mapping is controlled according to the data transferred from a main body CPU through a register 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention allows a large amount of image data to be recorded.
The present invention relates to a display control system capable of performing divided display using a set of flat displays, and particularly suitable for use in an electronic notebook size personal computer.

[0002]

2. Description of the Related Art In recent years, in the field of personal computers, laptop type, which is small, lightweight and convenient for carrying, has become the mainstream in place of the desktop type. It has been spurred on. Due to its characteristics, this kind of personal computer is driven by a battery, and a flat panel display such as a liquid crystal (LCD) is used as a display device.

Conventionally, in this type of personal computer, when image data is displayed on two sets of LCDs, the image data is stored in the one set of LCDs.
Since two sets of display memory are needed, two sets of display memory are required as a result. The same applies to the display controller.

[0004]

As described above, in the prior art, when displaying data on two LCDs,
Two sets of display memory are required. Since this kind of display memory is extremely expensive, it is against the reduction of the product cost, and it is difficult to apply it in the field of personal computers. In the field of small information processing equipment such as personal computers, when image data of one screen must be divided and displayed on two sets of display devices, cost reduction is essential, and bottles are required for commercialization. It was a neck.

On the other hand, in the above-mentioned small-sized information processing equipment, the displayable area becomes smaller as the display screen becomes smaller. However, if the characters or figures to be displayed become small to some extent, the usability becomes poor. Therefore, the image data of one screen is divided and displayed using a plurality of display screens.

The present invention has been made in view of the above circumstances.
An object of the present invention is to provide a display control method that realizes split screen display at low cost by adding a small amount of hardware to a display control device.

[0007]

According to the present invention, there is provided a central processing unit, and a display memory which stores image data for one screen generated by the central processing unit and supplies the image data to a plurality of flat displays. In an information processing device having a display control circuit for controlling display of one screen of image data on the plurality of flat displays, the display control circuit stores one screen of image data stored in a display memory. For split display on multiple flat displays,
An address conversion circuit that converts an address at which image data to be supplied to each flat display is stored and maps it in a display memory is provided, and one screen of image data is displayed in the display memory according to the address output by the address conversion circuit Is written, and image data to be displayed on each flat display is sequentially read from the display memory for each line, and desired screen division display is performed.

Further, according to the present invention, the bit information of a predetermined memory address corresponding to each dot of the flat panel display is stored in the display memory, and the address supplied from the outside in accordance with a predetermined formula in the address conversion circuit. It is characterized in that the addresses are converted and the addresses are rearranged in the display memory.

[0009]

According to the present invention, the display control circuit for dividing and displaying the image data for one screen of the display image is provided in the two sets of the display control circuits in the two sets of the flat displays with the one set of the display memories. The present invention is characterized in that two sets of flat displays are divided and displayed without modifying and adding conventional image data by software.

Therefore, an image data storage means for storing individual image data for two sets of flat displays in one set of display memory is provided in the display control circuit, whereby software can be provided for each flat display. The individual screen data being displayed can be programmed as if they were stored in the display memory provided for each flat display.

Further, according to the present invention, since two sets of LCDs are displayed by one frame memory, one frame memory corresponding to one flat display has a one-to-one relationship. It must be visible from the side. Therefore, the address conversion circuit converts the address data in which the image data of each flat display is stored and remaps it to the address of one frame memory.

According to the present invention, it is possible to easily display the image data of one screen on a plurality of screens while suppressing the cost increase, and to commercialize a small-sized information processing device equipped with a plurality of screens, Realization can be accelerated.

[0013]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention. In the figure, reference numeral 1 is an input / output buffer (I / O
It is a buffer) and has a function of temporarily storing data exchanged with a main body CPU (not shown). Reference numeral 2 is an input / output control circuit (I / O control circuit), which is a circuit portion for controlling the input / output direction.

Reference numeral 3 is a control data line through which input / output control data is transferred from the main body CPU. Reference numeral 4 is a data bus, through which data and addresses are transferred to and from the main body CPU. Reference numeral 5 is a data line, through which data is transferred between the input / output buffer 1 and a register 8 described later. Reference numeral 6 is a control line to which a signal for controlling the buffer 1 is transferred.
Reference numeral 7 is a control line to which a signal for controlling the register 8 is transferred.

Reference numeral 8 is a register in which data indicating the status (state) of the entire display control circuit shown in FIG. 1 is set. Reference numeral 9 is a data line in which data to be written is stored in the frame memory 10. Reference numeral 91 is an address line, and the address information of the data to be written in the frame memory 10 is transferred via this line 91.

Reference numeral 10 is a frame memory, which is an LCD
It is a memory that stores image data to be displayed on the screen. Code 1
Reference numeral 1 is a data line, to which the data output from the frame memory 10 is transferred. Reference numeral 12 is a data conversion circuit, which converts data output from the frame memory 10 from parallel to serial. Reference numeral 13 is a data line to which the display data converted by the conversion circuit 12 is transferred. Reference numeral 14 is a control line, and a signal for selecting which of the two sets of LCDs to output the data is transferred. Reference numeral 15 is a selection circuit, which controls the output of the data line 13 by a signal transferred through the control line 14.
Reference numeral 16 is a data line, which is display data for one LCD (A). Reference numeral 17 is a selection circuit,
Data line 1 depending on the signal transferred on control line 28
3 output is controlled. Reference numeral 18 is a data line,
It becomes the display data for the other LCD (B).

Reference numeral 19 is an address conversion circuit, which is a circuit for converting an address to the frame memory 10 by a signal transferred through the control line 21 which is the output of the register 8. Reference numeral 20 is an address line, and the address converted by the address conversion circuit 19 is transferred. Reference numeral 21 is a control line, to which the control data output from the register 8 is transferred. Reference numeral 22 is an address line, and the selected frame address is transferred via the selection circuit 23. Reference numeral 23 is a selection circuit, which is a circuit for controlling the address (91) from the register 8 by a signal output via the control line 21. Code 2
Reference numeral 4 is a control line to which a refresh control signal output by a refresh counter 241 described later is transferred.

Reference numeral 25 is a timing generator, which is an LC
A display timing clock for D is generated. Reference numeral 26 is a timing signal line to which the timing signal generated by the timing generator 25 is transferred.

Reference numeral 27 is a control circuit, which is a circuit for adjusting the timing under the control of the register 8. Reference numeral 28 is a control line, which is a pair of LCDs.
A signal for selecting which of (A) and (B) the data is output is transferred. Reference numeral 29 is a signal line to which the timing signal is transferred, and the timing signal adjusted by the control circuit 27 is transferred.

Reference numeral 30 is a selection circuit, and the control line 1
4 is a circuit that controls the timing output according to the signal transferred via the circuit 4. Reference numeral 31 is a selection circuit, which is a circuit for controlling the timing output by a signal transferred through the control line 28. Reference numeral 32 is a signal line for supplying a timing signal to one LCD (A), and reference numeral 33 is a signal line for supplying an LCD timing signal to the other LCD (B).

2 to 5 are views for explaining the operation of the embodiment of the present invention. FIG. 2 is an example showing the address mapping of the frame memory. In the figure, reference numeral 34 is a data string, and 8 bits of image data are shown as one string. Reference numeral 35 is a frame memory, which is a memory map for storing image data. Code 3
6, 37, 38, 39 and 40 are addresses, respectively, which are mapped in the frame memory.

FIG. 3 is a diagram showing an example of a frame memory mapping method according to the present invention, and shows how a frame address viewed from an application is converted into an actual frame address.

In the figure, reference numerals (41), (42),
(44) and (45) are calculation formulas for address mapping, respectively. Reference numerals 43, 46, and 47 are frame memories, and show memory maps for storing image data of which addresses are converted according to the above-described calculation formula. Reference numerals 48, 49, 50, and 51 are addresses, respectively, and indicate respective addresses mapped in the frame memories 43, 46, and 47.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention. In the figure, reference numeral 52 is a frame pulse (FP), which is one frame control signal of the LCD. Reference numerals 53 and 54 are latch pulses (LP),
This is a 1-line control signal for the LCD. Reference numerals 55 and 36 are shift clocks (SCK), which are 1-dot control signals for the LCD. Reference numerals 57 and 58 are image data for each LCD.

FIG. 5 shows an example of displaying an image according to the present invention on two sets of LCDs (A) and (B). In the figure, reference numerals 59, 62 and 64 are LCD screens respectively, and reference numeral 60 is a minimum unit dot constituting the LCD.
It becomes one pixel of D. Reference numerals 61, 63, 65, 66, 67
Are character strings, and show examples of actual display characters.

The operation of the embodiment of the present invention shown in FIG. 1 will be described below with reference to FIGS. First, image data and addresses generated by a main body CPU (not shown) are input to the input / output buffer 1 via bus signal lines 4 such as address lines and data lines connected to the main body CPU. Further, the data 3 of the input / output control line that arrives to control the input / output (peripheral device) is input to the input / output control circuit unit 2 that controls the input / output of data.

The contents temporarily stored in the input / output buffer 1 are sent to the register 8 via the data line 5 under the control of the input / output control circuit 2. Further, a signal for controlling the register 8 is output from the input / output control circuit unit 2 via the control line 7. For LCD not shown,
Image data is written to the frame memory 10 via the data line 9 in order to display characters and figures.

As a write address for writing the image data in the frame memory 10, the control data is output from the register 8 via the control line 21 and is input to the address selection circuit 23 and the address conversion circuit 19, and the address is the address line 91, An arbitrary frame address is determined through 22 and 20, and is supplied to the frame memory 10. In addition, in order to refresh the data written in the frame memory 10, the refresh counter 241
From this, a refresh signal (signal line 24) is generated.

The image data written in the frame memory 10 is the address selection circuit 23 and the address conversion circuit 1.
When an arbitrary address is selected by 9, it is output to the parallel-serial conversion circuit 12 through the data line 11. In the embodiment of the present invention, the data converted here is input to the LCD selection circuits 15 and 16 because two sets of LCDs (A) and (B) are connected to the controller. Further, the clock for controlling the display of the LCD is generated by the timing generator 25, and is supplied via the signal line 26 to the refresh counter 241 and the timing control circuit 2.
Input to 7. The timing control circuit 27 is supplied with control data in advance via the control line 21 for determining which of the two LCDs to display and which one to display.

Here, if any LCD is selected, the selection data selects one of the selection circuits 30 and 31 by the control lines 28 and 14, and the selected LCD is
The display timing is output via the data lines 32 and 33. Similarly, the selection data generated by the control circuit 27 selects one of the selection circuits 15 and 17 selected via the signal lines 14 and 28, respectively, and the image data is output via the data lines 16 and 18. , Image information is displayed on the selected LCD.

FIG. 2 shows an example of address mapping of the frame memory according to the present invention. In the embodiment of the present invention, an LCD having 640 × 400 dots is illustrated in FIG. The frame memory 35 stores bit information of a predetermined memory address corresponding to each bit of the LCD. One memory address has 8 bits to form one address (reference numeral 34). Therefore,
The first 8 bits of the 1st line are address 0 (reference numeral 36)
The first 8 bits of the second line are the address 50H (reference numeral 37), and the last 8 bits of the second line are 9FH.
It can be represented by an address (reference numeral 38).

A case where this is divided into two screens is shown in FIG. 640x400 dot screen, 320x on the left side
In the case of equally dividing into 400 dots (b-1) and 320 × 400 dots (b-2) on the right side, one frame memory 35 represents the dot information of two sets of LCDs, and therefore the left side (b-1 The first 8 bits of the first line of) is the same address 0 (reference numeral 36) as in (a), but the first 8 bits of the second line is 28H (reference numeral 39). Similarly,
The first 8 bits of the first line on the right side (b-2) is the address 0, the last 8 bits of the first line is the address 27H, and the last 8 bits of the second line is the address 4F (reference numeral 40). Becomes

According to the above description, two image data on the left side (b-1) and the right side (b-2) can be stored in one frame memory. FIG. 3 shows the mapping method of the frame memory by means of equations and further on the memory map. In the embodiment of the present invention, two sets of LCDs are used.
LCD for displaying on one frame memory
It is necessary for the application side to be able to see that one frame memory corresponding to is in a one-to-one relationship. Therefore, it is necessary to convert the address data in which the image data of each LCD is stored and remap it to the address of one frame memory. FIG. 3 shows the method of re-masting. Here, assuming that the individual display addresses are A and B, equations (reference numeral 41) to (reference numeral 42) and expressions (reference numeral 44) to (reference numeral 4).
By 5), it can be converted into one frame memory address.

For example, the address A (reference numeral 48) on the frame address (reference numeral 43) side of 320 × 400 dots is
The address XA of the frame address (reference numeral 47) of 640 × 400 dots according to the equations (reference numeral 41) to (reference numeral 42)
(Reference numeral 50). Similarly, for the frame address on the (reference numeral 46) side, the address B (reference numeral 49) is also converted into the address XB (reference numeral 51). By the above conversion method, it seems that the application side controls the image data in each frame memory, so the programming can be done without being aware that two LCDs are composed of one frame memory. You can do it.

FIG. 4 shows the driving timing of the LCD according to the present invention. Embodiments of the present invention include two sets of 32.
The description is given for the LCD of 0 × 400 dots. Reference numeral 52 denotes a frame pulse, which indicates the start of display for each screen by outputting a pulse for each screen. Reference numerals 53 and 54 are latch pulses, which indicate the start of display for each line by outputting a pulse for each display line. Reference numerals 55 and 56 are shift clocks, which output a pulse for each dot and control the image data for each dot. Reference numerals 57 and 58 are image data, and the image data of each dot is output by the shift clocks 55 and 56.

FIG. 5 shows an example of the screen display according to the present invention. That is, a case where a 640 × 400 dot LCD is equally divided into two screens and displayed on two sets of 320 × 400 dot LCDs is shown. Reference numeral 60 is an enlarged display of a part of the dots. In addition, "Toshiba Ome Factory Development No. 5
When "part" (61) and a character string are displayed, a character string such as 63, 65 is obtained by dividing into two. By LCD, L
It is possible to display "aiueo" (66) on the CD 62 and "information processing and device technology laboratory" (67) on the LCD 64, and a character string for each LCD.

The embodiment of the present invention uses an LC as a display device.
Although description has been made using D, the present invention can be similarly applied to other flat panels such as plasma displays. Further, although the LCD size has been described by exemplifying 640 × 400 dots, the same can be applied to 640 × 480 dots which is a standard display size of VGA (video graphics array). Further, although the embodiment of the present invention has been described by taking two divisions as an example, the present invention is not limited to this and can be applied to a plurality of division methods.

[0038]

As described above, according to the present invention, by devising the structure of the display control circuit, the image data for one screen of the image data to be displayed on two sets of flat displays in one set of display memory. Can be displayed. Thereby, the image data of one screen can be divided and displayed on a plurality of screens, which can be easily realized while suppressing the cost increase. In particular, by adopting the present invention to a small-sized information processing device, image data of one screen can be easily divided and displayed on a plurality of screens, and commercialization of a small-sized information processing device equipped with a plurality of screens is promoted. It

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an example of address mapping of a frame memory for explaining the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing an address mapping unit of a frame memory for explaining the operation of the embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the embodiment of the invention.

FIG. 5 is a diagram showing a screen display example for explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

1 ... I / O buffer, 2 ... I / O control circuit, 8 ... Register, 10 ... Frame memory, 12 ... Data conversion circuit, 1
5, 17, 23, 30, 31, ... Selection circuit, 19 ... Address conversion circuit, 25 ... Timing generator, 27 ... Control circuit, 241 ... Refresh counter.

Claims (2)

[Claims] 1. A central processing unit, a display memory for storing one screen of image data generated by the central processing unit, and supplying the image data to a plurality of flat displays, and one for the plurality of flat displays. In an information processing device having a display control circuit for controlling display of image data for one screen, the display control circuit divides and displays one screen of image data stored in a display memory on a plurality of flat displays. In order to do so, an address conversion circuit for converting the address at which the image data to be supplied to each flat display is stored and mapping it in the display memory is provided, and one screen is displayed in the display memory according to the address output by this address conversion circuit. Image data to be written on each flat display from the above display memory for each line. A display control method characterized by sequentially reading out image data and performing desired screen division display. 2. A display memory stores bit information of a predetermined memory address corresponding to each dot of a flat display, and an address conversion circuit converts an address supplied from the outside according to a predetermined formula to display the display memory. The display control method according to claim 1, wherein the address is rearranged.