JPH0728411B2 - Phase shift circuit - Google Patents

Description

The present invention relates to a phase shift circuit.

[Outline of Invention]

This invention divides the original signal by half in the phase shift circuit,
The divided output is supplied to the flip-flop through the gate, and the output of the flip-flop and the original signal are supplied to the gate to obtain the phase signals of 0 ° and 90 °.

[Conventional technology]

The carrier color signal in the NTSC system is a quadrature two-phase balanced modulation signal. Therefore, for example, in a color video camera, a subcarrier signal having a phase of 0 ° and a subcarrier signal having a phase of 90 ° are required to form the carrier color signal, so that a phase shift circuit of 90 ° is required. In need.

In addition, in the carrier color signal of the PAL system, one (90 ° phase) subcarrier signal is 90 ° for each horizontal period.
Such phase processing is also necessary because the signals are alternately inverted at 270 °.

Therefore, for example, according to "JP-A-60-39993",
A phase shift circuit as shown in the figure is considered.

That is, in the figure, the master oscillator circuit (21) forms an alternating signal S ₂₁ having a frequency 4fc that is four times the color subcarrier frequency fc, and this signal S ₂₁ is supplied to the frequency dividing circuit (22) to generate the frequency 2fc. Of the signal S ₂₂ and the signal S ₂₂ is supplied to the phase shift circuit (23).

This phase shift circuit (23) is composed of a flip-flop by an ECL circuit, and has a master section (23M) and a slave section (2M).
3S), the subcarrier signal Sb (and ▲ ▼) having a phase of 0 ° is extracted from the slave unit (23S), and the subcarrier signal Sr (and ▲) having a phase of 90 ° is output from the master unit (3M). ▼) is taken out.

Further, in the circuit of FIG. 6, the signal Sr, ▲ ▼ is supplied and the signal LALT, ▲ ▼ whose level is inverted to "L" and "H" every horizontal period is supplied. A subcarrier signal ± Sr, ± ▲ ▼ (the sign of ± indicates that the phase is inverted every horizontal period) whose phase is inverted to 90 ° and 270 ° every horizontal period is taken out.

[Problems to be solved by the invention]

However, in the phase shift circuit (23) of FIG. 4, as shown in FIG. 5, the signal Sb is inverted every other time when the signal S ₂₂ becomes the reference voltage Vb, and the signal Sr is Since the signal S ₂₂ is inverted every other time when the reference voltage becomes Vr (≠ Vb) and the fall time of the signal S ₂₂ cannot be set to 0, the potential difference between the signals Sb and Sr ( A phase error Δφ corresponding to Vb−Vr) occurs.

Therefore, when using this phase circuit (23),
It is necessary to perform phase compensation on the signal Sb or Sr,
Adjustment is also necessary.

Further, in this phase circuit (23), since the signal Sr, ▲ ▼ is formed by the transistor, the rising time and the falling time of the signal Sr, ▲ ▼ are different as shown in FIG. In the phase shift circuit of FIG. 6, the signals ± Sr, ± ▲ ▼ are inverted when the signals Sr, ▲ ▼ become the reference voltage Vs, as shown in FIG. Therefore, an error Δψ occurs in the duty ratio of ± ▲ ▼.

The present invention is intended to solve the above problems.

[Means for solving problems]

Supplied four times the first frequency divided signal S ₃ to the alternating signals S ₁ frequency 4fc was divided by 2 and of the alternating signals S ₁ of the frequency fc of the carrier signal to be required in this end the present invention A first gate circuit (4), a first flip-flop circuit (5) to which an output of the first gate circuit (4) is supplied, and a carrier signal having a phase of 0 ° is taken out from the output side; 1/2 the above alternating signal with the phase inverted with respect to the divided signal S ₃ of
Second divided signal that is divided And a second gate circuit (6) to which the alternating signal S ₁ is supplied
And the output of the second gate circuit (6) is supplied, and a carrier signal having a phase of 90 ° is taken out from the output side.
And an exclusive OR circuit (8) to which the outputs of the first and second flip-flop circuits (5) and (7) are supplied. It is a phase circuit formed by supplying the output of 8) to the second gate circuit (6).

[Action]

A subcarrier signal with no error in phase or duty ratio is output.

〔Example〕

In FIG. 1, an alternating signal S ₁ having an arbitrary duty ratio is taken out from a master oscillator circuit (1) at a frequency 4fc as shown in FIG. 2A, and this signal S ₁ rises through a buffer amplifier (2). It is supplied to a trigger type T flip-flop (3) and is supplied from its Q terminal to B in the same figure.
Slight delay with the signal S ₃ of frequency 2fc for inverting taken out, a signal level is inverted to the signal S ₃ as shown in Figure C from the terminal to each rising edge of the signals S ₁ as shown in Is taken out.

Then, the signal S ₃ is supplied to the OR gate (4) and the signal S ₁ is supplied to the OR gate (4) so that the OR gate (4) outputs a signal S ₄ as shown in FIG. Matches the rising edge of S ₁ and frequency
2fc signal S ₄ is taken out of, as supplied to the T flip-flop circuit of the trigger type the signal S ₄ rises (5) shown in Figure E from its Q terminal, slightly for each rise of the signal S ₄ A signal Sb having a frequency fc that is inverted with a delay, that is, a subcarrier signal Sb having a phase of 0 ° is extracted.

Also the signal And a signal S ₈ described later are supplied to the OR gate (6) to take out the OR output S ₆ . In this case, assuming that S ₈ = “L” at all times, the gate (6) receives one input signal S ₃ of the gate (4). Because it is equivalent to the place of the signal S _6, as indicated by the solid line in FIG. F, 1 cycle by the phase-shifted signal of the signals S ₁ to the signal S _4, i.e., 90 degree phase The signal will be shifted.

Then, this signal S ₆ is supplied to a rising trigger type T flip-flop (7), and its Q terminal has a frequency fc which is inverted with a slight delay at each rising of the signal S ₆ as shown by a solid line in FIG. Signal Sr of is taken out.

In this case, by making the flip-flops (5) and (7) have the same configuration, the delay of the signal Sr with respect to the signal S ₆ can be made the same as the delay of the signal Sb with respect to the signal S ₄ , and therefore, The signal Sr will have a 90 ° phase difference with respect to the signal Sb.

However, with the above configuration alone, it is not possible to determine whether the signal Sr advances or is delayed by 90 ° with respect to the signal Sb as shown in FIGS. In addition, in the case of the NTSC system, the signal Sr holds the state advanced by 90 ° with respect to the signal Sb, and in the case of the PAL system, 90%.
It is necessary to alternately realize a phase advanced state and a phase delayed 90 degree for each horizontal period.

Therefore, an exclusive OR gate (8) is provided and signals Sb and Sr are supplied to it. At the same time, it is "L" level in NTSC system and "L" level and "H" level every horizontal period in PAL system. Signal that alternates with level
LALT is supplied to the gate (8), the gate output S ₈ is taken out, and this signal S ₈ is fed back to the gate (6).

According to such a configuration, in the case of the NTSC system and the PAL system and every other horizontal period, LALT = “L”, so that the gate (8) is only 2 for the signals Sb and Sr. Acts as an exclusive OR gate for input.

Therefore, when the signal Sr is advanced by 90 ° with respect to the signal Sb (this is the correct state), as shown by the solid lines in E and G of the same figure, the signal S ₈ is shown by the solid line in H of the same figure. So that
This signal S ₈ is the input signal of the OR gate (6) Is equivalent to “L” level (when S ₈ = “H”, the signal At least one of them is at "H" level). Therefore,
This condition continues if the signal Sr leads the signal Sb by 90 °.

Also, when the power is turned on or the signal LALT is inverted,
As shown by the broken line in FIG. 6G, the period Tr that should be Sr = “H”
When Sr = “L”, the signal S ₈ becomes as shown by the broken line in FIG. H, and therefore the signal S ₆ becomes S ₆ = “L” as shown by the broken line in FIG. It remains at the “H” level during the period T ₆ when it should be. Therefore, omission inversion operation once the flip-flop (7) by the signal S _6, as shown by a broken line in the drawing G, the signal Sr is not rise to the end of the period Tr, an rise time of the next signal S ₆ Stand up. Therefore,
After that, the signals S ₆ , Sr, and S ₈ are in the states shown by the solid lines in FIGS.

Therefore, when LALT = “L”, the signal Sr is always held in a phase advanced by 90 ° with respect to the signal Sb.

On the other hand, in the case of the PAL method and the remaining every other horizontal period, LALT = “H”, and therefore the gate (8) functions as a 2-input exclusive NOR gate with respect to the signals Sb and Sr.

Therefore, when the signal Sr is delayed by 90 ° with respect to the signal Sb (this is the correct state), as shown by the solid line in FIGS. E and J, the signal S ₈ is shown by the solid line in K in the same figure. So that
This signal S ₈ is the input signal of the OR gate (6) Is equivalent to “L” level (when S ₈ = “H”, the signal At least one of them is at "H" level). Therefore,
This state continues when the signal Sr is delayed by 90 ° with respect to the signal Sb.

Also, when the power is turned on or the signal LALT is inverted,
As shown by the broken line in FIG. 6J, the period Tr that should be Sr = “L”
When Sr = “H”, the signal S ₈ becomes as shown by the broken line in FIG. 9K, and therefore the signal S ₆ becomes S ₆ = “L” as shown by the broken line in FIG. Remains at the “H” level during the period T ₆ that should be satisfied, so that the inversion operation of the flip-flop (7) by the signal S ₆ is skipped once, and as shown by the broken line in FIG. Does not rise to the signal Sr, but falls at the time of the next fall of the signal S ₆ . Therefore,
After that, the signals S ₆ , Sr, and S ₈ are in the states shown by the solid lines in FIGS.

Therefore, when LALT = "H", the signal Sr
It is always held in a state of being retarded by 90 °.

Thus, according to the present invention, when LALT = "L",
It is possible to obtain a signal Sr which is advanced by 90 ° with respect to the signal Sb,
When LALT = “H”, the signal Sr delayed by 90 ° with respect to the signal Sb can be obtained. Therefore, NTSC and PA
By switching the level of the signal LALT according to the L system, two subcarrier signals Sb, S having a predetermined orthogonality are obtained.
You can get r.

Moreover, in this case, in particular, according to the present invention, the signal S ₁ is frequency-divided And then this signal To obtain the signals Sb and Sr.
Since the clock signal is synchronized with the signal S _{1 for} dividing into b and Sr, the signals Sb and Sr can have a phase difference of exactly 90 °. Therefore, there is no need for the conventional phase compensation, and no adjustment is required. further,
Since no adjustment is required, when integrated into an IC, an external terminal pin for supplying an adjustment signal from the outside is unnecessary.

Further, since the circuit that affects the duty ratios of the signals Sb and Sr can be configured in a balanced type, the duty ratios of the signals Sb and Sr can be accurately set to 50%, and no adjustment is required.

FIG. 3 shows a specific example of the case where the above-mentioned phase shift circuit is integrated into an IC. (11) to (14) are bias circuits, the main part of which is a balanced type and the signals Sb and Sr are balanced signals. To be done.

In the above, the case of obtaining a sub-carrier signal for a carrier color signal is used. In CCIR type 8 mm video, when the carrier color signal is frequency-converted, every other field period has one horizontal line. Since the carrier signal whose phase changes by 90 ° for each period is used, the present invention can be applied to this case as well.

〔The invention's effect〕

According to the present invention, the signal S ₁ is divided to obtain a signal And then this signal To obtain the signals Sb and Sr.
Since the clock signal is synchronized with the signal S _{1 for} dividing into b and Sr, the signals Sb and Sr can have a phase difference of exactly 90 °. Therefore, there is no need for the conventional phase compensation, and no adjustment is required. further,
Since no adjustment is required, when integrated into an IC, an external terminal pin for supplying an adjustment signal from the outside is unnecessary.

Further, since the circuit that affects the duty ratios of the signals Sb and Sr can be configured in a balanced type, the duty ratios of the signals Sb and Sr can be accurately set to 50%, and no adjustment is required.

[Brief description of drawings]

1 and 3 are a system diagram and a connection diagram of an example of the present invention,
FIG. 2 and FIGS. 4 to 7 are diagrams for explanation. (1) is an oscillation circuit, (3), (5) and (7) are flip-flops, and (4), (6) and (8) are gates.

Claims (1)

[Claims] 1. A first sentence division signal obtained by dividing an alternating signal having a frequency 4fc which is four times the frequency fc of a required carrier signal by 1/2, and a first gate circuit to which the alternating signal is supplied. A first flip-flop circuit to which the output of the first gate circuit is supplied and a carrier signal having a phase of 0 ° is taken out from the output side, and the alternating circuit in which the phase is inverted with respect to the first divided signal. A second gate circuit to which the second frequency-divided signal obtained by frequency-dividing the signal and the alternating signal are supplied, and an output of the second gate circuit is supplied, and a carrier whose phase is 90 ° from the output side. A second flip-flop circuit for extracting a signal; and an exclusive OR circuit to which the outputs of the first and second flip-flop circuits are supplied. The output of the exclusive OR circuit is used as the second flip-flop circuit. Phase circuit composed by supplying to the gate circuit of.