JPH07283076A - Capacitor - Google Patents
CapacitorInfo
- Publication number
- JPH07283076A JPH07283076A JP7744594A JP7744594A JPH07283076A JP H07283076 A JPH07283076 A JP H07283076A JP 7744594 A JP7744594 A JP 7744594A JP 7744594 A JP7744594 A JP 7744594A JP H07283076 A JPH07283076 A JP H07283076A
- Authority
- JP
- Japan
- Prior art keywords
- comb
- shaped conductor
- capacitor
- dielectric film
- interdigital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えば１ＧHz以上の高
周波信号を扱う集積回路に搭載されるキャパシタに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor mounted on an integrated circuit that handles high frequency signals of, for example, 1 GHz or higher.
【０００２】[0002]
【従来の技術】図７は、従来の薄膜キャパシタの構成例
を示す。(1) は平面図であり、 (2)は(1) のＡ−Ａ′線
における断面図である。2. Description of the Related Art FIG. 7 shows a configuration example of a conventional thin film capacitor. (1) is a plan view, and (2) is a sectional view taken along the line AA ′ of (1).
【０００３】図において、半導体または誘電体の基板１
上に第１の平板導体２−１が形成され、その上に薄い誘
電体膜３が形成され、さらにその上に第２の平板導体２
−２が形成される。第１の平板導体２−１と第２の平板
導体２−２は誘電体膜３を介して対向し、キャパシタの
電極として作用する。本構成では、誘電体膜３を薄く形
成することにより、小さな面積で大きな容量のキャパシ
タを実現することができる。In the figure, a semiconductor or dielectric substrate 1 is shown.
The first flat plate conductor 2-1 is formed on the thin dielectric film 3, and the second flat plate conductor 2 is formed on the thin dielectric film 3.
-2 is formed. The first flat plate conductor 2-1 and the second flat plate conductor 2-2 face each other via the dielectric film 3 and act as electrodes of the capacitor. In this configuration, by forming the dielectric film 3 thin, it is possible to realize a capacitor having a large capacity with a small area.
【０００４】図８は、従来のインターディジタルキャパ
シタの構成例を示す。(1) は平面図であり、 (2)は (1)
のＡ−Ａ′線における断面図である。図において、半導
体または誘電体の基板１上に、第１の櫛形導体４−１お
よび第２の櫛形導体４−２が互いに組み合うように形成
される。第１の櫛形導体４−１の各細線導体と第２の櫛
形導体４−２の各細線導体はそれぞれ対向し、キャパシ
タの電極として作用する。本構成では、小さな容量のキ
ャパシタを精度よく、かつ簡単に製作することができ
る。FIG. 8 shows a configuration example of a conventional interdigital capacitor. (1) is a plan view, (2) is (1)
3 is a cross-sectional view taken along the line AA ′ of FIG. In the figure, a first comb-shaped conductor 4-1 and a second comb-shaped conductor 4-2 are formed on a semiconductor or dielectric substrate 1 so as to be combined with each other. The thin wire conductors of the first comb-shaped conductor 4-1 and the thin wire conductors of the second comb-shaped conductor 4-2 face each other and act as electrodes of the capacitor. With this configuration, a capacitor having a small capacitance can be manufactured accurately and easily.
【０００５】[0005]
【発明が解決しようとする課題】高周波回路を構成する
場合には、回路に直列に挿入するキャパシタの容量は比
較的小さなものが必要となる。薄い誘電体膜を挟んで２
枚の平板導体を対向させた従来の薄膜キャパシタで 0.5
ｐＦ以下の小さな容量を実現しようとすると、平板導体
の面積を非常に小さくしなければならない。しかし、従
来の薄膜キャパシタでは平板導体の端部のフリンジング
の効果が大きく、精度のよいキャパシタを形成すること
ができなかった。When constructing a high frequency circuit, it is necessary that the capacitance of a capacitor inserted in series in the circuit is relatively small. 2 across a thin dielectric film
With a conventional thin film capacitor with two flat plate conductors facing each other, 0.5
In order to realize a small capacitance of pF or less, the area of the flat conductor must be made very small. However, in the conventional thin film capacitor, the effect of fringing at the end of the flat plate conductor is great, and it is not possible to form a capacitor with high precision.
【０００６】また、このような構造では、図９(1) に示
すように製造過程で下側の第１の平板導体２−１の端部
にバリ５が生じるとキャパシタの電極が短絡しやすくな
り、信頼性が低下することがあった。この問題を解決す
るためには、従来は図９(2)に示すように上側の第２の
平板導体２−２が下側の第１の平板導体２−１の端部と
交差する位置にブリッジ６を設けている。しかし、この
ブリッジ６を形成するには誘電体膜３の一部を厚くする
処理を行うことになるが、このときブリッジ６の高さ，
形状，角度などを精密に制御することが困難であった。
また、ブリッジ６の部分における平板導体間の距離が他
の部分と異なることになる。このようなことからエッジ
部容量が不確定となり、キャパシタ容量の精度を高める
ことができなかった。Further, in such a structure, as shown in FIG. 9 (1), when a burr 5 is formed at the end of the lower first plate conductor 2-1 in the manufacturing process, the electrode of the capacitor is likely to be short-circuited. And the reliability may decrease. In order to solve this problem, conventionally, as shown in FIG. 9 (2), the upper second flat plate conductor 2-2 is located at a position where it intersects with the end of the lower first flat plate conductor 2-1. A bridge 6 is provided. However, in order to form the bridge 6, a process of thickening a part of the dielectric film 3 is performed.
It was difficult to precisely control the shape and angle.
Further, the distance between the flat plate conductors in the bridge 6 portion is different from that in the other portions. For this reason, the capacitance of the edge portion becomes uncertain, and the accuracy of the capacitance of the capacitor cannot be improved.
【０００７】一方、従来のインターディジタルキャパシ
タでは、誘電体膜を用いないのでバリなどによる短絡の
心配はない。しかし、対向する電極の面積が小さいの
で、その容量は１ｍｍ長の電極１本あたり0.05ｐＦから
0.1ｐＦ程度と非常に小さいもっであった。したがっ
て、容量を大きくする場合には、各電極の幅を大きくす
るか櫛形導体の数を増やす必要があり、全体の面積が大
きくなる問題があった。On the other hand, in the conventional interdigital capacitor, since no dielectric film is used, there is no fear of short circuit due to burrs or the like. However, since the area of the electrodes facing each other is small, the capacitance is 0.05 pF per 1 mm long electrode.
It was very small, about 0.1 pF. Therefore, in order to increase the capacitance, it is necessary to increase the width of each electrode or increase the number of comb-shaped conductors, which causes a problem of increasing the entire area.
【０００８】本発明は、高い容量精度が得られるインタ
ーディジタルキャパシタの特徴を活かし、さらに面積を
大きくすることなく容量を大きくすることができ、また
多層型ＭＭＩＣや誘電体多層基板を用いた集積回路に適
する構造のキャパシタを提供することを目的とする。The present invention makes use of the characteristics of the interdigital capacitor that can obtain high capacitance accuracy, can increase the capacitance without increasing the area, and also can provide an integrated circuit using a multilayer MMIC or a dielectric multilayer substrate. It is an object of the present invention to provide a capacitor having a structure suitable for the above.
【０００９】[0009]
【課題を解決するための手段】本発明は、第１の櫛形導
体と第２の櫛形導体を互いに組み合わせたインターディ
ジタルキャパシタを誘電体膜を介して複数個重ねて形成
し、各インターディジタルキャパシタを並列に接続した
構成である。According to the present invention, a plurality of interdigital capacitors each having a first comb-shaped conductor and a second comb-shaped conductor combined with each other are formed with a dielectric film interposed therebetween to form each interdigital capacitor. It is a configuration in which they are connected in parallel.
【００１０】また、本発明の構成において、上下に位置
するインターディジタルキャパシタの第１の櫛形導体の
各細線導体が互いに重なり、また第２の櫛形導体の各細
線導体が互いに重なるように形成されたことを特徴とす
る。Further, in the structure of the present invention, the thin wire conductors of the first comb-shaped conductor of the interdigital capacitors located above and below are formed so as to overlap each other, and the thin wire conductors of the second comb-shaped conductor are formed so as to overlap each other. It is characterized by
【００１１】また、本発明の構成において、上下に位置
するインターディジタルキャパシタの第１の櫛形導体の
各細線導体と第２の櫛形導体の各細線導体が互いに重な
るように形成されたことを特徴とする。Further, in the configuration of the present invention, the thin wire conductors of the first comb-shaped conductor and the thin wire conductors of the second comb-shaped conductor of the upper and lower interdigital capacitors are formed so as to overlap each other. To do.
【００１２】[0012]
【作用】本発明のキャパシタは、各インターディジタル
キャパシタの第１の櫛形導体が第１の電極として作用
し、第２の櫛形導体が第２の電極として作用する並列構
造になっている。したがって、各インターディジタルキ
ャパシタの容量は小さくとも、並列数に応じた大きな容
量を面積を大きくすることなく実現することができる。The capacitor of the present invention has a parallel structure in which the first comb-shaped conductor of each interdigital capacitor acts as the first electrode and the second comb-shaped conductor acts as the second electrode. Therefore, even if the capacitance of each interdigital capacitor is small, a large capacitance corresponding to the number of parallels can be realized without increasing the area.
【００１３】また、上下に位置するインターディジタル
キャパシタの第１の櫛形導体の各細線導体と第２の櫛形
導体の各細線導体を互いに重ねることにより、上下方向
の第１の櫛形導体と第２の櫛形導体との間にもキャパシ
タが形成される。これにより、複数のインターディジタ
ルキャパシタを単純に並列接続した以上の大きな容量を
実現することができる。Further, by overlapping the thin wire conductors of the first comb-shaped conductors and the thin wire conductors of the second comb-shaped conductors of the interdigital capacitors located above and below each other, the first comb-shaped conductors and the second comb-shaped conductors in the vertical direction are formed. A capacitor is also formed between the comb-shaped conductor. As a result, it is possible to realize a larger capacitance than that obtained by simply connecting a plurality of interdigital capacitors in parallel.
【００１４】また、本発明のキャパシタは、多層型ＭＭ
ＩＣや誘電体多層基板による集積回路と構造的な整合性
がよく、これらの集積回路内に容易に形成することがで
きる。The capacitor of the present invention is a multi-layer type MM.
It has good structural compatibility with integrated circuits such as ICs and dielectric multilayer substrates, and can be easily formed in these integrated circuits.
【００１５】また、各インターディジタルキャパシタ間
の誘電体膜の厚さを例えば１〜５μｍ程度にすれば、製
造過程で生じるバリ等による短絡を防ぐことができ、信
頼性を高めることができる。また、各誘電体膜の厚さを
調整することにより、キャパシタの容量を変えることが
できる。Further, if the thickness of the dielectric film between the interdigital capacitors is set to, for example, about 1 to 5 μm, short circuit due to burrs or the like generated in the manufacturing process can be prevented and reliability can be improved. In addition, the capacitance of the capacitor can be changed by adjusting the thickness of each dielectric film.
【００１６】[0016]
【実施例】図１は、本発明のキャパシタの第１実施例の
構成を示す（請求項２）。(1) は斜視図であり、(2) は
(1)のＡ−Ａ′線における断面図である。なお、図８に
示す従来のインターディジタルキャパシタと同等の機能
を果たすものは同一符号を付している。1 shows the structure of a first embodiment of a capacitor of the present invention (claim 2). (1) is a perspective view, (2) is
It is a sectional view taken along the line AA ′ of (1). The same reference numerals are given to those having the same function as the conventional interdigital capacitor shown in FIG.
【００１７】図において、半導体または誘電体の基板１
上に第１の櫛形導体４−１および第２の櫛形導体４−２
が互いに組み合うように形成され、その上に厚さが例え
ば１〜５μｍ程度の誘電体膜７が形成される。さらに、
誘電体膜７上に第３の櫛形導体４−３および第４の櫛形
導体４−４が互いに組み合うように形成される。このと
き、第１の櫛形導体４−１の各細線導体と第３の櫛形導
体４−３の各細線導体が重なり、第２の櫛形導体４−２
の各細線導体と第４の櫛形導体４−４の各細線導体が重
なるように形成される。第１の櫛形導体４−１と第３の
櫛形導体４−３は誘電体膜７に設けたスルーホール８−
１を介して接続され、第２の櫛形導体４−２と第４の櫛
形導体４−４は誘電体膜７に設けたスルーホール８−２
を介して接続される。なお、図１(1) では、基板１およ
び誘電体膜７は省略されている。In the figure, a semiconductor or dielectric substrate 1
First comb-shaped conductor 4-1 and second comb-shaped conductor 4-2
Are formed so as to be combined with each other, and a dielectric film 7 having a thickness of, for example, about 1 to 5 μm is formed thereon. further,
A third comb-shaped conductor 4-3 and a fourth comb-shaped conductor 4-4 are formed on the dielectric film 7 so as to be combined with each other. At this time, the thin wire conductors of the first comb-shaped conductor 4-1 and the thin wire conductors of the third comb-shaped conductor 4-3 overlap each other, and the second comb-shaped conductor 4-2 is formed.
And the thin wire conductors of the fourth comb-shaped conductor 4-4 overlap each other. The first comb-shaped conductor 4-1 and the third comb-shaped conductor 4-3 are provided with through holes 8-in the dielectric film 7.
The second comb-shaped conductor 4-2 and the fourth comb-shaped conductor 4-4 are connected to each other through the through hole 8-2 provided in the dielectric film 7.
Connected via. Note that the substrate 1 and the dielectric film 7 are omitted in FIG. 1 (1).
【００１８】このような構造では、第１の櫛形導体４−
１と第２の櫛形導体４−２からなるインターディジタル
キャパシタと、第３の櫛形導体４−３と第４の櫛形導体
４−４からなるインターディジタルキャパシタが並列に
接続されることになる。このようなキャパシタは、従来
のインターディジタルキャパシタと比較して、面積を大
きくすることなく容易に大きな容量を実現することがで
きる。なお、本実施例では２層構造のものを示したが、
３層以上に構成することにより並列数に応じた容量増加
を図ることができる。In such a structure, the first comb-shaped conductor 4-
The interdigital capacitor composed of the first comb-shaped conductor 4-2 and the interdigital capacitor composed of the third comb-shaped conductor 4-3 and the fourth comb-shaped conductor 4-4 are connected in parallel. Such a capacitor can easily realize a large capacitance without increasing the area as compared with the conventional interdigital capacitor. In addition, although a two-layer structure is shown in this embodiment,
By constructing three or more layers, the capacity can be increased according to the number of parallel connections.
【００１９】図２は、本発明のキャパシタの第２実施例
の構成を示す（請求項３）。(1) は斜視図であり、(2)
は (1)のＡ−Ａ′線における断面図である。なお、図１
に示す第１実施例と同等の機能を果たすものは同一符号
を付している。FIG. 2 shows the structure of a second embodiment of the capacitor of the present invention (claim 3). (1) is a perspective view, (2)
FIG. 3B is a sectional view taken along line AA ′ in (1). Note that FIG.
Components having the same functions as those of the first embodiment shown in are designated by the same reference numerals.
【００２０】図において、半導体または誘電体の基板１
上に第１の櫛形導体４−１および第２の櫛形導体４−２
が互いに組み合うように形成され、その上に厚さが例え
ば１〜５μｍ程度の誘電体膜７が形成される。さらに、
誘電体膜７上に第３の櫛形導体４−３および第４の櫛形
導体４−４が互いに組み合うように形成される。ここ
で、第１の櫛形導体４−１の各細線導体と第４の櫛形導
体４−４の各細線導体が重なり、第２の櫛形導体４−２
の各細線導体と第３の櫛形導体４−３の各細線導体が重
なるように形成される。第１の櫛形導体４−１と第３の
櫛形導体４−３は誘電体膜７に設けたスルーホール８−
１を介して接続され、第２の櫛形導体４−２と第４の櫛
形導体４−４は誘電体膜７に設けたスルーホール８−２
を介して接続される。なお、図２(1) では、基板１およ
び誘電体膜７は省略されている。In the figure, a semiconductor or dielectric substrate 1
First comb-shaped conductor 4-1 and second comb-shaped conductor 4-2
Are formed so as to be combined with each other, and a dielectric film 7 having a thickness of, for example, about 1 to 5 μm is formed thereon. further,
A third comb-shaped conductor 4-3 and a fourth comb-shaped conductor 4-4 are formed on the dielectric film 7 so as to be combined with each other. Here, the thin wire conductors of the first comb-shaped conductor 4-1 and the thin wire conductors of the fourth comb-shaped conductor 4-4 overlap each other, and the second comb-shaped conductor 4-2 is formed.
And the thin wire conductors of the third comb-shaped conductor 4-3 are overlapped with each other. The first comb-shaped conductor 4-1 and the third comb-shaped conductor 4-3 are provided with through holes 8-in the dielectric film 7.
The second comb-shaped conductor 4-2 and the fourth comb-shaped conductor 4-4 are connected to each other through the through hole 8-2 provided in the dielectric film 7.
Connected via. The substrate 1 and the dielectric film 7 are omitted in FIG. 2 (1).
【００２１】このような構造では、第１の櫛形導体４−
１と第２の櫛形導体４−２からなるインターディジタル
キャパシタと、第３の櫛形導体４−３と第４の櫛形導体
４−４からなるインターディジタルキャパシタが並列に
接続されることになる。さらに、第１の櫛形導体４−１
と第４の櫛形導体４−４、第２の櫛形導体４−２と第３
の櫛形導体４−３の各細線導体が対向してキャパシタが
形成される。これにより、平面的なインターディジタル
キャパシタの並列接続による容量と、上下方向に対向す
る櫛形導体間に形成されるキャパシタの容量が合算され
る。したがって、複数のインターディジタルキャパシタ
を単純に並列接続した第１実施例の構成以上の大きな容
量を実現することができる。In such a structure, the first comb-shaped conductor 4-
The interdigital capacitor composed of the first comb-shaped conductor 4-2 and the interdigital capacitor composed of the third comb-shaped conductor 4-3 and the fourth comb-shaped conductor 4-4 are connected in parallel. Furthermore, the first comb-shaped conductor 4-1
And the fourth comb-shaped conductor 4-4, and the second comb-shaped conductor 4-2 and the third
The thin wire conductors of the comb-shaped conductor 4-3 are opposed to each other to form a capacitor. As a result, the capacitance due to the parallel connection of the planar interdigital capacitors and the capacitance of the capacitor formed between the comb-shaped conductors facing each other in the vertical direction are added. Therefore, it is possible to realize a larger capacitance than that of the first embodiment in which a plurality of interdigital capacitors are simply connected in parallel.
【００２２】なお、本実施例は２組のインターディジタ
ルキャパシタで第１の電極となる櫛形導体（４−１，４
−３）と、第２の電極となる櫛形導体（４−４，４−
２）が完全に重なるようになっているが、一方のインタ
ーディジタルキャパシタを水平方向にずらして形成する
ことにより、キャパシタの容量を調整することができ
る。なお、誘電体膜７の厚さを変えても同様にキャパシ
タの容量を調整することができる。In this embodiment, two sets of interdigital capacitors are used as the first electrodes of the comb-shaped conductors (4-1, 4).
-3) and a comb-shaped conductor (4-4, 4-
Although 2) is completely overlapped, the capacitance of one of the interdigital capacitors can be adjusted by horizontally shifting the interdigital capacitors. The capacitance of the capacitor can be similarly adjusted by changing the thickness of the dielectric film 7.
【００２３】ここで、従来のインターディジタルキャパ
シタ、第１実施例のキャパシタ、第２実施例のキャパシ
タにおいて、各櫛形導体の櫛の数Ｎと容量Ｃ（ｐＦ）と
の関係について計算した結果を図６に示す。なお、計算
結果では、キャパシタのＳパラメータを電磁界解析によ
り解析し、理想的なキャパシタとしてフィッティングし
て求めたものである。計算条件は、 基板１の誘電率 12.6 誘電体膜７の誘電率 3.3 誘電体膜７の厚さ 2μｍ 櫛形導体４の細線導体（櫛）の幅 4μｍ 櫛形導体４の細線導体（櫛）の間隔 2μｍ 櫛形導体４の細線導体（櫛）の長さ 50μｍ である。図に示すように、従来構成に対して、第１実施
例の構成では２倍程度の容量、第２実施例の構成では３
倍程度の容量を同一の面積で実現できることがわかる。Here, in the conventional interdigital capacitor, the capacitor of the first embodiment, and the capacitor of the second embodiment, the calculation results of the relationship between the number N of combs of each comb-shaped conductor and the capacitance C (pF) are shown. 6 shows. The calculation result is obtained by analyzing the S parameter of the capacitor by electromagnetic field analysis and fitting it as an ideal capacitor. Calculation conditions are as follows: Dielectric constant of substrate 12.6 Dielectric constant of dielectric film 7 3.3 Thickness of dielectric film 7 μm Width of thin wire conductor (comb) of comb-shaped conductor 4 4 μm Distance between thin wire conductors (comb) of comb-shaped conductor 4 2 μm The length of the thin wire conductor (comb) of the comb-shaped conductor 4 is 50 μm. As shown in the figure, the capacity of the first embodiment is about double the capacity of the conventional structure, and the capacity of the second embodiment is 3 times.
It can be seen that a double capacity can be realized in the same area.
【００２４】図３は、本発明のキャパシタの第３実施例
の構成を示す（請求項３）。(1) は斜視図であり、(2)
は (1)のＡ−Ａ′線における断面図である。なお、図１
および図２に示す実施例と同等の機能を果たすものは同
一符号を付している。FIG. 3 shows the structure of a third embodiment of the capacitor of the present invention (claim 3). (1) is a perspective view, (2)
FIG. 3B is a sectional view taken along line AA ′ in (1). Note that FIG.
The same reference numerals are given to those having the same functions as those of the embodiment shown in FIG.
【００２５】図において、半導体または誘電体の基板１
上に第１の櫛形導体４−１および第２の櫛形導体４−２
が互いに組み合うように形成され、その上に第１の誘電
体膜７−１が形成される。さらに、第１の誘電体膜７−
１上に第３の櫛形導体４−３および第４の櫛形導体４−
４が互いに組み合うように形成され、その上に第２の誘
電体膜７−２が形成される。さらに、第２の誘電体膜７
−２上に第５の櫛形導体４−５および第６の櫛形導体４
−６が互いに組み合うように形成される。ここで、第１
の櫛形導体４−１，第４の櫛形導体４−４，第５の櫛形
導体４−５の各細線導体が重なり、第２の櫛形導体４−
２，第３の櫛形導体４−３，第６の櫛形導体４−６の各
細線導体が重なるように形成される。In the figure, a semiconductor or dielectric substrate 1
First comb-shaped conductor 4-1 and second comb-shaped conductor 4-2
Are formed so as to be combined with each other, and a first dielectric film 7-1 is formed thereon. Furthermore, the first dielectric film 7-
On top of the first comb-shaped conductor 4-3 and the fourth comb-shaped conductor 4-
4 are formed so as to be combined with each other, and the second dielectric film 7-2 is formed thereon. Furthermore, the second dielectric film 7
-2 on the fifth comb-shaped conductor 4-5 and the sixth comb-shaped conductor 4
-6 are formed so as to mate with each other. Where the first
The thin wire conductors of the comb-shaped conductor 4-1, the fourth comb-shaped conductor 4-4, and the fifth comb-shaped conductor 4-5 overlap each other, and the second comb-shaped conductor 4-
The thin wire conductors of the second, third comb-shaped conductor 4-3 and sixth comb-shaped conductor 4-6 are formed to overlap each other.
【００２６】第１の櫛形導体４−１と第３の櫛形導体４
−３および第２の櫛形導体４−２と第４の櫛形導体４−
４は、それぞれ第１の誘電体膜７−１に設けたスルーホ
ール８−１，８−２を介して接続される。また、第３の
櫛形導体４−３と第５の櫛形導体４−５および第４の櫛
形導体４−４と第６の櫛形導体４−６は、それぞれ第２
の誘電体膜７−２に設けたスルーホール８−３，８−４
を介して接続される。なお、図２(1) では、基板１、誘
電体膜７−１，７−２は省略されている。The first comb-shaped conductor 4-1 and the third comb-shaped conductor 4
-3 and the second comb-shaped conductor 4-2 and the fourth comb-shaped conductor 4-
4 are connected to each other through through holes 8-1 and 8-2 provided in the first dielectric film 7-1. In addition, the third comb-shaped conductor 4-3 and the fifth comb-shaped conductor 4-5, and the fourth comb-shaped conductor 4-4 and the sixth comb-shaped conductor 4-6 are the second comb-shaped conductor 4-3.
Through holes 8-3 and 8-4 provided in the dielectric film 7-2 of
Connected via. Note that the substrate 1 and the dielectric films 7-1 and 7-2 are omitted in FIG. 2 (1).
【００２７】このような構造では、各層のインターディ
ジタルキャパシタが並列に接続されるとともに、第２実
施例と同様に上下方向に形成されるキャパシタによる容
量増加を図ることができる。なお、本実施例の構成で
は、第２実施例の構成以上の大きな容量を実現すること
ができる。With such a structure, the interdigital capacitors of the respective layers are connected in parallel, and the capacitance can be increased by the capacitors formed in the vertical direction as in the second embodiment. The configuration of this embodiment can realize a larger capacity than that of the configuration of the second embodiment.
【００２８】なお、本実施例では３層構造のものを示し
たが、４層以上に構成することにより並列数に応じた容
量増加を図ることができる。また、第１実施例の構成と
第２実施例の構成を組み合わせて３層構造以上にしても
よい。Although a three-layer structure is shown in this embodiment, it is possible to increase the capacity in accordance with the number of parallels by forming four layers or more. Further, the structure of the first embodiment and the structure of the second embodiment may be combined to form a three-layer structure or more.
【００２９】図４は、本発明のキャパシタの第４実施例
の構成を示す断面図である。なお、本実施例は第１実施
例の構成に適用したものであるが、第２実施例あるいは
第３実施例の構成にも同様に適用することができる。FIG. 4 is a sectional view showing the structure of a fourth embodiment of the capacitor of the present invention. Although the present embodiment is applied to the structure of the first embodiment, it can be similarly applied to the structure of the second or third embodiment.
【００３０】本実施例の特徴は、基板１と第１のインタ
ーディジタルキャパシタ（第１の櫛形導体４−１，第２
の櫛形導体４−２）との間に、誘電体膜７−３を形成し
たところにある。本実施例の構成においても同様にキャ
パシタの容量を大きくすることができるが、特に誘電体
膜７−３により第１のインターディジタルキャパシタの
容量を大きくして全体の容量増大を図ることができる。The feature of this embodiment is that the substrate 1 and the first interdigital capacitor (the first comb-shaped conductor 4-1 and the second interdigital capacitor 4-1) are provided.
The dielectric film 7-3 is formed between the dielectric film 7-3 and the comb-shaped conductor 4-2). In the configuration of the present embodiment, the capacitance of the capacitor can be similarly increased. In particular, the dielectric film 7-3 can increase the capacitance of the first interdigital capacitor to increase the overall capacitance.
【００３１】図５は、本発明のキャパシタの第５実施例
の構成を示す断面図である。なお、本実施例は第１実施
例の構成に適用したものであるが、第２実施例あるいは
第３実施例の構成にも同様に適用することができる。FIG. 5 is a sectional view showing the structure of a fifth embodiment of the capacitor of the present invention. Although the present embodiment is applied to the structure of the first embodiment, it can be similarly applied to the structure of the second or third embodiment.
【００３２】本実施例の特徴は、基板１と第１のインタ
ーディジタルキャパシタ（第１の櫛形導体４−１，第２
の櫛形導体４−２）との間に誘電体膜７−３を形成し、
さらに第２のインターディジタルキャパシタ（第３の櫛
形導体４−３，第４の櫛形導体４−４）の上に誘電体膜
７−４を形成したところにある。本実施例の構成におい
ても同様にキャパシタの容量を大きくすることができる
が、特に誘電体膜７−４により第２のインターディジタ
ルキャパシタの容量を大きくして全体の容量増大を図る
ことができる。The feature of this embodiment is that the substrate 1 and the first interdigital capacitor (the first comb-shaped conductors 4-1 and the second interdigital capacitors 4-1) are provided.
A dielectric film 7-3 between the comb-shaped conductor 4-2) of
Further, a dielectric film 7-4 is formed on the second interdigital capacitor (third comb-shaped conductor 4-3, fourth comb-shaped conductor 4-4). The capacitance of the capacitor can be similarly increased in the configuration of the present embodiment, but the capacitance of the second interdigital capacitor can be increased by the dielectric film 7-4 to increase the overall capacitance.
【００３３】本発明のキャパシタは、各実施例に示すよ
うに複数のインターディジタルキャパシタを上下方向に
配置して並列接続した構成である。したがって、多層型
ＭＭＩＣや誘電体多層基板による集積回路と構造的な整
合性がよく、これらの集積回路の層間に容易に形成する
ことができる。The capacitor of the present invention has a structure in which a plurality of interdigital capacitors are arranged vertically and connected in parallel as shown in each embodiment. Therefore, it has good structural compatibility with an integrated circuit using a multilayer MMIC or a dielectric multilayer substrate, and can be easily formed between layers of these integrated circuits.
【００３４】[0034]
【発明の効果】以上説明したように本発明は、複数のイ
ンターディジタルキャパシタを並列接続した構成であ
り、各インターディジタルキャパシタの容量は小さくと
も、並列数に応じた大きな容量を面積を大きくすること
なく実現することができる。As described above, the present invention has a configuration in which a plurality of interdigital capacitors are connected in parallel. Even if the capacitance of each interdigital capacitor is small, a large capacitance corresponding to the number of parallels has a large area. Can be realized without.
【００３５】また、上下に位置するインターディジタル
キャパシタで第１の電極となる櫛形導体と第２の電極と
なる櫛形導体を重ねることにより、上下方向にもキャパ
シタが形成され、複数のインターディジタルキャパシタ
を単純に並列接続した以上の大きな容量を実現すること
ができる。Further, by interposing the comb-shaped conductors serving as the first electrodes and the comb-shaped conductors serving as the second electrodes in the interdigital capacitors located above and below, the capacitors are formed in the vertical direction, and a plurality of interdigital capacitors are formed. It is possible to realize a larger capacity than that obtained by simply connecting in parallel.
【００３６】また、各層のインターディジタルキャパシ
タの間に形成される誘電体膜の厚さを十分にとることに
より、製造過程で生じるバリ等による短絡を防ぐことが
でき、信頼性を高めることができる。Further, by sufficiently making the thickness of the dielectric film formed between the interdigital capacitors of the respective layers, it is possible to prevent a short circuit due to burrs or the like caused in the manufacturing process, and it is possible to improve reliability. .
【図１】本発明のキャパシタの第１実施例の構成を示す
図。FIG. 1 is a diagram showing a configuration of a first embodiment of a capacitor of the present invention.
【図２】本発明のキャパシタの第２実施例の構成を示す
図。FIG. 2 is a diagram showing a configuration of a second embodiment of a capacitor of the present invention.
【図３】本発明のキャパシタの第３実施例の構成を示す
図。FIG. 3 is a diagram showing the configuration of a third embodiment of the capacitor of the present invention.
【図４】本発明のキャパシタの第４実施例の構成を示す
図。FIG. 4 is a diagram showing the configuration of a fourth embodiment of the capacitor of the present invention.
【図５】本発明のキャパシタの第５実施例の構成を示す
図。FIG. 5 is a diagram showing the configuration of a fifth embodiment of the capacitor of the present invention.
【図６】本発明による容量増加の効果を計算した結果を
示す図。FIG. 6 is a diagram showing a result of calculating the effect of increasing the capacity according to the present invention.
【図７】従来の薄膜キャパシタの構成例を示す図。FIG. 7 is a diagram showing a configuration example of a conventional thin film capacitor.
【図８】従来のインターディジタルキャパシタの構成例
を示す図。FIG. 8 is a diagram showing a configuration example of a conventional interdigital capacitor.
【図９】従来の薄膜キャパシタの問題点および解決法を
示す図。FIG. 9 is a diagram showing problems and solutions of a conventional thin film capacitor.
１ 基板 ２ 平板導体 ３，７ 誘電体膜 ４ 櫛形導体 ５ バリ ６ ブリッジ ８ スルーホール 1 substrate 2 plate conductor 3, 7 dielectric film 4 comb-shaped conductor 5 burr 6 bridge 8 through hole
Claims (3)
に組み合わせたインターディジタルキャパシタを誘電体
膜を介して複数個重ねて形成し、各インターディジタル
キャパシタを並列に接続した構成であることを特徴とす
るキャパシタ。1. A structure in which a plurality of interdigital capacitors each of which is formed by combining a first comb-shaped conductor and a second comb-shaped conductor with each other are stacked via a dielectric film, and the interdigital capacitors are connected in parallel. Capacitor.
櫛形導体の各細線導体が互いに重なり、また第２の櫛形
導体の各細線導体が互いに重なるように形成された構成
であることを特徴とするキャパシタ。2. The capacitor according to claim 1, wherein the thin wire conductors of the first comb-shaped conductors of the upper and lower interdigital capacitors overlap each other, and the thin wire conductors of the second comb-shaped conductor overlap each other. A capacitor having a formed structure.
櫛形導体の各細線導体と第２の櫛形導体の各細線導体が
互いに重なるように形成された構成であることを特徴と
するキャパシタ。3. The capacitor according to claim 1, wherein the thin wire conductors of the first comb-shaped conductor and the thin wire conductors of the second comb-shaped conductor of the upper and lower interdigital capacitors are formed to overlap each other. Is a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7744594A JPH07283076A (en) | 1994-04-15 | 1994-04-15 | Capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7744594A JPH07283076A (en) | 1994-04-15 | 1994-04-15 | Capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07283076A true JPH07283076A (en) | 1995-10-27 |
Family
ID=13634227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7744594A Pending JPH07283076A (en) | 1994-04-15 | 1994-04-15 | Capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07283076A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745335A (en) * | 1996-06-27 | 1998-04-28 | Gennum Corporation | Multi-layer film capacitor structures and method |
| EP0905792A3 (en) * | 1997-09-30 | 2000-02-09 | Hewlett-Packard Company | Stacked-fringe integrated circuit capacitors |
| EP1022768A2 (en) * | 1999-01-20 | 2000-07-26 | Philips Corporate Intellectual Property GmbH | Voltage-stable thin film capacitor with inter-digital structure |
| JP2000315625A (en) * | 1999-04-09 | 2000-11-14 | Alcatel | Layered capacitor device |
| EP1075004A1 (en) * | 1999-02-17 | 2001-02-07 | TDK Corporation | Capacitor |
| WO2001078149A3 (en) * | 2000-04-07 | 2002-03-21 | Koninkl Philips Electronics Nv | Interdigitated multilayer capacitor structure for deep sub-micron cmos |
| JP2005183739A (en) * | 2003-12-19 | 2005-07-07 | Ricoh Co Ltd | Capacitive element |
| JP2007258719A (en) * | 2006-03-20 | 2007-10-04 | Standard Microsystems Corp | Fringe-capacitor using bootstrapped non-metal layer |
| US7551421B2 (en) * | 2006-12-26 | 2009-06-23 | International Business Machines Corporation | Capacitor having electrode terminals at same end of capacitor to reduce parasitic inductance |
| US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
| WO2015141107A1 (en) * | 2014-03-18 | 2015-09-24 | 株式会社日本マイクロニクス | Battery |
| US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
| US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
| US10998136B2 (en) | 2016-06-09 | 2021-05-04 | Point Engineering Co., Ltd. | Three-dimensional capacitor |
| WO2024119411A1 (en) * | 2022-12-07 | 2024-06-13 | 华为技术有限公司 | Capacitor, preparation method for capacitor, and integrated circuit and electronic device |
-
1994
- 1994-04-15 JP JP7744594A patent/JPH07283076A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745335A (en) * | 1996-06-27 | 1998-04-28 | Gennum Corporation | Multi-layer film capacitor structures and method |
| EP0905792A3 (en) * | 1997-09-30 | 2000-02-09 | Hewlett-Packard Company | Stacked-fringe integrated circuit capacitors |
| US6999297B1 (en) | 1999-01-20 | 2006-02-14 | U.S. Philips Corporation | Breakdown-resistant thin film capacitor with interdigitated structure |
| EP1022768A2 (en) * | 1999-01-20 | 2000-07-26 | Philips Corporate Intellectual Property GmbH | Voltage-stable thin film capacitor with inter-digital structure |
| EP1022768A3 (en) * | 1999-01-20 | 2004-05-06 | Philips Intellectual Property & Standards GmbH | Voltage-stable thin film capacitor with inter-digital structure |
| EP1075004A1 (en) * | 1999-02-17 | 2001-02-07 | TDK Corporation | Capacitor |
| EP1075004A4 (en) * | 1999-02-17 | 2007-05-02 | Tdk Corp | Capacitor |
| JP2000315625A (en) * | 1999-04-09 | 2000-11-14 | Alcatel | Layered capacitor device |
| WO2001078149A3 (en) * | 2000-04-07 | 2002-03-21 | Koninkl Philips Electronics Nv | Interdigitated multilayer capacitor structure for deep sub-micron cmos |
| US6822312B2 (en) | 2000-04-07 | 2004-11-23 | Koninklijke Philips Electronics N.V. | Interdigitated multilayer capacitor structure for deep sub-micron CMOS |
| JP2005183739A (en) * | 2003-12-19 | 2005-07-07 | Ricoh Co Ltd | Capacitive element |
| JP2007258719A (en) * | 2006-03-20 | 2007-10-04 | Standard Microsystems Corp | Fringe-capacitor using bootstrapped non-metal layer |
| US7551421B2 (en) * | 2006-12-26 | 2009-06-23 | International Business Machines Corporation | Capacitor having electrode terminals at same end of capacitor to reduce parasitic inductance |
| US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
| US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
| WO2015141107A1 (en) * | 2014-03-18 | 2015-09-24 | 株式会社日本マイクロニクス | Battery |
| TWI568043B (en) * | 2014-03-18 | 2017-01-21 | 日本麥克隆尼股份有限公司 | Battery |
| CN106463617A (en) * | 2014-03-18 | 2017-02-22 | 日本麦可罗尼克斯股份有限公司 | Battery |
| JPWO2015141107A1 (en) * | 2014-03-18 | 2017-04-06 | 株式会社日本マイクロニクス | battery |
| KR101877151B1 (en) * | 2014-03-18 | 2018-07-10 | 가부시키가이샤 니혼 마이크로닉스 | Battery |
| US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
| US10998136B2 (en) | 2016-06-09 | 2021-05-04 | Point Engineering Co., Ltd. | Three-dimensional capacitor |
| WO2024119411A1 (en) * | 2022-12-07 | 2024-06-13 | 华为技术有限公司 | Capacitor, preparation method for capacitor, and integrated circuit and electronic device |
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