JPH1154369A - Multilayered electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered electronic component which permits satisfac tory improvement in insulation property, even if the component is miniaturized. SOLUTION: A large margin MA of a capacitor conductor DA for input/ output electrodes 18, 20 is provided. A capacitor conductor DB is wide in the direction of input/output electrodes 18, 20, and provides a small margin for the input/output electrode 18, 20. Since the margin MA between the input/output electrodes 18, 20 and the capacitor conductor DA connected to a GND electrode 16 is large, the pressure resistance between them is improved and dielectric breakdown is reduced. Thus, a multilayered electronic component having a small size and a high capacitance can be obtained without causing deterioration in insulation resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a multilayer electronic component such as a C composite component and a three-terminal capacitor, and more specifically relates to improvement of the withstand voltage of the terminal electrode.

[0002]

2. Description of the Related Art An example of a laminated electronic component, for example, a laminated LC composite component, has a laminated structure as shown in FIG. This background art is an example of a laminated structure of an LC composite component constituting a so-called T-type filter, as shown in an equivalent circuit in FIG. As shown in the figure, a capacitor (capacitor) section 10 is constituted by the upper six layers, and an inductor (coil) section 12 is constituted by the lower 10 layers.
Is configured. The sheets A1 to A6 forming the capacitor section 10 are formed of, for example, a dielectric material, and the sheets A2 to A5 are formed with capacitor conductors. On the other hand, sheet B1 forming inductor section 12
To B10 are made of, for example, a magnetic material (magnetic ferrite or the like), and inductors are formed on the sheets B2 to B9. A sheet 14 is provided between the capacitor section 10 and the inductor section 12 as a dissimilar joining material. Each of the above sheets is laminated, molded, pressed and fired, and a terminal electrode for external drawing is formed on the laminated body, whereby a laminated LC composite component is obtained.

[0003] Describing the capacitor section 10, the sheet A1 is a protective layer. One of the capacitor conductors D1 is formed on each of the sheets A2 and A4. These capacitor conductors D1 are exposed on the front and rear sides of the laminated sheet, and are connected to the GND electrodes (side terminals) 16 shown in FIG. 6B or 6C. Sheets A3 and A5
The other capacitor conductors D2 are formed. These capacitor conductors D2 are connected by via holes D3 (indicated by connection lines) near the center. That is, a window is provided at the central portion of the above-described capacitor conductor D1, and the upper and lower portions of the capacitor conductor D2 are connected by a via hole D3 passing through this portion. Sheet A6 is also a protective layer. The capacitor C shown in the equivalent circuit of FIG. 6D is constituted by the capacitor conductors D1 and D2 described above.

Next, the inductor portion 12 will be described. The sheet B1 is a protective layer. On the sheets B2 to B9, coil conductors are formed. A substantially U-shaped coil conductor E1, F1 is formed on the sheet B2. These coil conductors E1 and F1 are continuous in a substantially inverted S-shape.
The connection portion is connected to the capacitor section 10 via hole D3 penetrating the sheets A6, 14, B1.

[0005] A substantially U-shaped coil conductor E2, F2 is formed on the sheet B3 so that the opening faces the opposite side. One end of each of the via holes G1, H1
Are connected to the coil conductors E1 and F1, respectively. Similarly, a substantially U-shaped coil conductor E3, F3 is formed on the next sheet B4 so that the opening faces. One end of each of the via holes G2, H2
Are connected to the coil conductors E2 and F2, respectively. On the following sheets B5 and B7, coil conductors E2 and F2 similar to sheet B3 are formed, respectively.
Further, the sheet conductors E3 and F3 similar to the sheet B4 are formed on the sheets B6 and B8. On the sheet B9, coil conductors E4 and F4, each of which has a substantially U-shaped pattern extended and exposed to the left and right sides, respectively, are formed. The hole connection is the same as that of the sheet. The lowermost sheet B10 is a protective layer.

[0006] Of the above components, the coil conductors E1, E2, E3, E4 and the via holes G1, G2, which are spirally continuous, constitute a coil LA of an equivalent circuit shown in FIG. 6 (D). The coil conductor LB of the equivalent circuit shown in FIG. 6D is constituted by the coil conductors F1, F2, F3, F4 and the via holes H1, H2 which are continuous in a spiral shape. The coil conductors E4 and F4 of the sheet B9 are exposed to the left and right from the laminated sheet, and are connected to the input / output electrodes 18 and 20 of FIGS. 6B and 6C, respectively. The external structure of FIGS. 6B and 6C is GN
The difference lies in whether the D electrode 16 is located before and after the side surface of the laminated chip or on the entire periphery of the side surface.

In the meantime, in the laminated type LC composite component, if the value of the capacitance of the capacitor section 10 varies, the cutoff frequency fc in the T-type filter shown in FIG. 6 (D) varies. One of the causes of the variation in the capacitance is the variation in the facing area of the electrodes. When the chip component is miniaturized and the facing area of the electrodes is reduced, even a slight displacement of the electrode area causes a large variation in the capacitance. In addition, the facing area of the electrodes may change due to stacking deviation. Therefore, one of the opposing electrodes is made wider than the other so that the opposing area does not change even if there is some misalignment, so that even if a slight displacement occurs, the variation in capacitance is not affected. I have.

FIG. 7 shows an example of specific shapes and dimensions of the capacitor conductors D1 and D2. As shown in FIG. 7C, the conductor D1 covers the entire conductor D2. As shown in FIG. That is, the capacitor conductor is configured such that the facing area does not change. The unit of the numerical value in the figure is “mm”. The terminal electrodes 16, 18, and 20, as shown in FIG. 7C, are formed directly on the surface of the chip body.

[0009]

However, the above background art has the following disadvantages. (1) Since there is a demand for miniaturization, high capacity, and high inductance of components, there is a tendency to make the facing area of the capacitor conductor as large as possible. Therefore, the distance (side margin) between the external terminal electrode and the internal conductor is reduced. In this case, there is no particular inconvenience even if the distance between the electrode and the conductor having the same potential is short, but the possibility of dielectric breakdown increases due to the short distance between the electrode and the conductor having different potentials. For example, in the example of FIG. 7, the area of the capacitor conductor D1 connected to the GND electrode 16 is larger. Therefore, dielectric breakdown may occur between the capacitor conductor D1 and the input / output electrodes 18 and 20.

(2) In addition, as the size of components is reduced, the potential difference between the external terminal electrode and the internal conductor, which are different in potential, increases. For this reason, when the laminated element body between the two has pores (pores) or the like and moisture enters the laminated body, the deterioration of the pressure resistance is apt to occur due to the influence thereof,
Dielectric breakdown may occur.

The present invention focuses on the above points.
It is an object of the present invention to provide a laminated electronic component capable of satisfactorily improving insulation even if the component is downsized.

[0012]

In order to achieve the above object, the present invention provides an internal conductor having the same potential as an external electrode.
A pattern having a small margin and a pattern having a large margin for an internal conductor having a different potential from the external electrode are provided. Further, another invention is characterized in that a portion where the external electrode of the laminate is formed contains vitreous material.

According to the present invention, by increasing the margin of the internal conductor with respect to the external electrode having a different potential, the insulation resistance value in this portion is increased, and the withstand voltage is improved. Further, by including a vitreous material in a predetermined portion of the external electrode, the pores of the surface layer portion of the laminate are filled with vitreous material,
The penetration of moisture is prevented and the insulation is improved. The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

[0014]

Embodiments of the present invention will be described below in detail. Note that the same reference numerals are used for components corresponding to the above-described background art.

(1) First Embodiment FIG. 1 shows an example of the laminated structure and the shape and dimensions of an electrode according to a first embodiment. First, when explaining from the laminated structure of FIG.
The shapes of the conductors DA and DB of the capacitor section 30 are different. That is, the capacitor conductor DA is connected to the input / output electrodes 18 and 2.
0, and the input / output electrodes 18 and 2
The dimension has a large margin with respect to 0. FIG.
(B) shows an example of the capacitor conductor DA. According to this example, the width WDA of the capacitor conductor DA is 1.9 mm. In the background art described above, 2.1 mm
It is. That is, in the present embodiment, the input / output electrodes 18 and 20
Is 0.1 mm larger than the background art. Further, the margin MA is set to be larger than the interlayer distance between the capacitor conductors DA and DB.

When attention is paid only to the capacitor conductor DA, the margin on the connected GND electrode 16 side is narrow,
The margin on the side of the input / output electrodes 18 and 20 having a large potential difference is designed to be wide.

On the other hand, the capacitor conductor DB has a wide shape in the direction of the input / output electrodes 18 and 20, and has a small margin with respect to the input / output electrodes 18 and 20. FIG. 1C shows an example of the capacitor conductor DB. According to this example, the width WDB of the capacitor conductor DB is 2.1 mm. In the background art described above, it is 1.9 mm. That is, in the present embodiment, the input / output electrode 1
The margin MB for 8, 20 is 0.1% more than the background art.
mm smaller.

Focusing only on the capacitor conductor DB, the margin on the side of the GND electrode 16 having a large potential difference is designed to be wide, and the margin on the side of the input / output electrodes 18 and 20 having a small potential difference is designed to be narrow.

The degree of overlap between the capacitor conductors DA and DB is, for example, as shown in FIG. As described above, in the present embodiment, the difference between the margin DM of the capacitor conductor DA and the margin DB of the capacitor conductor DB is 0.1 mm, and is connected to the input / output electrodes 18 and 20 and the GND electrode 16. The margin MA with the capacitor conductor DA is larger than in the background art. Therefore, the breakdown voltage between them is improved, and dielectric breakdown is reduced. Thereby, a small-sized and high-capacity laminated electronic component can be obtained without deteriorating the insulation resistance.

In particular, even when a crack or the like enters from the side surface of the chip body, the crack is suppressed by the inner conductor of the same potential which is close to the margin from the side surface, so that the insulation deterioration between the inner conductor of the different potential is prevented. be able to. That is,
Certain types of cracks entering the chip body are often prevented from growing where the inner conductor is formed. In the present embodiment, an inner conductor having the same potential exists in the vicinity of the outer electrode outside the chip body because of a margin. For this reason, even if cracks enter from the peripheral surface of the chip body, the growth of the cracks is prevented by the inner conductor having the same potential. Therefore, even when the crack reaches the internal conductor, the potential is the same, so that even if the insulation resistance between them decreases, it does not cause a fatal problem, and high reliability is obtained. Also,
Since the capacitor conductors DA and DB have a margin for overlapping, the variation of the facing area is also suppressed, and the influence on the variation in capacitance is reduced.

(2) Second Embodiment FIG. 2 shows an example of the laminated structure and the shape and dimensions of an electrode according to a second embodiment. First, the structure of the inductor section 12 is the same as that of the background art, but the capacitor section 32 is different. Sheet A1 is
It is a protective layer as in the background art. One of the capacitor conductors DC is formed on each of the sheets A2 and A4. These capacitor conductors DC are exposed on the front and rear sides of the laminated sheet, and are connected to the GND shown in FIG. 6B or 6C.
It is connected to the electrode 16. In addition, the conductor D for the capacitor
The left and right ends of C are cut in a U-shape for hole connection.

On the sheets A3 and A5, the same capacitor conductors DB as those in the first embodiment are formed. These capacitor conductors DB are connected by via holes DD and DE at both left and right ends. That is, the upper and lower portions of the capacitor conductor DB are connected by the via holes DD and DE passing through the cutout portions at the left and right ends of the capacitor conductor DC. Sheet A6 also
It is a protective layer as in the background art. The capacitor C shown in the equivalent circuit of FIG. 6D is constituted by the capacitor conductors DB and DC described above.

Among these, the capacitor conductor DC is
It has a narrow shape in the direction of the input / output electrodes 18 and 20,
The size of the margin with respect to the input / output electrodes 18 and 20 is large. FIG. 2B shows an example of the capacitor conductor DC. The width WDC of the capacitor conductor DC is also
It is 1.9 mm as in the first embodiment, and the margin MC with respect to the input / output electrodes 18 and 20 is 0.1 mm more than in the background art.
1mm larger.

The degree of overlap between the capacitor conductors DC and DB is, for example, as shown in FIG. Thus, also in this embodiment, the difference between the capacitor conductors DC and DB is 0.1 mm.
And the input / output electrodes 18 and 20 and the GND electrode 1
Margin MC with capacitor conductor DC connected to 6
Is larger than the background art. Therefore, the breakdown voltage between them is improved, and dielectric breakdown is reduced. In addition, since there is a margin in the overlap between the capacitor conductors DC and DB, the variation of the facing area is suppressed, and the influence on the variation in capacitance is reduced. According to the second embodiment, the capacitor conductor DB
Are securely connected by the two via holes DD and DE.

Comparing the first and second embodiments, the window connecting the via holes of the capacitor conductors DA and DC does not contribute as a capacitor. This window is different from the first embodiment in that the window is located at the center of the capacitor conductor DA, and in the second embodiment, the window is located at the left and right end sides of the capacitor conductor DC, that is, at a portion that takes a margin.

(3) Embodiments of Embodiments 1 and 2 Next, an embodiment in which a sample under the above-described Embodiments 1 and 2 and a background art sample were subjected to a wet load test will be described. The sample was manufactured in the following procedure. An organic binder is added to the TiO ₂ dielectric material to a thickness of 50
A green sheet of μm was obtained. The same treatment is performed on the Ni—Zn-based magnetic material to obtain a green sheet having a thickness of 30 μm. Then, a capacitor pattern and an inductor pattern were formed on these green sheets by screen printing. The sheet thus obtained was edited in the order of the internal layer constitution, and was laminated at a temperature and pressure of, for example, 90 ° C. and 500 kg / cm ² .

The laminate obtained as described above is separated into individual chips by a dicing machine and
After performing r (time) binder removal processing, 1 hour at 900 ° C.
hr was fired. Next, a conductive paste for an external electrode was applied to the heat-treated chip, and baked at 600 ° C. for 15 minutes. As the conductive paste, for example, a commercially available silver paste can be used.

The GND electrode 16 on the side surface of the chip was formed by using a screen printing method or a transfer method.
Since the screen printing method can apply only a flat surface, the application operation is performed for each surface of the chip. Further, in the transfer method, for example, a groove formed in a flexible flat plate is filled with a paste material, and the chip side surface is pressed against the flat plate to make it concave,
This is a method of applying a paste material over the chip side surface and the end of the adjacent surface. Furthermore, the input / output electrode 1 on the chip end face
For Nos. 8 and 20, the conductive paste was spread on a flat plate to a predetermined thickness, and a chip end face was vertically immersed and applied by a dip method.

Further, the chip after the formation of the external electrodes was plated on Ni with Sn or SnPb (solder) to obtain a finished chip. 100 samples were prepared for each form. Each sample was mounted on a substrate, and a load voltage of 32 V DC was applied between the GND electrode 16 and the input / output electrodes 18 and 20. The test environment was a temperature of 85 ° C. and a relative humidity of 95% RH. And 100h
The number of defective products generated after elapse of 500 hours and 1000 hours was checked. In addition, the thing whose insulation resistance was a value of 1 MΩ or less was regarded as a defective number. The results are shown in Table 1 below. As shown in the figure, the number of defects did not occur in the present embodiment, whereas in the background art structure, the number of defects was 2 at 500 hours.
The number of defects is 15 for 1000 hours.

[0030]

[Table 1]

Next, an impact test was performed on each sample from the side direction, and then a wet load test under the same conditions as described above was performed. In the impact test (2.0 kgf), the chip body is placed horizontally on a support table, and a sharp pin with a tip of 0.7 mmφ is set upright at the center of the chip body, and the end of the pin is ,
This is a test method in which a 9.2 g hard ball is dropped from a height of 2 mm, and is a test that is repeated 10 times for one sample. The result in this case is as shown in Table 2 below. As shown, after 100 hours, the number of defects is 12 in the background art and 0 in the present embodiment. After 500 hours, 95 pieces of background art, 0 pieces of form 1 and 1 pieces of form 2
It is the number of defectives. Further, at 1000 hours, the number of defects is 98 in the background art, 2 in the mode 1, and 3 in the mode 2. Since the impact test is performed, the number of defectives is larger than that in Table 1, but the number of defectives in the present embodiment is much smaller than that of the background art.

[0032]

[Table 2]

As described above, according to the first and second embodiments, the margin of the internal conductor pattern with respect to the external electrodes having different potentials is set large, so that the dielectric breakdown is favorably reduced and the reliability of the parts is improved.

(4) Third Embodiment Next, a third embodiment will be described with reference to FIG. The following embodiment is characterized in that the element body of the external electrode portion contains vitreous material. FIG. 3A is a side view before the external electrode is formed, and FIG. 3B is a cross-sectional view of FIG. 3A along the line # 3 in the direction of the arrow after the external electrode is formed (the same applies to FIGS. 4 and 5). FIG.
In the element, the capacitor body 50 and the heterogeneous junction 1
4, the inductor section 12 is laminated. The capacitor unit 50 may have any of the configurations of the first and second embodiments and the background art.

In the present embodiment, the GND electrode 16 on the side surface of the element is intended to improve the breakdown voltage. Then, the capacitor unit 50
The glass paste 52 is applied to the portion where the GND electrode 16 is formed and its vicinity except for the conductors D1, DA, and DC, that is, the magnetic ferrite portion constituting the inductor portion 12, and further heated and baked. The magnetic ferrite portion has a lower withstand voltage than the dielectric layer forming the capacitor portion 50,
It is generally porous. Therefore, the heated glassy material 52 melts and diffuses inside, and acts to seal the pores existing in the magnetic ferrite portion. Vitreous 5
No. 2 is excellent in withstand voltage, and thus improves the pressure resistance of the surface of the magnetic ferrite portion by diffusion. The vitreous material 52 does not hinder the contact between the internal conductor and the external electrode. After such vitreous diffusion, the external electrodes 16, 1
8, 20 are formed.

As described above, according to the present embodiment, the withstand voltage between the GND electrode 16 formed on the side surface of the chip body and the conductor in the chip body is improved by the vitreous material 52,
The insulation is improved. In addition, since the pores in the surface layer of the chip element are filled with glassy material, the invasion of moisture is prevented, and the dielectric breakdown is reduced in this regard.

(5) Fourth Embodiment Next, a fourth embodiment will be described with reference to FIG. In the fourth embodiment, as shown in FIG. 4, the vitreous material 52 is contained in the capacitor portion 50. That is,
One capacitor conductor D connected to the GND electrode 16
The vitreous material 52 includes the portions 1, 1, and DC, and the GND electrode 16 is formed thereon. For this reason, the inner conductor and the GND electrode 1 in the capacitor section 50
6 is also improved, and the breakdown voltage is improved.

(6) Fifth Embodiment Next, a fifth embodiment will be described with reference to FIG. In the fifth embodiment, the vitreous materials 54 and 56 are contained in the input / output electrodes 18 and 20 at the left and right ends. The input / output electrodes 18 and 20 are formed on the vitreous materials 54 and 56, respectively. According to this embodiment, the withstand voltage between the capacitor conductors D1, DA to DC and the input / output electrodes 18, 20 is mainly improved.

(7) Examples of Embodiments 3 to 5 Next, examples of Embodiments 3 to 5 will be described.
First, a description will be given of a sample manufacturing procedure. As described in Embodiment 1, an organic binder was added to the TiO ₂ dielectric material to obtain a green sheet having a thickness of 50 μm. The same processing is performed on the Ni—Zn-based magnetic material to obtain a green sheet having a thickness of 30 μm. Then, a capacitor pattern and an inductor pattern were formed on these green sheets by screen printing. The sheet thus obtained is edited in the order of the internal layer structure,
The layers were laminated at a temperature of 500 ° C. and a pressure of 500 kg / cm ² .

The laminate obtained as described above is separated into individual chips by a dicing machine and
After the binder removal treatment, baking was performed at 900 ° C. for 1 hour. Thereafter, a glass paste is applied to a corresponding portion of the sintered body by a screen printing method or a transfer method,
Heat treatment was performed at 0 ° C. for 15 minutes. As the glass paste, for example, a commercially available lead borosilicate-based material can be used.

Next, a conductive paste for an external electrode was applied to the heat-treated chip and baked at 600 ° C. for 15 minutes. As the conductive paste, for example, a commercially available silver paste can be used. The GND electrode 16 on the side surface of the chip was formed by using a screen printing method or a transfer method. Also, the input / output electrodes 18 and 20 on the chip end face are used.
As for (2), a conductive paste was spread to a predetermined thickness on a flat plate, and a chip end face was vertically immersed in the conductive paste and applied by a dip method. Further, the chip after forming the external electrodes was plated with Ni-Sn or Pb to obtain a finished chip. Samples of 5 for each form
0 pieces were prepared.

The finished product chip is mounted on a substrate, and GND
A DC 50 is provided between the electrode 16 and the input / output electrodes 18 and 20.
A load voltage of V was applied for 1000 hours. The test environment was a temperature of 60 ° C. and a relative humidity of 95% RH. And 1000
The GND electrode 16 after the hr test and the input / output electrodes 18 and 20
Was measured to determine the incidence of defective products. The criterion was a good product having an insulation resistance value of 100 MΩ or more after the test, and a poor product having an insulation resistance value less than 100 MΩ. The results are shown in Table 3 below. As shown in Table 3, in each of the embodiments, no insulation failure occurred, whereas in the background art, 31 defective products occurred.

[0043]

[Table 3]

(8) Other Embodiments There are many embodiments of the present invention, and various modifications can be made based on the above disclosure. For example, the following is also included. (1) In the forms 3 and 4, the vitreous is formed only in the GND electrode portion of the external electrode, and in the form 5, the vitreous is formed only in the input / output electrode portion.
Vitreous material may be formed on all external electrode portions. In this case, in order to simplify the operation, a glass paste may be applied to the entire surface of the chip body to form vitreous.

(2) Embodiments 1 and 2 and Embodiments 3 to 5
May be combined. (3) In the above embodiment, the present invention is applied to a multilayer chip EMI removal filter, but can be applied to various multilayer chip components such as a multilayer capacitor and a three-terminal capacitor.
Also, the present invention is applicable to various types of filters such as π-type and double π-type filters in addition to T-type filters. (4) The number of sheets laminated, the conductor pattern, the via hole, or the manufacturing conditions described in the above-described embodiment may be appropriately set as necessary.

[0046]

As described above, according to the present invention,
The following effects are obtained. (1) The margin of the inner conductor at the same potential is made smaller than that of the external electrode, and the margin of the inner conductor at a different potential is made larger.This improves insulation and improves the reliability of the product. Obtainable. In addition, insulation deterioration due to cracks is also favorably reduced. (2) Since the vitreous material is formed at a predetermined portion of the external electrode, the dielectric breakdown is favorably reduced, and the reliability of the component is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention.
(A) is a figure which shows the laminated structure, (B)-(D) shows the plane of the principal part.

FIG. 2 is a diagram showing a configuration of a second embodiment of the present invention.
(A) is a figure which shows the laminated structure, (B)-(D) shows the plane of the principal part.

FIG. 3 is a diagram showing a configuration of a third embodiment of the present invention.
(A) is a side view and (B) is a view showing a cross section of (A) after external electrodes are formed.

FIG. 4 is a diagram showing a configuration of a fourth embodiment of the present invention.
(A) is a side view and (B) is a view showing a cross section of (A) after external electrodes are formed.

FIG. 5 is a diagram showing a configuration of a fifth embodiment of the present invention.
(A) is a side view and (B) is a view showing a cross section of (A) after external electrodes are formed.

FIG. 6 is a diagram showing an example of the background art. (A) is a diagram showing a laminated structure, (B) and (C) are external views, and (D) is a diagram showing an equivalent circuit.

FIG. 7 is a diagram showing a plane of a main part of the background art.

[Explanation of symbols]

10, 30, 32, 50: capacitor part 12: inductor part 14: heterogeneous bonding layer 16: GND electrode 18, 20: input / output electrode 52, 54, 56: vitreous A1-A6, B1-B10: sheet D1, D2 , DA, DB, DC: Conductor for capacitor D3, DD, DE, G1, G2, H1, H2, ... Via hole E1 to E4, F1 to F4: Conductor for inductor MA, MB, MC: Margin

Claims (4)

[Claims] 1. A laminated electronic component comprising: a sheet on which a pattern of internal conductors is formed; and an external electrode connected to a corresponding one of the internal conductors formed on an outer surface of the laminate. A multilayer electronic component, wherein an internal conductor having the same potential is a pattern having a small margin, and an internal conductor having a different potential from the external electrode is a pattern having a large margin. 2. A laminated electronic component comprising: a sheet on which a pattern of internal conductors is formed; and external electrodes connected to a corresponding one of the internal conductors formed on an outer surface of the laminate. A laminated electronic component, wherein a vitreous material is contained in a portion where the external electrode is formed. 3. A laminated electronic component in which sheets on which patterns of internal conductors are formed are laminated, and external electrodes connected to corresponding ones of the internal conductors are formed on the outer surface of the laminate. The inner conductor having the same potential is a pattern having a small margin, and the inner conductor having a different potential from the external electrode is a pattern having a large margin.The portion of the laminate where the external electrodes are formed is made of glass. A laminated electronic component characterized by being contained. 4. The laminated electronic component forms a capacitor by laminating sheets on which capacitor conductors are formed, laminates sheets on which inductor conductors are formed, and forms sheets of inductors by connecting conductors with connection conductors. Type L that forms an inductor by connecting between
The multilayer electronic component according to claim 1, 2 or 3, which is a C composite component.