JPH07281926A - Protection device for information processor - Google Patents

Abstract

PURPOSE:To provide a protection device which minimizes the detrioration of throughput of an information processing system, detects the abnormality and protects an information processor. CONSTITUTION:An ID(identification) detection circuit 31 inputs the ID and control codes which are previously set between a protection device 1000 and a CPU. When the ID code is coincident with a prescribed code, a control circuit 41 decodes the control code. At the same time, a count stop control signal 105 is outputted to a counter 10 together with a clear control signal 103, a write control signal 109, a read control signal 107 and a selection signal 104. The counter 10 sets and reads its initial value and starts and stops its counting operation based on the control signal sent from the circuit 41. Then a count end signal 108 is outputted to an output selection circuit 20 when the count value is set at zero by a count-down operation. The initial value of the counter 10 is set and read in response to the signals 109 an 107 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection apparatus for an information processing apparatus, which protects the information processing apparatus by detecting the abnormality of the information processing system, and more particularly, by detecting the abnormality that minimizes the decrease in the throughput of the information processing system. Regarding

[0002]

2. Description of the Related Art Conventionally, there has been a method of using a watchdog timer as a means for detecting runaway of an information processing system.

The watchdog timer is initialized by the information processing system on a regular basis, and generates an abnormality detection signal when a predetermined time has elapsed. Therefore, the information processing system side initializes the watchdog timer and then
The watchdog timer is accessed and reinitialized within the predetermined time.

In the initialization access of the watchdog timer, an abnormality on the information processing system side, for example, when the program processing goes out of control, the initialization access of the watchdog timer is erroneously generated, and the abnormality is not detected, or In order to solve the problem that the abnormality detection is delayed, the identification code for accessing the watchdog timer is
If the identification code of the watchdog timer matches the identification code of the watchdog timer by inputting the identification code to the watchdog timer before accessing the internal registers and circuits of the watchdog timer, There is a method using an identification code that permits acceptance of an access cycle.

[0005]

[Problems to be solved] Here, in order to minimize system damage due to system abnormality, it is necessary to reduce the initialization interval of the watchdog timer, so the initialization processing time of the watchdog timer is minimized. I needed to shorten it.

However, the method using the above-mentioned identification code has a problem that the initialization processing time of the watchdog timer becomes long and the throughput of the entire system is lowered.

The present invention has been made in view of the above-mentioned conventional example, and provides a protection device for an information processing device, which protects the information processing device by detecting an abnormality while minimizing a decrease in throughput of the information processing system. The purpose is to

[0008]

In order to achieve the above object, a protection device for an information processing device of the present invention has the following configuration. That is, an input means for inputting an identification code including a control code, a comparing means for comparing the identification code input in the input step with a predetermined identification code, and a control code for the control code at the same time as the comparison by the comparing means. Decoding means for decoding and generating a command signal to be input to the counter, and validating means for validating the command signal if the identification code and a predetermined identification code match in the comparison by the comparing means. , Inputting the command signal validated by the validating means, initializing the measurement of a predetermined time, measuring a predetermined time interval, and generating a predetermined time elapsed signal when the predetermined time has elapsed, and processing the information. And an output means for outputting to the device.

[0009]

In the above structure, the input means inputs the identification code including the control code, the comparison means compares the identification code input in the input step with a predetermined identification code, and the decoding means At the same time as the comparison by the comparison means,
If the control code is decoded to generate a command signal to be input to the counting counter, and the identification code and the predetermined identification code match in the comparison by the comparison means,
The command signal is validated by the validating means, the command signal validated by the validating means is input, measurement of a predetermined time is initialized, measurement is performed at a predetermined time interval, and when the predetermined time elapses. The predetermined time elapse signal is generated and output to the information processing device by the output means.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining the configuration of a computer protection device 1000 according to an embodiment of the present invention. Protective device 100
0 is composed of an ID detection circuit (31), a control circuit (41), a counter (10), and an output selection circuit (20). The protection device 1000 is connected to an internal bus of a CPU (not shown) via the CPU bus 100. Control data is input to and output from the CPU via the CPU bus. Further, the reset signal 101 and the interrupt signal output from the output selection circuit (20) can be input to the CPU to issue a reset request and an interrupt request for the processing performed by the CPU. The ID detection circuit (31) inputs an identification code (hereinafter referred to as an ID code) and a control code preset between the protection device 1000 and the CPU via the CPU bus 100 and checks the ID code to determine a predetermined value. If it can be identified, the input control code is sent to the control circuit 41.
A specific configuration example of the ID detection circuit (31) is shown in FIG. 2 and will be described later.

The control circuit (41) includes an ID detection circuit (3
1) The control code output from 1) is input and decoded, and the counter (1
0) requests a count stop control signal (105), a clear control signal (103) for requesting counter initialization, a write control signal (109) for requesting setting of a count initial value, and reading of the current count value. Read control signal (1
07) is sent, and a selection signal (104) for selecting the output of the reset signal (101) or the interrupt signal (102) is output to the output selection circuit (20).

The counting counter (10) includes a control circuit (4
Set the initial value of the counter according to the control signal from 1)
Processing such as reading, counting start / stop, and count clear is performed in synchronization with the clock (106). The counting counter (10) counts down the set counter value based on a reference clock of a predetermined frequency supplied from the outside, and when the count value becomes zero, the count end signal (108) becomes active. , To the output selection circuit (20). The counting counter (1
Various control signals for 0) are
It is issued only at the timing immediately after the ID code is written. The setting / reading of the initial value of the counter is executed in response to the write control signal (109) and the read control signal (107), and if it is a read request, the internal bus (106)
The current counter value via the CPU bus (10
0). If it is a write request, the CPU initial value is set in an internal register (not shown) via the internal bus (120) from the CPU bus (100).

In the output selection circuit (20), the selection signal (1
04) based on the input count end signal (10
The output destination of 8) is either the reset signal (101) or the interrupt signal (102) and is output.

Next, a specific example of the configuration of the ID detection circuit (31) and the control circuit (41) shown in FIG. 2 will be described. The ID detection circuit (31) includes a register (61) and a register (6
2), the register (63), the matching circuit (64), the matching circuit (65), the matching circuit (66), and the AND gate (6
7) etc.

Further, the control circuit (41) includes a decoder (7
1) and AND gates (72), (73), (74),
(75), toggle type flip-flop (76) and the like.

The bit width of the above-mentioned three registers is, for example, 8 bits. The 3-byte data format set in these registers is shown in FIG. This data format has an ID code (2004) indicating an identification code for accessing the protection device 1000 and the protection device 100.
It is composed of a control code (2005) for operating 0.
The ID code (2004) includes an 8-bit first ID code (2000), a second ID code (2001), and
It is composed of a third ID code (2002) of bits. The control code (2005) is the counting counter (10).
And the type of control for the output selection circuit (20).

FIG. 4 shows the pattern (300) of each control code.
It is the figure which put together the kind of control (3001) and the drive signal name (3002) corresponding to 0). If the pattern (3000) of the control code is "000", the corresponding control type (3001) is "count counter clear", which sets a predetermined default value in the counter (10). Means that. At this time, the count clear control signal (103) is made active. If the control code pattern (3000) is "001", the corresponding control type (3001) is "count counter stop",
This means that the countdown operation of the counting counter (10) is stopped. At this time, the count stop control signal (105) is made active. If the control code pattern (3000) is "010", the corresponding control type (3001) is "counting counter data write", which means that the counting value is stored in the counting counter (10). It means setting via the bus (100). At this time, the write control signal (109) is made active. Also, the control code pattern (3000)
If is "011", the corresponding control type (3001)
Is "reading of counter counter data", which means that the current count value of the counter (10) is read. At this time, the read control signal (107) is made active. Also, the control code pattern (3000)
If is "100", the corresponding control type (3001)
Is "reset / interrupt output selection". This means whether the reset signal (101) is output or the interrupt signal is output when the count value of the counting counter (10) reaches zero due to countdown. Means to select. At this time, the selection signal (104) is made active.

Returning to FIG. 2, the configuration and operation of the ID detection circuit (31) and control circuit (41) will be described.

The protection circuit 100 already described with reference to FIG.
Five kinds of control for 0 are performed by supplying the protection circuit 1000 with the ID code and the control code in the format shown in FIG. The register (61), the register (62), and the register (63) are registers for inputting and storing these codes. Next, the operation of storing these codes in each register will be described.

In the first write cycle from the CPU bus (100), the corresponding first ID code (2000)
Is stored in the register (61). Then, in the subsequent second write cycle, the ID code (2000 written in the register (61) is transferred to and written in the register (62), and the second I
The D code (2001) is written. In the subsequent third write cycle, the data written in the register (62) is transferred to and written in the register (63), and the second ID code (20) written in the register (61) is written.
01) is transferred to the register (62) for writing, and
The third ID (2002) and the control code (2005) are written in the register (61). Through the above three write cycles, the first ID code (2000) is stored in the register (63) and the second ID code (2001) is stored in the register (62).
A third ID code (2002) and a control code (2005) are stored in 1).

The 3-bit control code (2005) stored in the register (61) is decoded by the decoder (71). Each decoded signal has an AND gate (7
2), AND gate (73), AND gate (74),
It is input to the AND gate (75).

On the other hand, the register (63) and the register (6
2), the first I stored in the register (61) respectively
D code (2000), second ID code (200
1), the third ID code (2002) is the first
ID matching circuit (66) and second ID matching circuit (6
5) It is input to the third ID matching circuit (64), and confirmation is made as to whether it matches a predetermined ID code. If they match, the respective ID matching circuits output the first ID code matching signal (6000), the second ID code matching signal (6001), and the third ID code matching signal (6002), respectively.
And are set to active, that is, logic "1", and input to the AND gate (67). In the AND gate (67),
The logical product of the input ID code coincidence signals is calculated, and the result is AND gate (72), AND gate (73),
Input to the AND gate (74) and the AND gate (75). In each of these AND gates, the logical product of the ID code coincidence signal (6003) from 67 and each control signal from the decoder (71) is calculated, and the "clear control signal (103)" and "count stop control signal" are respectively obtained. (105) ","
Write control signal (109) "," Read control signal (10
7) "is output to the counting counter (10).

Reference numeral 76 is a toggle flip-flop, which inverts the selection signal (104) every time the decode signal from the decoder (71) is input. The selection signal (104) is input to the output selection circuit (20) and is output to the reset signal (101) or the interrupt signal (10).
2) Select whether or not.

5 and 6 are flow charts showing the procedure for giving an operation instruction to the protection circuit (1000). A program corresponding to this flowchart is stored in advance in a ROM such as 5003 in FIG. 7,
It is executed by the CPU (5000). In addition, FIG.
A configuration example of a computer system (5100) using the protection circuit (1000) of this embodiment is shown.

In FIG. 5, the control code patterns shown in FIG. 4 are "000", "001", "100", that is, "count counter clear", "count counter stop", "reset / interrupt output selection". The operation instruction procedure in the case of is shown.

First, it is assumed that the 3-byte format data shown in FIG. 3 is set in the RAM (5002) in advance.

In step S1, the first ID code stored in the RAM (5002) is protected by the protection circuit (100
Write to 0).

In step S2, the second ID code stored in the RAM (5002) is protected by the protection circuit (100
Write to 0).

In step S3, the third ID code stored in the RAM (5002) is protected by the protection circuit (100
Write to 0).

By the above steps, the ID detection circuit (3
Each ID code and control code are stored in the registers (63) to (61) of 1). Then, the stored ID codes are matched with each other, and the control circuit (41) decodes the control code and decodes it to the counter (10) and the output selection circuit (20). The control signal is sent to the counter (10) and the output selection circuit (2).
In 0), the corresponding processing is performed.

Next, referring to FIG. 6, when the control code patterns shown in FIG. 4 are "010" and "011", that is, "counting counter data write" and "counting counter data read", respectively. The operation instruction procedure is shown.

First, it is assumed that the 3-byte format data shown in FIG. 3 is set in the RAM (5002) in advance.

In step S11, the RAM (5002)
The first ID code stored in the protection circuit (10
00).

In step S12, the RAM (5002)
The second ID code stored in the protection circuit (10
00).

In step S13, the RAM (5002)
The third ID code stored in the protection circuit (10
00).

By the above steps, the ID detection circuit (3
Each ID code and control code are stored in the registers (63) to (61) of 1). Then, the stored ID codes are matched with each other, and the control code is decoded by the control circuit (41), and the decoded control signal, that is, the read control is given to the counter (10). A signal (107) or a write control signal (109) is sent. In the counting counter (10), the read control signal (10
When 7) is input, the current counter value of the counting counter (10) is output to the internal bus (106) in synchronization with the read cycle generated from the next CPU bus (100) to the internal bus (106). Get ready. When the write control signal (109) is input, the next CPU bus (10
In preparation for storing the write data on the bus in the counting counter (10) as an initial counter value in synchronization with the write cycle generated from 0) to the internal bus (106).

In step S14, the type of the control code is determined. If "010", a read cycle for the protection circuit (1000) is generated in step S15, and the current counter value from the counter (10) is CPU (5
000) reads.

If the type of control code is "010", a write cycle for the protection circuit (1000) is generated in step S16, and the initial count data is stored in the count counter (10).

FIG. 7 shows an example in which the protection circuit of this embodiment is applied to an information processing device (5100), which will be described below with reference to FIG.

The ROM (5003) stores a control program for controlling the protection circuit (1000) of this embodiment, various software executed by the information processing device (5100), etc., and is read by the CPU (5000). Is executed, interpreted and executed. The CPU (5000) controls the entire information processing device (5100). RAM (5002)
Is a storage memory for work when the CPU (5100) performs various processes. Application circuit (500
1) is composed of various interfaces or control circuits necessary for the information processing device (5100) to control an external device or the like. Reference numeral 1000 denotes a protection circuit (1000) of the present embodiment, which is connected to another device by a CPU bus (100), and which sends a reset signal (101) and an interrupt signal (102) to a CPU (50).
00).

In the CPU (5000), the protection circuit (10
When an interrupt request or a reset request is input from (00), it is determined that the operation of the CPU itself is above some level, and the CPU jumps to a predetermined restoration processing program stored in the ROM (5003) and starts execution. C
The PU (5000) periodically accesses the protection circuit (1000) that is counting down,
The count value is initialized so that the protection circuit does not issue an interrupt or a reset request.

Therefore, if some abnormality occurs in the CPU (500
0) and ROM (5003) where programs are stored
If the above occurs, the periodical access of the protection circuit (1000) is lost, and the above-mentioned interrupt request or reset request is generated. By this, it is possible to detect that some abnormality has occurred in the information processing device (5100), and it is possible to minimize system damage by performing the restoration process.

In the above embodiment, the register (63),
The register (62) and the register (61) are registers each having a 1-byte size, but it goes without saying that these may be variable according to the size of the ID code.

Similarly, in the above embodiment, the size of the control code was 3 bits, but this is not limited to this bit size and may be another bit size.

The counting counter (10) described above is used.
Shows an example in which the lapse of a predetermined time is measured by a countdown, but it goes without saying that, for example, the count value may start from zero and the count value may be counted up to the counter value indicating the predetermined time.

As described above, the protection circuit of this embodiment can reduce the overhead of the periodical access processing for updating the counter value for the protection circuit.

[0047]

As described above, according to the present invention, it is possible to detect the abnormality while minimizing the decrease in the throughput of the information processing system and protect the information processing apparatus.

[0048]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a protection circuit according to an embodiment.

FIG. 2 is a configuration diagram of an ID detection circuit and a control circuit of the protection circuit of this embodiment.

FIG. 3 is a diagram showing formats of an ID code and a control code to be written in the protection circuit.

FIG. 4 is a diagram illustrating types of control corresponding to patterns of control codes.

FIG. 5 is a flow chart of a control program for the protection circuit of the present embodiment.

FIG. 6 is a flowchart of a control program for the protection circuit of the present embodiment.

FIG. 7 is a diagram showing a configuration of an example of an information processing device to which the protection circuit of the present embodiment is applied.

Claims (1)

[Claims] 1. A protection device for an information processing apparatus, which measures a predetermined time interval, generates a predetermined time elapsed signal when the predetermined time has elapsed, and outputs the signal to the information processing apparatus, wherein an identification code including a control code is input. Inputting means, a comparing means for comparing the identification code and a predetermined identification code inputted in the inputting step, and a command for decoding the control code and inputting it to a counter at the same time as the comparison by the comparing means. In the comparison by the decoding means for generating a signal and the comparison means, if the identification code and the predetermined identification code match, the validation means validates the command signal, and the validation means validates the command signal. Input a command signal to initialize the measurement of a predetermined time, measure a predetermined time interval, and generate a predetermined time elapsed signal when the predetermined time has elapsed. Protection device of an information processing apparatus and an outputting means for outputting the information processing apparatus.