JPH07281891A - Microprocessor and method for generating execution address thereof - Google Patents

Abstract

PURPOSE:To function as the microprocessor even without having a program address control part by embedding a program address to be processed next in program data. CONSTITUTION:When a program code 3 is read out of a program storage memory 2, an address value needs to be inputted to the program storage memory 2 in advance. This address value is written in the program storage memory 2 together with a last program code. Consequently, the program code 3 and a next program address 7 can be read out of the program storage memory 2 at the same time, the next program address 7 is temporarily stored in a latch 8 and outputted as an address value once the program code 3 is read in by a program processing part 4, thereby easily generating a program execution address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor for generating the next execution address and an execution address generation method for the microprocessor.

[0002]

2. Description of the Related Art A conventional microprocessor and a method of generating an execution address of the microprocessor will be described with reference to FIG. FIG. 3 is a block diagram of a microprocessor having a program storage memory and performing processing while reading a program code as needed.

The microprocessor 1 is operating according to the program code 3 read from the program storage memory 2 while being processed by the program processing unit 4. Here, when reading the program code 3, the program processing unit 4 needs to instruct the program address control unit 5 in advance by using the address control signal 6 of the address information to be read next from the program storage memory 2.

[0004]

By the way, the program address control is, so to speak, an auxiliary operation that is not directly related to the original processing operation of the microprocessor 1, and is an overhead in terms of processing time. In terms of hardware, regardless of the scale of the actual processing unit of the microprocessor,
This is a part that requires a certain circuit scale, and particularly in a small-scale microprocessor, there has been a problem that the ratio of the address control unit to the entire circuit cannot be ignored.

An object of the present invention is to obtain a microprocessor for generating a next address of a program storage memory and a method for generating an execution address of the microprocessor without having a program address controller.

[0006]

In order to achieve the above-mentioned object, the present invention embeds a program address to be processed next in the program data, so that a microprocessor as a microprocessor can be provided without a program address control section. Provided are a microprocessor capable of providing a function and a method of generating an execution address of the microprocessor.

[0007]

According to the present invention, by embedding the program address to be processed next in the program data, the function as a microprocessor can be achieved without the program address control section.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of one embodiment. Similar to FIG. 2, the microprocessor 1 is operating while being processed by the program processing unit 4 according to the program code 3 read from the program storage memory 2.

When reading the program code 3 from the program storage memory 2, it is necessary to input an address value to the program storage memory 2 in advance. By writing this address value in the program storage memory 2 together with the previous program code, the program code 3 and the next program address 7 can be read simultaneously from the program storage memory. Is temporarily stored in the latch 8,
By outputting the program code 3 as an address value from the latch 8 when the program processing unit 4 reads it,
The program execution address can be easily generated.

The first address value for the program storage memory 2 can be realized by configuring the circuit so that the start address value can be loaded into the latch 8. Since the program processing unit 4 of the microprocessor 1 does not need to perform any work for address management of the program storage memory 2, it can concentrate on the actual work of the program and improve the processing efficiency. In addition, since hardware that controls the address of the program storage memory is rarely needed,
The circuit becomes very simple and the circuit can be miniaturized. Since a branch instruction is not required, the instruction decoder circuit scale of the program processing unit / the processing time is small /
Speeding up is possible.

In this embodiment, the program storage memory 2 is explained as a memory outside the microprocessor 1, but the present invention is also effective for a memory inside the microprocessor. In particular, when applied to a microcode memory inside a microprocessor, high-speed processing becomes possible, so that it is easy to increase the operation clock of the microprocessor.

This embodiment can be realized even when the conditional branch of the program is performed. When the conditional branch signal 9 is received from the program processing unit by giving the latch 8 an increment counter function and the conditional branch signal 9 does not come, the value of the next program address 7 is used as it is, and when the conditional branch signal 9 comes. The conditional branch can be realized by performing processing such as giving the value of the next program address 7 by +1.

FIG. 2 is a conceptual diagram of the program code. The program code consists of an executable statement a and an address b indicating the next address. Address 400 is a conditional statement, and if yes, address 500 is executed. If no, the value of address 7 is incremented by the conditional branch signal 9 and 501 is executed.

[0014]

According to the present invention, by embedding the program address to be processed next by the microprocessor in the program data of the microprocessor, the function as the microprocessor can be achieved without the program address control section. Therefore, the processing speed of the microprocessor can be increased, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a microprocessor using an execution address generation method for a microprocessor according to the present invention.

FIG. 2 is a conceptual diagram of a program code according to an embodiment.

FIG. 3 is a block diagram of a microprocessor using a conventional execution address generation method of the microprocessor.

[Explanation of symbols]

1 ... Microprocessor, 2 ... Program storage memory,
3 ... Program code, 4 ... Program processing unit, 5 ... Program address control unit, 6 ... Address control signal, 7 ...
Next program address, 8 ... Latch, 9 ... Conditional branch signal.

Claims (6)

[Claims] 1. A method of generating an execution address of a microprocessor, wherein the next execution address is embedded in a program code. 2. A method of generating an execution address of a microprocessor, wherein the next execution address is embedded in a microcode inside the microprocessor. 3. A microprocessor comprising a program processing unit for performing processing according to a program code read from a program storage memory, and a latch for storing an address in the program code and outputting the address to the program storage memory. 4. The microprocessor according to claim 3, wherein the program storage memory is a microcode memory. 5. The microprocessor according to claim 3, wherein the latch changes an address according to a conditional branch signal sent from a program processing unit. 6. The microprocessor according to claim 3, wherein the latch has an increment counter function, and counts up an address according to a conditional branch signal sent from a program processing unit.