JPH0727977B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including a trench capacitor and a transistor including a buried gate electrode, and a manufacturing method thereof.

(Prior Art) With the high integration of semiconductor memory devices in response to the demand for higher speed and smaller size of electronic devices, miniaturization of transistors and capacitors forming the semiconductor memory devices has been advanced. As the miniaturization of this semiconductor memory device progresses, the area occupied by the transistors or capacitors on the surface of the semiconductor substrate becomes smaller. As a result, there have been drawbacks such as a decrease in the capacitance of the capacitor, a decrease in the threshold voltage due to the short channel effect and a narrow channel effect in the transistor, and the occurrence of leakage current.

For the above-mentioned drawbacks, for example, reference: IEEE-Inter-
As disclosed in the national Electron Devices Meeting (lecture number 6.2, December 1986), the trench (Trench:
There is known a technique of using a so-called trench capacitor in which a trench) is formed and the capacitor oxide film formed on the inner surface of the trench also functions as a capacitor.

Further, in the above-mentioned literature, a so-called buried gate transistor is used, in which not only a capacitor is three-dimensionally configured and used, but also a transistor is formed in a region between adjacent trench capacitors in a depth direction of a semiconductor substrate. Techniques for forming a semiconductor memory device using the same have been disclosed.

The configuration of a conventional semiconductor memory device of this type disclosed in the above-mentioned document will be described below with reference to the drawings.

FIG. 2 is a device configuration diagram shown by a schematic sectional view of the conventional semiconductor memory device for explaining the configuration of the device. In the drawings, hatching showing a cross section is omitted except for some parts, and constituent components made of the same constituent material are shown with the same hatching.

According to the structure of the semiconductor memory device shown in FIG. 2, a second groove 15a for forming a capacitor is formed in a predetermined region of the semiconductor substrate 11 made of p-type silicon with the transfer gate region 13 interposed therebetween. Each of the 15b is formed and the second groove is formed.
Plate electrodes 19a and 19b made of polysilicon (poly-Si) are provided on 15a and 15b, respectively, with the capacitor oxide film 17 interposed therebetween. In the configuration of this semiconductor memory device, the capacitor oxide film 17 formed on the bottom surface and the side surface of the second trenches 15a and 15b is used as a capacitor, so that a sufficient memory capacity is ensured when the semiconductor memory device is miniaturized. You can

In addition, the transfer between the above-mentioned second grooves 15a and 15b
The semiconductor substrate 11 corresponding to the gate region 13 is ion-implanted with n-type impurities by using the above-mentioned plate electrodes 19a and 19b as a mask, so that the low resistance layer 21 (indicated by a dashed line in FIG. 2). Are formed.

Further, in the transfer gate region 13 described above, the gate electrode formation regions 23a and 23b and the drain region 25 between the gate electrode formation regions 23a and 23b are formed. Has a contact hole 29 for connecting the pit line 27 of the semiconductor memory device. Further, the first grooves 31a and 31b are formed in the gate electrode formation regions 23a and 23b, and the first grooves 31a are formed.
And 31b are provided with gate electrodes 35a and 35b, respectively, sandwiching the gate oxide films 33a and 33b.

On the other hand, on the surfaces of the above-mentioned plate electrodes 19a and 19b, plate electrode insulating oxide films 37a and 37b are formed, respectively, and the insulating oxide films 37a and 37b and the semiconductor substrate corresponding to the transfer gate region 13 are formed. Nitride film on the upper side of 11
39 are deposited.

In a similar configuration, the gate electrode insulating oxide film 41a or 41b is formed on the surfaces of the gate electrodes 35a and 35b, respectively, and further above the insulating oxide films 41a and 41b, and as described above. A mask oxide film 43 for reducing the coupling capacitance between the bit lines 27 and the gate electrodes 35a and 35b corresponding to the word lines is deposited on the upper side of the nitride film 39.

As described above, the transistor formed by using the first grooves 31a and 31b and the second groove 1 on the semiconductor substrate 11.
A capacitor configured by using 5a and 15b is provided, and these constituent components are provided as gate electrode insulating oxide films 41a and 41b, plate electrode insulating oxide films 37a and 37b, and nitride film 3
9 and the mask oxide film 43.

In the above-described conventional semiconductor memory device, since the gate electrode is formed in a state of being buried in the first groove formed in the semiconductor substrate, it is not necessary to make the diffusion depth of the low resistance layer particularly shallow. The apparent depth of the pn junction can be made shallow. Furthermore, since it is possible to effectively increase the channel length and the channel width with respect to the gate mask length and the gate mask width, it can be expected to suppress the short channel effect and the narrow channel effect.

(Problems to be Solved by the Invention) However, the above-mentioned document does not describe in detail the specific manufacturing technique of the conventional semiconductor memory device. It is judged that the low resistance layer is formed with a uniform depth in the semiconductor substrate corresponding to the transfer gate region before the formation of the first groove constituting the. Therefore, in the vicinity of the gate oxide film formed in the first groove and the end portion of the low resistance layer adjacent to the gate oxide film and diffused deepest in the depth direction of the semiconductor substrate (see FIG. 2). , Indicated by the electric field concentration region 45.), a local electric field concentration is caused, resulting in deterioration of the gate breakdown voltage.

In view of the above-mentioned conventional problems, an object of the present invention is to provide a semiconductor memory device having a high degree of integration and high reliability with a good yield.

(Means for Solving Problems) In order to achieve this object, according to the method for manufacturing a semiconductor memory device of the first invention of the present application, the first groove formed in the semiconductor substrate is used. A semiconductor memory device comprising: a configured transistor, a capacitor configured using a second groove formed in the semiconductor substrate, and a bit line connected to a drain region. In manufacturing a semiconductor memory device formed by reducing the depth of the low resistance layer in the vicinity of the first groove and increasing the depth of the low resistance layer in the region away from the first groove, The step of sequentially depositing the nitride film and the first oxide film on the semiconductor substrate on which the groove 2, the capacitor oxide film, the plate electrode, and the oxide film for insulating the plate electrode have been formed; Primary acid A step of sequentially removing the film, the nitride film, and the capacitor oxide film by etching, a step of depositing a side wall forming nitride film on the semiconductor substrate described above, and an anisotropic etching process on the side wall forming nitride film described above to form a gate. A step of forming a side wall around the electrode formation region, a step of forming a first groove by an etching process using the above-mentioned first oxide film, nitride film and side wall as a mask, and a step of forming the above-mentioned first groove A step of forming a gate oxide film on the side surface and the bottom surface; a step of depositing a gate electrode forming polysilicon layer on the above-mentioned semiconductor substrate and then forming a gate electrode by an etch-back process; and a step of forming the above-mentioned first oxide film. After removing by etching, a step of forming a low resistance layer by impurity ion implantation using the nitride film, the side wall and the gate electrode as a mask, and the gate using the nitride film and the side wall as a mask. A step of forming an oxide film for pole insulation, and a second oxide film is deposited on the above-mentioned nitride film and oxide film for gate electrode insulation using the resist pattern for lift-off defined in the drain region as a mask, and then this resist The method is characterized by including a step of lifting off the pattern and a part of the second oxide film deposited in the drain region, and a step of forming a contact hole in the drain region.

(Operation) Further, according to the structure of the method for manufacturing a semiconductor memory device of the invention of this application, the side wall provided around the gate electrode formation region serves as a mask, and the side wall around the first groove forming the transistor is surrounded. It is possible to reduce the depth of the low resistance layer and to increase the depth of the low resistance layer in the region away from the first groove.

(Embodiment) An embodiment of a method for manufacturing a semiconductor memory device of the present invention will be described below with reference to the drawings.

Furthermore, it should be understood that the embodiments described below are merely preferred examples of the present invention, and the present invention is not limited to the following embodiments.

1 (A) to 1 (H) are manufacturing process diagrams for explaining an embodiment of the present invention, and each drawing shows a cross section of a wafer at a manufacturing stage of a semiconductor memory device. Further, in these drawings, the shapes, dimensions and arrangement relationships of various components are only schematically shown to the extent that the present invention can be understood.
In the drawing, hatching and the like showing a cross section are omitted except for a part, and the same constituent components as those already described with reference to FIG. The same reference numerals are given. Further, in some cases, reference numerals may be omitted in the drawings, except for constituent components that are characteristic in each manufacturing process.

First, a wafer structure as shown in FIG. 1A is obtained by a conventionally known method. Therefore, after the semiconductor substrate 11 made of p-type silicon is isolated (not shown) by a selective oxidation method, the second trenches 15a and 15b are formed in predetermined regions of the semiconductor substrate 11 with the transfer gate region 13 interposed therebetween. Then, the capacitor oxide film 17 is formed on the side surfaces and bottom surfaces of the 15a and 15b. At this time, the capacitor oxide film 17
Are also formed on the surface of the semiconductor substrate 11 other than the second grooves 15a and 15b. Then, polysilicon is deposited and the groove 15
A and 15b are completely buried, and the polysilicon deposited on the transfer gate region 13 is removed by etching to form plate electrodes 19a and 19b.

Next, the wafer thus obtained is subjected to thermal oxidation treatment to form plate electrode insulating oxide films 37a and 37b on the surfaces of the plate electrodes 19a and 19b. Then, on the entire upper surface of this wafer, for example, chemical vapor deposition (Chemical
Vapor Deposition (CVD) method or any other suitable,
By the deposition method with excellent step coverage, the nitride film 47 and the first
The oxide film 49 is sequentially deposited to obtain a wafer in the state shown in FIG.

Next, the first oxide film 49, the nitride film 47, and the capacitor oxide film 17 in the portions corresponding to the gate electrode formation regions 23a and 23b of this wafer are sequentially removed by etching by a well-known photolithography etching method, and the substrate surface The openings are formed by exposing 11a and 11b. Subsequently, the sidewall forming nitride film 51 is deposited on the entire upper surface of the wafer after the etching process by the above-described CVD method, and the constituent components formed on the semiconductor substrate 11 are completely embedded. A wafer in the state as shown in B) is obtained.

Then, the side wall forming nitride film 51 deposited on the wafer is
For example, reactive ion etching (Re-active Ion Etchi
ng: RIE) anisotropic etching process,
The above-described nitride film 51 is left on the side surfaces of the openings formed in the gate electrode formation regions 23a and 23b, and these regions 23a and 2 are formed.
Side walls 53a and 53b are formed around 3b. Then, in this step, the first oxide film 49 exposed on the surface of the wafer and the side wall 53a are formed.
And 53b as masks, anisotropic etching is performed by the above-mentioned RIE method using any suitable etching gas capable of etching only silicon constituting the semiconductor substrate 11 to form the first grooves 55a and 55b. To do. Furthermore, the above-mentioned components 49, 53a and 53b used in this etching process.
Gate oxide film 57a
And 57b are formed to obtain a wafer in the state shown in FIG.

Subsequently, similarly to the case where the plate electrodes 19a and 19b are formed, a gate electrode forming polysilicon layer 59 (hereinafter, may be simply referred to as a poly-Si layer 59) is formed on the entire upper surface of the wafer. accumulate. After depositing the poly-Si layer 59, as shown in FIG. 1 (D), a resist material 61 made of any suitable material is applied so as to fill the irregularities formed on the surface of the semiconductor substrate 11, and Flatten the surface of the wafer.

Next, the gate electrodes 63a and 63b and the low resistance layer 65 are formed,
In order to obtain the wafer in the state shown in FIG. 1E, the resist material 61 and poly-Si provided on the wafer in FIG.
The layer 59 and the poly-Si layer 59 are etched back under an etching condition such that the resist material 61 and the poly-Si layer 59 have the same etching rate, thereby forming the gate electrodes 63a and 63b. Thereafter, by this step, the first oxide film 49 (see FIG. 1D) exposed on the surface of the semiconductor substrate 11 is selectively removed by etching.

Then, using the plate electrode insulating oxide films 37a and 37b and the nitride film 47 formed on the plate electrodes 19a and 19b of the wafer described above and the sidewalls 53a and 53b as a mask, for example, arsenic (As) or other An n-type impurity (indicated by an arrow a in the figure) is ion-implanted to form a low resistance layer 65 (indicated by a dashed line in the figure), and the state shown in FIG. To obtain the wafer.

The profile of the low resistance layer 65 formed by the above-mentioned process is the periphery of the first trenches 55a and 55b for forming a transistor in the semiconductor memory device by the action of the side walls 53a and 53b arranged by the above-mentioned process. It can be understood that the depth of the ion implantation can be made shallower and the depth of the ion implantation in the region away from the first groove can be made deeper.

Next, the gate electrodes 63a and 6 formed by the steps described above.
The respective surfaces of 3b are subjected to thermal oxidation treatment using the nitride film 47 and the side walls 53a and 53b as masks to form gate electrode insulating oxide films 67a and 67b. After that, the oxide film 67a
And at least the gate electrode 6 of the wafer on which 67b is formed.
A lift-off resist pattern 69 is defined so as to completely cover the region between 3a and the gate electrode 63b, and a second oxide film 71 is deposited on the entire upper surface of the semiconductor substrate 11 as shown in FIG.
A wafer in the state shown in is obtained. In this case, the second oxide film
It is preferable to deposit 71 so that the lift-off resist pattern 69 can be laminated at a low temperature such as a photo-CVD method so as not to damage it.

Further, the lift-off resist pattern 69 and the second oxide film 71 deposited on the upper side of the resist pattern 69 are lifted off. Through this step, at least the lift-off resist pattern 69 defining the gate electrode 63 is formed.
The above-mentioned second oxide film 71 is deposited on the entire upper surface of the wafer except for the portion corresponding to the drain region 73 between the a and the gate electrode 63b to obtain the wafer in the state shown in FIG. 1 (G). .

Next, using the above-described second oxide film 71 as a mask, the nitride film 47 and the oxide film 17 on the upper side of the region to be the drain region 73 of the semiconductor substrate 11 are sequentially removed by etching to open a contact hole 75. . After that, by the same process as the conventional one,
A bit line 77 made of, for example, tungsten silicide (WSi ₂ ) or any other suitable material is deposited, and further, an intermediate insulating layer, a wiring electrode, or other component (not shown) according to the design is provided. To complete the semiconductor memory device (FIG. 1 (H)).

As described above in detail, according to the method of manufacturing a semiconductor memory device of the present invention, the gate electrode forming poly-Si layer 5 is formed.
After depositing 9, without using a resist pattern,
By etching back, the gate electrodes 63a and 63b can be formed by self-alignment. Therefore, it is not necessary to perform photolithography etching after forming the first trenches 55a and 55b, which is suitable for manufacturing a semiconductor memory device having a fine structure.

In addition, in the opening of the contact hole 75, compared with the film thickness of the oxide film (corresponding to the above-mentioned capacitor oxide film 17) formed in the portion corresponding to the drain region 73, the second oxide film 71 or the gate is formed. By designing the electrode insulating oxide films 67a and 67b to be thick, it is possible to omit the photolithography process that requires strict alignment.

The above-described embodiment has been described as suitable conditions for facilitating the understanding of the present invention.
It is apparent that the etching conditions, and further the film thickness and other conditions can be arbitrarily changed and modified according to the design within the scope of the object of the present invention.

(Effects of the Invention) As is apparent from the above description, according to the method for manufacturing a semiconductor memory device of the present invention, the depth of the low resistance layer is reduced in the vicinity of the first groove forming the transistor. Then
It is possible to easily and easily manufacture a semiconductor memory device having a fine structure in which the depth of the low resistance layer is increased in the region away from the first groove, with high yield.

[Brief description of drawings]

1 (A) to 1 (H) are schematic manufacturing process diagrams of a semiconductor memory device used for explaining an embodiment of the invention, and FIG. 2 is a semiconductor memory device for explaining a conventional semiconductor memory device. It is a device block diagram shown by the schematic cross-sectional view of FIG. 11 ... Semiconductor substrate 11a, 11b ... Substrate surface 13 ... Transfer gate 15a, 15b ... Second groove 17 ... Capacitor oxide film 19a, 19b ... Plate electrode 21,65 ... Low resistance layer 23a, 23b ・ ・ ・ Gate electrode formation area 25,73 ‥ Drain area, 27,77 ‥‥ Bit line 29,75 ‥‥ Contact hole 31a, 31b, 55a, 55b ‥ First groove 33a, 33b, 57a, 57b ‥ Gate oxide film 35a, 35b, 63a, 63b ... Gate electrode 37a, 37b ... Plate electrode insulating oxide film 39, 47 ... Nitride film 41a, 41b, 67a, 67b ... Gate electrode insulating oxide film 43 ... Mask oxide film, 45 Electric field concentration region 49 First oxide film, 51 Side wall forming nitride film 53a, 53b Side wall 59. Gate electrode forming polysilicon (poly-Si) layer 61. Resist material 69. Lift-off resist pattern 71. Second oxide film a .. N-type impurities.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 7514-4M // H01L 29/78 301 V

Claims (1)

[Claims] 1. A step of sequentially depositing a nitride film and a first oxide film on a semiconductor substrate on which a second groove, a capacitor oxide film, a plate electrode and an oxide film for insulating a plate electrode are formed, and on the semiconductor substrate. Etching the first oxide film, the nitride film, and the capacitor oxide film in the gate electrode forming region in order; depositing a sidewall forming nitride film on the semiconductor substrate; and anisotropically forming the sidewall forming nitride film. Forming a side wall around the gate electrode forming region by a selective etching process, forming a first groove by an etching process using the first oxide film, the nitride film and the side wall as a mask, Forming a gate oxide film on the side surface and bottom surface of the groove, and forming a gate electrode by etching back after depositing a gate electrode forming polysilicon layer on the semiconductor substrate. Forming a low resistance layer by impurity ion implantation using the nitride film, the sidewalls and the gate electrode as a mask, after removing the first oxide film by etching, and oxidizing the gate electrode with the nitride film and the sidewall as a mask A step of forming a film, a step of depositing a second oxide film on the nitride film and the oxide film for insulating a gate electrode, and then a lift-off process using the lift-off resist pattern defined in the drain region as a mask; And a step of forming a contact hole in the drain region.