KR980011938A - A method of making self-aligned polysides using a planarized layer of material to expose a polysilicon structure to sequentially deposited metal layers reacted to form metal silicides - Google Patents

Abstract

The process of forming a metal silicide layer on polysilicon structures such as gates and interconnects forms an insulating layer on the polysilicon structure and removes the insulating layer until the insulating layer is substantially flattened to remove the insulating layer on the polysilicon structure. The thickness is within a predetermined thickness range, the planarized layer of insulation is etched until a portion of the polysilicon structure is exposed, a metal layer is deposited on the resulting structure, and the polysilicon structure is reacted with the metal layer to form a metal silicide layer It is simplified by forming.

Description

A method of making a self-aligned polyside using a planarized layer of material to expose a polysilicon structure to a sequentially deposited metal layer that is reacted to form metal silicide

FIELD OF THE INVENTION The present invention relates to polyside processes, and more particularly, to a self-aligned polyside process using a planarized layer of material to expose a polyside structure to a subsequently deposited metal layer that is reacted to form metal silicides.

Sheets of electrical conduction structure of such devices, such as gates of MOS transistors, emitters of bipolar transistors, local interconnection areas of MOS and bipolar transistors, and connection lines connecting these devices together with increasing integration of semiconductor devices. Resistivity is beginning to limit the speed at which these devices can operate.

One well-known technique for reducing the sheet resistivity of polysilicon gates and interconnects of conventional buried channel CMOS devices is to form layers of metal silicides across polysilicon gates and interconnects. The interconnect structure, known as the resulting gate and polyside structure, provides the lower resistivity of metal silicides in addition to the well known features of polysilicon.

1A-1B show cross-sectional views illustrating a standard polysilicon process as part of an overall buried channel CMOS process. As shown in FIG. 1A, the process includes a well region 12 in a lightly doped substrate 10 of opposite conductivity type, a series of field oxide regions FOX, regions of gate oxide 14 and polysilicon (poly). Begin by conventionally forming a layer 16 of (in addition to channel stop and thrash hold injection).

Following conventional n + doping of the polylayer 16, the polyside process begins with the deposition of the top layer of tungsten silicide (WSi2) 18. Thereafter, a gate / line mask 20 is formed and patterned on the layer of tungsten silicide 18 using standard photolithography techniques.

Once the mask 20 is formed, as shown in FIG. 1B, the unmasked region of silicide 18 and the upper region of poly 16 are then etched to form polysilicon gate 22 and interconnect 24. ). Therefore, in a conventional CMOS transistor, a polyside structure can be formed by simply depositing a layer of tungsten silicide on a layer of doped polysilicon.

One disadvantage of conventional buried channel CMOS devices, whether formed as polyside structures or not, is that the poly gates of both NMOS and PMOS transistors are heavily doped with the same n-type material. Although ideal for NMOS transistors, n-type gates make it difficult to achieve low slash voltages in PMOS transistors.

Therefore, more recent devices called "surface-channel" CMOS devices have been developed to optimize the performance of PMOS transistors. In surface-channel CMOS devices, the polysilicon gate of an NMOS transistor is doped with an n-type material, while the polysilicon gate of a PMOS transistor is doped with a p-type material.

However, in a surface-channel CMOS device, when the n-type gate of an NMOS transistor is connected to the p-type gate of the PMOS transistor by one of the n-type or p-type interconnect lines, the n-type or p-type interconnect line is p-type. Or pn junctions are formed at points where the n-type gates meet each other.

Therefore, in order to reduce the sheet resistivity of polysilicon gates and interconnects, as well as to avoid pn junctions, surface channel CMOS devices need to provide electrical connections between NMOS and PMOS devices using polysilicon or equivalent structures. Do.

One process for forming a surface-channel CMOS device into a polysilicon structure is simply to dope a poly layer in an NMOS region with an n-type material and to dope a poly layer in a PMOS region with a p-type material. In this approach, the polyside structure can then be formed by simply depositing a layer of tungsten silicide on top of the n- and p-type doped polysilicon layers.

2A-2C show that one process for forming the entire surface-channel CMOS device into a polysilicon structure is simply doping the polylayer in the NMOS region with n-type material and doping the polylayer in the PMOS region with p-type material. . In this approach, the polyside structure is then formed in the well region 32 in the n- and p-type doped substrates 30, a series of field oxide region FOX, regions of the gate oxide 34, and polysilicon (poly Begins with conventionally forming a layer 36.

Following conventional formation of the poly layer 36, an n implant mask 38 is formed over the PMOS region to protect the poly layer 36 in the PMOS region from n + doping of the poly layer 36 in the NMOS region. Subsequently, the unmasked area is doped with n-type material.

After poly layer 36 in NMOS region is doped with n-type material, n-injection mask 38 is removed and the process is performed from p + doping of poly layer 36 in PMOS region and poly layer 36 in NMOS region. It is repeated with a p injection mask (not shown) that protects.

Next, as shown in FIG. 2B, tungsten silicide (WSi2) 40 is deposited on top of the poly layer 36, followed by formation and patterning of the gate / line mask 42. Thereafter, as shown in FIG. 2C, the unmasked region of tungsten silicide 40 and the upper region of poly 36 are etched to form interconnects with the polysilicon gate of the device.

Therefore, in conventional buried-channel CMOS devices, the surface-channel polyside structure can also be formed by simply depositing a layer of tungsten silicide on top of the doped polysilicon layer. However, unlike buried-channel CMOS devices, the above-described process for forming surface-channel CMOS devices requires two additional masking steps after a conventional buried-channel CMOS process that dope the poly layer 36. do.

Another disadvantage of the surface-channel process described above is that a high temperature processing step is commonly used after the formation of the metal silicide layer. These high temperature excursions allow n + poly and p + poly via metal silicides so that one type of poly can be a counter doped by another type of poly, i.e., p-type ions moving from p + poly to n + poly. Dopant interdiffusion of the side can be induced in turn.

Therefore, because of the additional cost and complexity of using two additional masking steps in addition to the high temperature limit, this process is not a preferred approach to forming surface-channel CMOS devices.

Additionally, one of the drawbacks of using deposited metal silicides to form polyside structures, whether buried channel CMOS devices or surface-panel CMOS devices, is the tendency of the deposited metal silicide to break into thin pieces, There is a tendency to peel off the poly layer. Such cracking results in stresses placed on the polyside structure and are known to make it difficult to remove all remaining oxide from the surface of the polysilicon during the cleaning step prior to the deposition of the metal silicide layer.

Another approach commonly used to form silicides on top of gates and interconnects, as well as source and drain regions, is a process known as self-aligned silicides or salicides. In the salicide process, silicide is formed after the formation of the source and drain regions. As a result, the same implantation steps used to form the source and drain regions can be used to dope the polysilicon gate.

3A-3E show cross-sectional views of conventional salicide processes that are part of the overall surface-channel CMOS process. As shown in FIG. 3A, the process includes a well region 52 in a lightly doped substrate 50 of opposite conductivity type, a series of field oxide regions FOX, a region of gate oxide 54 and polysilicon (poly). Begin by conventionally forming a layer 56 of.

Following conventional formation of the poly layer 56, a gate / line mask 58 is formed and patterned on the layered portion of the polysilicon 56. Next, the unmasked regions of poly 56 are etched to form polysilicon gates 60 and interconnect lines 62 for NMOS devices, and polysilicon gates 64 and interconnect lines 66 for PMOS devices. ).

Subsequently, as shown in FIG. 3B, the mask 58 is removed and an n implantation mask 68 is formed over the PMOS region to protect the PMOS region. Once the mask 68 is in place, the NMOS region is again implanted with an n-type material to heavily dop the polysilicon gate 66, interconnect lines 64, and source and drain regions 70 and 72. This step forms a well known LDD structure.

Next, the n implant mask 79 is removed and this process protects the NMOS region during heavy p + doping of the poly gate 62, interconnect 68 and source and drain regions 74 and 76. p is repeated with an injection mask (not shown).

Subsequently, as shown in FIG. 3D, a layer of refractory metal 80 is formed on top of the device. Next, as shown in FIG. 3E, the layer of refractory metal 80 reacts to form polysilicon gates 62/66, interconnect lines 64/68, source region 70/74, and A layer of metal silicide 82 is formed over the drain region 72/76. The layer of metal 80 does not react significantly with the oxide spacer 78 or the field oxide region FOX.

After the layer of metal silicide 82 is formed, the unreacted metal layer 80 is removed by selective etching. The salicide process is self-aligned so that metal over the gate 62/66, interconnect 64/68, source region 70/74, and drain region 72/76 without the need for any masking steps A layer of silicide 82 is formed. The layer of metal 80 does not react significantly with the oxide spacer 78 or the field oxide region FOX.

However, one limitation of conventional salicide processes is that even if the metal layer does not react significantly with the oxide spacer, a thin trace of silicide may remain on the oxide spacer after selective etching. These traces can in turn create a state known as "bridging" in which the traces of silicide short the gate to the source or drain region.

In addition, as shown in FIGS. 3D and 3E, since the metal silicide is formed by the reaction of the underlying silicon with the metal layer, the salicide process consumes a portion of the silicon in the reaction. As a result, the salicide process results in a flatter shallower junction depth (CMOS devices typically use a shallower junction depth), which in turn can lead to junction leakage.

Another limitation of the conventional salicide process is that the width of the silicide interconnects drops below nearly 0.25 microns and the sheet resistivity of the silicided polysilicon wires increases. This increase in sheet resistivity is known to be caused by several mechanisms such as distorted silicide morphology (the so-called "smiling" salicide structure) and thin silicides, smaller grain size, and incomplete step strain.

Therefore, there is a need for a method for forming a layer of metal silicide over interconnects and polysilicon gates of conventional surface-channel CMOS devices that reduce or limit the above noted limitations.

1A-1B are cross-sectional views illustrating a standard polyside fabrication method as part of the overall buried channel CMOS fabrication method.

2A-2C are cross-sectional views illustrating a polyside fabrication method as part of an entire surface channel CMOS fabrication method.

3A-3E are cross-sectional views illustrating conventional silicide fabrication methods as part of the entire surface channel CMOS fabrication method.

4a-4c are cross-sectional views illustrating a first alternative manufacturing method in accordance with the present invention.

6A-6E are cross-sectional views illustrating the self-aligned polyside fabrication method of the present invention applied to a surface channel CMOS fabrication method.

7 is a cross-sectional view illustrating the first manufacturing method of the manufacturing method shown in FIGS. 6A-6E.

8 is a cross-sectional view illustrating a second alternative manufacturing method of the manufacturing method shown in FIGS. 6A-6E.

9 is a cross-sectional view illustrating a self-manufacturing method of the present invention applied to a buried channel CMOS fabrication method.

10A-10D are cross-sectional views illustrating the self-alignment method of the present invention as applied to an enhanced buried channel CMOS fabrication method.

11A-11D are cross-sectional views illustrating a first approach for using LOCOS forming field oxide in the manufacturing method of the present invention.

12A-12C are cross-sectional views illustrating a second approach for using LOCOS forming field oxide in the manufacturing method of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 30, 50: substrate 12, 32, 52: well region

16: polysilicon 14, 34, 54: gate oxide

18, 40, 82: silicide 62, 66: polysilicon gate

The present invention provides a self-aligning method of forming a metal silicide layer on a structure formed as part of a semiconductor device, such as a surface channel CMOS device, that reduces or eliminates the limitations present in conventional polyside and salicide manufacturing methods.

In the present invention, an insulating material layer is first formed on a semiconductor element to cover the structure by the insulating material layer. The insulating material layer is then removed to expose the surface of the structure until the insulating material layer is substantially flat. Thereafter, a metal layer is deposited on the exposed material layer and the exposed surface of the structure. The metal layer then reacts with the structure to form a metal silicide layer and an unreacted metal layer on the insulating material layer on the structure. The unreacted metal layer is removed from the insulating material layer, leading to a conventional post step process.

DESCRIPTION OF THE EMBODIMENTS Hereinafter, the features and advantages of the present invention will become more apparent by describing embodiments in which the principles of the present invention are used with reference to the accompanying drawings.

4A to 4C are cross-sectional views illustrating a self-aligned polyside method according to the present invention. As shown in FIG. 4A, the method of the present invention discloses a conventional form of a semiconductor device 100 that includes an electrically conductive polysilicon structure 110. For example, structure 110 may include a gate of a MOS transistor, an emitter of a bipolar transistor, a local interconnection material of a MOS or bipolar transistor (ie, a source region such as to facilitate contact between a doped region and a contact plug. Material formed in the doped region), or internal connection lines between the semiconductors.

In the case where device 100 and structure 110 are formed, the method of the present invention is directed to oxide, nitride, or oxide / nitride compounds for device 100 in which structure 110 is covered with insulating material layer 112. Deposition of the same insulating material layer 112 is disclosed. As shown in FIG. 4B, insulating material layer 112 may be subjected to chemical mechanical polishing (CMP), such as reflow or resist etch back, until insulating material layer 112 is substantially planar. Or by another technique, the top surface of the substrate 110 is exposed. (If the lower point of the insulating material layer 112 is lower than the upper surface of the substrate 110, the upper surface portion of the substrate 110 may be required to be removed so that the surface is almost flat.)

Next, a metal layer 114 such as titanium, cobalt, tungsten or nickel is deposited on the insulating material layer 112 and the exposed top surface of the substrate 110. Subsequently, as shown in FIG. 4C, metal layer 114 is reacted with polysilicon exposed to a nitrogen environment to form metal silicide layer 116 using a rapid thermal process (RTP).

In this regard, the metal silicide layer 116 is in a C49 phase called the C49 phase. The metal layer 114 is formed on the insulating material 112 layer but does not react sufficiently with the insulating material 112 layer (although a thin metal nitride layer may be formed on the metal 114 layer due to the nitrogen environment). After the metal silicide layer 116 is formed, the unreacted metal layer 114 (including thin metal nitride layer) is etched such as NH ₄ OH + H ₂ O ₂ + H ₂ O _{2 at} a ratio of 1: 1: 1. Removed with selective edges with chemicals.

Next, the metal silicide layer 116 is further crystallized by exposing the device 100 in a second RTP step. In this regard, the metal silicide layer 116 is in a so-called C54 or in a low resistivity phase. Next, the process continues to a conventional back-end process step.

5A-5C are cross-sectional views illustrating a first optional method in accordance with the present invention. As shown in FIG. 5A, the insulating material layer 112 may also be etched following a planarization step that allows sidewall portions of the structure 100 to be exposed.

As shown in FIG. 5B, when the sidewall portion of the structure 100 is exposed, the metal layer 114 is deposited on the insulating material layer 112 and the top and sidewall surfaces of the exposed structure 110. Thereafter, the method is continued as described above to manufacture the device shown in FIG. 5C.

In a second optional method of the present invention, rather than removing the insulating material layer 112 until the insulating material layer 112 is substantially planarized, the top surface of the substrate 110 is exposed and the removing step is performed on the substrate 110. When the thickness of the insulating material layer is within a predetermined thickness range, the termination is finished, and the insulating material layer 112 is substantially flattened.

Thereafter, the insulating material layer is etched until the surface of the substrate 110 is exposed. The method then continues as described above with the deposition of the metal layer 114.

In a third optional method of the invention, rather than planarizing and etching the insulating material layer 112 to expose the structure 110, the insulating material layer 112 may be masked and etched to expose the structure 110. There is. Thereafter, metal layer 114 is deposited and then reacted to form metal silicide layer 116. As mentioned above, the unreacted metal can then be removed by selective etching. However, this method is not self alignment and requires an additional masking step.

In a fourth optional method of the present invention, rather than depositing the metal layer 114 on the insulating material layer 112 and the exposed surface of the substrate 110, the tungsten layer may be selectively deposited by chemical vapor deposition (CVD). Can be. By the CVD method, the tungsten layer is formed only on the exposed surface of the substrate 110. Subsequent to chemical vapor growth of the metal layer 114, the method continues with a conventional backend processing step.

One method having particular advantages from the method of the present invention is a method of forming a surface channel CMOS device. 6A through 6E are cross-sectional views showing the present invention to which the method for forming the surface channel CMOS device is applied.

As shown in FIG. 6A, the surface channel method includes n well regions, trench field oxide regions (FOX), a series of gate oxide 154 regions, n ⁺ and p ⁻ polysilicon formed in a lightly doped p-type substrate. gate 156/158, n ^- and p ⁺ polysilicon interconnection line (160 to 162), n ^- / n ^- and p ⁺ / p ^- a source region ^{(164/166), n - / n} - and p ⁺ / p ^discloses a prior art form of a drain region (168/170), and (channel stop and along the injection threshold) surface channel including an oxide spacer (172) CMOS structure 200.

When the CMOS structure 200 is formed, the insulating material (oxide, nitride, or oxide / nitride compound) layer 112 may include gates 156/158, internal interconnects 160/162, spacers 172, and substrates 150. In the exposed region, field oxide region (FOX).

Thereafter, as shown in FIG. 6B, the insulating material layer 112 is removed (by CMP or other equivalent technique) until it is substantially planarized, and the top surface of the polysilicon gate 156/158 is exposed. (When the top surface of the polysilicon gate 156/158 is exposed, since the small amount is grown in the upper direction when the field oxide region (FOX) gate oxide region 154 is formed, the insulating material thin layer 112 has an internal connection line. Remains on the top surface of (160/162) in a thickness of approximately 50-80 mm 3.)

Next, as shown in FIG. 6C, the insulating material layer 112 and the oxide spacer 172 expose part of the upper and sidewall surfaces of the gates 156 to 158 and both sides of the internal connection line 160/162. Selectively etched away.

As shown in FIG. 6D, when the polysilicon gates 156/158 and the internal connection lines 160/162 are exposed, the surface channel method is internally connected with the insulating material layer 112 and the gates 156/158. Continuous deposition of metal layer 114 (titanium, cobalt, tungsten, or nickel) to a thickness of approximately 200 to 1000 microns with respect to the exposed top and sidewall surfaces of lines 160/162.

Subsequently, as shown in FIG. 6E, the metal layer 114 is exposed to polysilicon in a nitrogen environment to form the metal silicide layer 116 using a rapid heat treatment (RTP) of approximately 650 to 750 ° C. for 60 seconds. Reacts with

(As described above, in this respect, the metal silicide layer 116 is in C49, which is called the C49 phase.)

However, the metal layer 114 does not react sufficiently with the oxide spacer 172 or the insulating material layer 112 (even if a thin metal nitride layer is formed in the metal layer 114 due to the nitrogen environment). After the metal silicide layer 116 is formed, the unreacted metal layer 114 (including the thin metal nitride layer) is etch chemistry such as NH ₄ OH + H ₂ O ₂ + H ₂ O _{2 at} a ratio of 1: 1: 1. Removed with selective edges with water.

Next, the metal silicide layer 116 is further crystallized by exposing the structure in the second RTP step, which is nearly 800 to 850 ° C. for 10 to 60 seconds. (As described above in this respect, the metal silicide layer is in a so-called C54 Nan, called C54, or in a low resistance phase.) Subsequently, the method continues with a conventional backend treatment step.

In addition to the methods described in connection with FIGS. 6A-6E, optional numbers may be practiced within the spirit of the invention. For example, as shown in FIG. 7, the selection edge can be stopped after the top surface of the internal connection line 160/162 is exposed.

In addition, as shown in FIG. 8, chemical mechanical polishing of the insulating material layer may continue until the top surfaces of the gates 156/158 and the internal connection lines 160/162 are exposed. The method shown in FIG. 8 may then be continued using selective etching to expose a portion of the sidewall surfaces of the gates 156/158 and internal interconnects 160/162.

Furthermore, as described above, the removal (CMP planarization) step may include a thickness of the insulating layer in the gate 156/158 and the internal connection line 160/162 within a predetermined thickness range, and the insulating material layer 112 may be generally used. It can be terminated when planarized.

The predetermined thickness ranges from a few angstroms to thousands of angstroms remaining after chemical-mechanical polishing, slightly greater than zero.

In addition, as described above, rather than depositing the metal layer 114, a tungsten layer may be selectively deposited by chemical vapor deposition (CVD). By this CVD process, a tungsten layer may be deposited only on the exposed top and sidewall surfaces 156/158 and interconnect lines 160/162 of the gate.

An advantage of the CVD process is that the tungsten layer has a lower sheet resistance than the tungsten silicide layer. Thus, although the resistance is higher than the tungsten silicide layer, the two thermal process steps used above to form the silicide layer can be eliminated.

Thus, the self-aligned polyside process described forms a metal silicide layer on polysilicon structures such as gates and interconnect lines of surface channel CMOS devices. The polyside process of the present invention is self-aligned in that no masking step is required to form the silicide layer on the structure.

In addition to using two fewer masking steps than the polyside process described with reference to FIGS. 2A-2C, the metal silicide layer 116 is formed after the high temperature step in the present invention. As a result, the problem of dopant interdiffusion is almost eliminated. In addition, because it is formed by reacting the metal silicide layer 116 with polysilicon, the problem of splitting into thin pieces occurring in the deposited metal silicide layer is also greatly reduced.

Referring to the conventional silicide CMOS process described in Figures 3A-3E, no silicon in the source and drain regions is consumed during the formation of the metal silicide because the source and drain regions are not silicided in the surface channel process. As a result, the problem of junction leakage occurring in the silicided source and drain regions is also eliminated (although higher resistance is costly). In addition, since the source and drain regions are not silicided, the problem of bridging is also eliminated.

In addition, as shown in FIGS. 5A and 6C, by exposing a portion of the sidewalls of structures such as interconnect lines, the problem of increasing sheet resistance occurring in silicided regions less than approximately 0.25 microns wide is also reduced. . Because the silicided surface is no longer limited to only the top surface.

In addition to surface channel CMOS structures, the present invention may also be used in buried channel CMOS structures.

9 shows a buried channel structure 300 made conventionally except that the tungsten silicide deposition step is omitted. (See FIG. 1A). Thus, as shown in FIG. 9, after the spacer and source / drain regions have been made, the process of the present invention begins by first depositing a layer of insulating material 112 as described above. The process then continues as described above.

In addition, conventional buried channel processes can be further refined to obtain a simpler manufacturing process in view of the present invention. 10A-10D illustrate cross-sectional views illustrating the polyside process of the present invention as part of an improved buried channel CMOS process.

As shown in FIG. 10A, an improved buried channel process includes an n well region 152, a trenched field oxide region (FOX), a series of gate oxide regions 154 formed in a lightly doped p-type substrate 150. , Polysilicon gates (156/158), polysilicon interconnect lines (160/162), n ⁺ / n ^- and p ⁺ / p ^- source regions (164/166), n ⁺ / n ^- and p ⁺ / p ^- start the formation of the drain region (168/170) and an oxide spacer (172) buried channel CMOS structure 400, including (a channel stop and along the injection threshold).

CMOS structure 400 differs from conventional buried channel devices in that a polylayer, such as polylayer 16 (see FIG. 1A), is not covered with an overlapping layer of doping or silicide prior to patterning and etching.

Once the CMOS structure 400 is formed, the buried channel process of the present invention performs the steps described above, namely, deposition of the insulating material, planarization of the insulating material, and selective etchback of the insulating material to expose the sidewalls. Form the structure shown in FIGS. 10B, 10C, depending on the degree of planarization and etching performed.

As shown in FIGS. 10B, 10C, and 10D, polysilicon gates 156/158 and interconnect lines 160/162 are again exposed at this stage. Thus, in accordance with the present invention, the polysilicon gates 156/158 and interconnect lines 160/162 are implanted with n-type materials, such as arsenic, into the gates 156/158 and interconnect lines 160/162. Or, optionally, doped next by applying POCl 3 diffusion to gate 156/158 and interconnect line 160/162.

The process then continues as described above with the deposition of an overlapping layer of metal.

One of the advantages of the buried channel process described above is that polysilicon, such as polylayer 16 (see FIG. 1A), when polysilicon is not doped due to the smaller grain size and lower reflectivity of undoped polysilicon. It is easier to pattern and etch the layer. Thus, as described with reference to FIGS. 10A-10D, by doping polysilicon after the gate is formed, it is possible to better control the fabrication steps required to form the gate.

In addition, doped polysilicon oxidizes faster than undoped polysilicon. Thus, the polysilicon gate and interconnect lines are less oxidized during the processing step leading to the formation of the spacer 172. In addition, the doping of the gate and interconnect lines injects the n-type material into a portion of the upper region of insulating material layer 112, which in turn acts as a gettering site. As a result, the back-end processing step of depositing an oxide layer doped with phosphorus to form a gettering site can be eliminated.

In addition, although the process of the present invention has been described with reference to trenched field oxide regions (FOX), the present invention also applies to field oxide regions formed by local oxidation of silicon (LOCOS).

11A-11B illustrate cross-sectional views illustrating a first approach of applying the process of the present invention to field oxide regions formed of LOCOS. As shown in FIG. 11A, a conventional LOCOS process planarizes the field oxide regions (FOX) that extend on the top surface of the substrate 540 using standard CMP or other planarization techniques.

Once the field oxide region FOX is planarized, conventional steps are applied to form the underlayer structure. Thus, compared to trenched field oxide regions, the only significant difference with this approach is excessive lateral erosion of the field oxide regions formed with LOCOS.

12A-12C show cross-sectional views illustrating a second approach of applying the process of the present invention to a field oxide region formed of LOCOS. As shown in FIG. 12A corresponding to FIG. 6B, when a field oxide region formed of LOCOS is used, the initial planarization step is interrupted at the top surface of the interconnect line 160 due to the height of the step height of the field oxide region FOX. do.

Thus, as shown in FIG. 12B corresponding to FIG. 6C, the selective etching may expose only a portion of the sidewall of the gate 156/158 while exposing a large portion to the sidewall of the interconnect line 160. .

In an optional process, rather than forming a metal silicide layer across gate 156/158 and interconnect line 160, the metal silicide layer may be formed only on interconnect line 160. The performance of analog transistors is sensitive to the presence of an overlap layer of silicide. As a result, an optional process allows the silicide layer to be formed on the interconnect line, thereby reducing the sheet resistance of the line without changing the performance of the analog transistor.

Thus, following the planarization step shown in FIG. 12A or following an etch back exposing the faces of the interconnect line 160, the metal layer 114 is formed of an insulating material layer 112 and an exposed interconnect line. And may only be deposited on 160.

As shown in FIG. 12C, in another alternative approach, polishing of chemical-mechanical insulating material layer 112 is performed until both top surfaces of gate 156/158 and interconnect line 160 are exposed. Continues. And optionally, the process illustrated in FIG. 12C continues by performing a selective etch to also expose a portion of the sidewall surface of gate 156/158 and interconnect line 160.

It should be understood that various alternatives to the embodiments of the invention described herein may be used in practicing the invention. For example, although the present invention has been described with reference to n well CMOS processes, the present invention applies equally to p well and twin well CMOS processes. In addition, the present invention is not limited to surface channel and buried channel CMOS processes, but also applies to conventional NMOS and PMOS processes as well as a memory cell process.

Also, although structures such as gates 156/158 and interconnect lines 160/162 have been described as being formed of polysilicon, amorphous silicon or polycrystalline silicon germanium may also be used. Accordingly, the following claims will include methods and structures that define the scope of the invention and fall within the scope of these claims and their equivalents.

As described above, the present invention provides a method for forming a metal silicide layer on a structure formed as part of a semiconductor device such as a surface channel CMOS device, which reduces or eliminates the limitations present in conventional polyside and salicide manufacturing methods. Provide a self-aligning method.

Claims (71)

A method of forming a layer of metal silicide on a structure formed as part of a semiconductor device, the method comprising: forming an insulating material layer on a semiconductor device such that the structure is applied with a layer of insulating material, the insulating material layer being generally planar and Removing the insulator layer until the surface is exposed, depositing a metal layer on the exposed surface and the insulator layer of the structure, reacting the structure with the metal layer, and not reacting on the metal silicide layer and the insulator layer on the structure. Forming a layer of metal and removing an unreacted metal layer from the insulator layer. The method of claim 1, wherein the structure comprises a gate of a MOS transistor. 3. The method of claim 2, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. The method of claim 2 wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 3. The method of claim 2 wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. The method of claim 1 wherein the structure comprises an emitter of a bipolar transistor. 7. The method of claim 6, wherein the emitter is formed of a material selected from polysilicon, amorphous silicon, and polycrystalline germanium. 7. The method of claim 6, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 7. The method of claim 6, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitride composites. The method of claim 1 wherein the structure comprises interconnects. 11. The method of claim 10, wherein the interconnect is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. The method of claim 10 wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. The method of claim 10, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 2. The method of claim 1, further comprising etching the planarized layer of insulation until the sidewall portions of the structure are exposed. A method of forming a metal silicide layer on a structure formed as part of a semiconductor device, the method comprising forming an insulating material layer on a semiconductor device to apply the structure to the insulating film layer, and layering the metal material until the insulating material layer is substantially planarized Removing the thickness of the insulating layer on the structure so that the thickness of the insulating layer on the structure is within a predetermined thickness range, etching the planarized layer of the insulating material until a portion of the structure is exposed, and removing the metal layer on the insulating layer and the exposed structure. Depositing, reacting the structure with the metal layer to form a metal silicide layer and an unreacted metallobe on the insulation layer, and removing the unreacted metal layer from the insulation layer. How to. 16. The method of claim 15, wherein the structure comprises a gate of a MOS transistor. 17. The method of claim 16, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. The method of claim 16 wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 17. The method of claim 16, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 16. The method of claim 15, wherein the structure comprises interconnects. 21. The method of claim 20, wherein the emitter is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 21. The method of claim 20, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 21. The method of claim 20, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 16. The method of claim 15, wherein the structure comprises interconnects. 25. The method of claim 24, wherein the interconnect line is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 25. The method of claim 24, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 25. The method of claim 24, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. A method of forming a layer of metal silicide on a structure formed as part of a semiconductor device, the method comprising forming an insulating material layer on the semiconductor device to apply the structure to the insulating material layer, and until the insulating material layer is substantially planarized Removing the layer to expose the surface of the structure and selectively chemically vapor depositing a metal layer on the structure. 29. The method of claim 28, wherein the structure comprises a gate of a MOS transistor. 30. The method of claim 29, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 30. The method of claim 29, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 30. The method of claim 29, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 29. The method of claim 28, wherein the structure comprises an emitter of a bipolar transistor. 34. The method of claim 33, wherein the emitter is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 34. The method of claim 33, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 34. The method of claim 33, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 29. The method of claim 28, wherein the structure comprises interconnects. 38. The method of claim 37, wherein the interconnect portion is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 38. The method of claim 37, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 38. The method of claim 37, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. A method of forming a polyside on a semiconductor device formed on a substrate of a first conductivity type, wherein a plurality of active device regions, a field oxide region formed on a substrate that isolates the plurality of active device regions, and a doped region pair are respectively A plurality of spatially separated doped regions formed on the substrate such that they are formed within an active element region of the substrate, the doped regions defining a plurality of substrate channel regions such that each pair of doped regions within the active element region defines a corresponding substrate channel region. A plurality of gate oxide regions formed on the plurality of substrate channel regions, a plurality of gate oxide regions formed on each corresponding gate oxide region, and a plurality of gate oxide regions formed on the corresponding gate oxide regions A plurality of gates formed on the gate oxide region, each gate having sidewalls A device formed on the field oxide region, the interconnect line having sidewalls, and a plurality of spacers formed on the sidewalls of the gate and the sidewalls of the interconnect line, and on the field oxide region, the substrate gate, the coral interconnects and the spacers. Depositing an insulating material layer with a thickness, removing the insulating material layer until the insulating material layer is substantially flattened and exposing the surface of the gate, and removing the insulating material layer until the surface of both the gate and the coral connection line is exposed. Etching, depositing a metal layer on the insulation layer, the gate, the spacer, and the coral interconnect; reacting the gate, the coral interconnect, and the metal layer to form a metal silicide layer on the gate and the coral interconnect; Forming an unreacted layer on the layer, and removing the unreacted metal layer from the insulating material layer and the spacer, Characterized in that it comprises the method comprising the step, leaving a metal silicide layer on the site and a line connected coral. 42. The method of claim 41, wherein the first number of gates is doped to have a first conductivity type and the second number of gates is doped to have a second conductivity type. 43. The method of claim 42, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 43. The method of claim 42, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 43. The method of claim 42, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 43. The method of claim 42, wherein the field oxide region comprises a trenched field oxide region. 43. The method of claim 42, wherein the etching step is exposed to portions of the sidewalls of the interconnect lines. 42. The method of claim 41 wherein the gate has a single conductive form. 49. The method of claim 48, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 49. The method of claim 48, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 49. The method of claim 48, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 49. The method of claim 48, wherein the field oxide region comprises a trenched field oxide region. 49. The method of claim 48, wherein said etching step exposes sidewall portions of interconnect lines. 49. The method of claim 48, further comprising doping the gate and interconnect lines prior to doping the metal layer. A method of forming a polyside on a semiconductor device formed on a substrate of a first conductivity type, wherein a plurality of active device regions, a field oxide region formed on a substrate that isolates the plurality of active device regions, and a doped region pair are respectively A plurality of spatially separated doped regions formed on the substrate such that they are formed within an active element region of the substrate, the doped regions defining a plurality of substrate channel regions such that each pair of doped regions within the active element region defines a corresponding substrate channel region. A plurality of spatially separated doped regions, a plurality of gate oxide regions formed on the plurality of substrate channel regions such that each gate oxide region is formed on a corresponding substrate channel region, and each gate is formed on a corresponding gate oxide region. A plurality of gates and field oxide regions formed on the plurality of gate oxide regions to be formed An insulating material layer having a thickness on the field oxide region, the substrate gate, the coral interconnect and the spacer, the device comprising an interconnection line having a sidewall and a plurality of spacers formed on the sidewall of the gate and the sidewall of the interconnection. Depositing, removing the insulator layer, a portion of the gate and a portion of the spacer formed on the sidewalls of the gate until the insulator layer is substantially planarized and the top surface of the gate and the coral interconnect are exposed; Depositing a metal layer on the spacer, the gate and the coral interconnect, and reacting the gate and the coral interconnect and the metal layer to form a metal silicide layer on the gate and the coral interconnect and forming an unreacted layer on the insulating and spacer layers. Forming and removing the unreacted metal layer to form metal silicide on the gate and the coral interconnect Method characterized in that the method comprises having a step to leave. 56. The method of claim 55, further comprising etching the insulator layer and spacers to expose the sidewalls of the gate and the coral interconnect. A method of forming a polyside on a semiconductor device formed on a substrate of a first conductivity type, wherein a plurality of active device regions, a field oxide region formed on a substrate that isolates the plurality of active device regions, and a doped region pair are respectively A plurality of spatially separated doped regions formed on the substrate such that they are formed within an active element region of the substrate, the doped regions defining a plurality of substrate channel regions such that each pair of doped regions within the active element region defines a corresponding substrate channel region. A plurality of spatially separated doped regions, a plurality of gate oxide regions formed on the plurality of substrate channel regions so that each gate oxide region is formed on a corresponding substrate channel region, and each gate is formed on a corresponding gate oxide region Formed on the plurality of gate oxide regions, each having a plurality of sidewalls And a device formed on the field oxide region, the interconnect line having sidewalls, the device comprising a plurality of spacers formed on the sidewall of the gate and the sidewall of the interconnect line, and on the field oxide region, the substrate gate, the coral interconnect and the spacer. Depositing an insulating material layer having a thickness on the insulating layer, removing the insulating material layer until the insulating material layer is substantially planarized, so that the thickness of the insulating material layer is within a predetermined thickness region, and the surface of both the gate and the interconnect line. Etching the insulator layer until it is exposed, depositing a metal layer on the insulator layer, spacers, gates and coral interconnects, and reacting the gate and coral interconnects with the metal layer to react the metal silicide on the gates and coral interconnects Forming a layer, forming an unreacted layer on the insulating material layer and the spacer layer, and removing the unreacted metal layer And, leaving a metal silicide layer on the gate and the coral interconnect. 59. The method of claim 57, wherein the first number of gates is doped to have a first conductivity type and the second number of gates is doped to have a second conductivity type. 59. The method of claim 58, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 59. The method of claim 58, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 59. The method of claim 58, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 59. The method of claim 58, wherein the field oxide region comprises a trenched field oxide region. 59. The method of claim 58, wherein the etching step exposes portions of the sidewalls of the coralline. 59. The method of claim 58, wherein the gate has a single conductivity type. 65. The method of claim 64, wherein the gate is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and polycrystalline germanium. 65. The method of claim 64, wherein the metal layer is selected from the group consisting of tungsten, titanium, nickel and cobalt. 65. The method of claim 64, wherein the insulation layer is selected from the group consisting of oxidized, nitrided and oxidized / nitrided composites. 65. The method of claim 64, wherein the field oxide region comprises a trenched field oxide region. 65. The method of claim 64, wherein the etching step exposes portions of the sidewalls of the coralline. 65. The method of claim 64, further comprising doping the gate and interconnect lines prior to doping the metal layer. A method of forming a polyside on a semiconductor device formed on a substrate of a first conductivity type, comprising: a space-separated doped region formed on a substrate, the space-separated doped region defining a substrate channel region, and on the substrate channel region. Depositing a device having a gate oxide region formed on the gate oxide region, a gate formed on the gate oxide region, a gate having sidewalls, a spacer formed on the sidewalls of the gate, and an insulating material layer having a thickness on the substrate, the gate, and the spacer. Removing the insulator layer until the insulator layer is substantially planar, so that the thickness of the insulator layer on the gate has a predetermined thickness region, and etching the insulator layer until the surface of the gate is exposed; Depositing a metal layer on the insulating material layer and the gate, and reacting the gate with the metal layer to form a metal silicide on the gate. Characterized in that it comprises a method for was removed for steps and, a layer that is not reacted from the layers of insulating material forming a layer that is not reacted in the layer and the layers of insulating material, comprising the step, leaving a metal silicide layer on the gate. ※ Note: The disclosure is based on the initial application.