JPS63284851A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To make a semiconductor memory device, which is high in its integrity and its reliability, formable with good yield, by performing ion implantation so that depth of a low resistance layer on the periphery of first grooves for composition of a transistor is made small and that of the low resistance layer on a region distant from the first grooves is made large. CONSTITUTION:A nitriding film 57 provided with patterning processing for the formation of side walls on a drain region, a first oxidizing film 47 for the formation of first openings 53a, 53b, and second openings 55a, 55b, are respectively used as masks, and next second grooves 61a, 61b are formed in depth l1 in accordance with their design by means of self-alignment in respect to second openings 55a, 55b. Subsequently the nitriding film 57 for the formation of the side walls are provided with anisotropic etching processing so as to form the side walls 63a, 63b around the first openings formed on a gate electrode forming region. In succession, first grooves 65a, 65b are formed in depth l2 in accordance with their design by means of self-alignment in respect to the side walls, and at the same time second grooves 67a, 67b are formed in depth l1+l2. Accordingly a semiconductor memory device high in its integrity and its reliability can be formed simply, easily, and with good yield.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor memory device (1) comprising a trench capacitor and a transistor comprising a buried gate electrode.

(Prior Art) As semiconductor memory devices become more highly integrated in response to demands for higher speeds and smaller sizes of electronic devices, transistors and capacitors constituting the semiconductor memory devices are being miniaturized. As semiconductor memory devices become smaller, the area occupied by transistors or capacitors formed on the surface of a semiconductor substrate becomes smaller. This has resulted in disadvantages such as a decrease in capacitance of the capacitor, a decrease in threshold voltage due to short channel effects and narrow channel effects in the transistor, and generation of leakage current.

For the above-mentioned drawbacks, for example, literature: 1. E, E, E,
-Inter-national Electron
Devices Meetinq
As disclosed in the International Electron Devices Meeting (Lecture No. 6.2, December 1986), grooves (T) are formed in the depth direction of a semiconductor substrate.
A technique using a so-called trench capacitor is known in which a trench is formed and a capacitor oxide film formed on the inner surface of the trench also functions as a capacitor.

Furthermore, in the above-mentioned literature, a so-called buried gate transistor is used, in which a capacitor is not only configured three-dimensionally, but also a transistor is configured in the depth direction of a semiconductor substrate in a region between two adjacent trench capacitors. A technique for configuring a semiconductor memory device using the above has been disclosed.

Hereinafter, the configuration of the conventional semiconductor memory device disclosed in the above-mentioned document will be explained with reference to the drawings.

FIG. 2 is a schematic sectional view of a conventional semiconductor memory device of this type, in order to explain its structure. Note that in the drawings, hatchings indicating cross sections are omitted except for some parts, and components made of the same constituent materials are shown with the same hatchings.

According to the configuration of the semiconductor memory device shown in FIG. 2, a second groove 15a for forming a capacitor and +5b are respectively formed, and the capacitor oxide film 1 is formed in the second grooves 15a and +5b.
Plate electrodes 19a and +9b made of polysilicon (poly-St) are placed on both sides of the plate electrodes 7, respectively. In the configuration of this semiconductor memory device, the second trench 15a and the +5
Since the capacitor oxide film 17 formed on the bottom and side surfaces of the semiconductor memory device b is used as a capacitor, a sufficient storage capacity can be ensured when miniaturizing a semiconductor memory device.

Further, in the semiconductor substrate 11 corresponding to the transfer gate region 13 between the above-mentioned second groove 15a and +5b,
n using the plate electrodes 19a and +9b as masks.
By ion-implanting type impurities, the low resistance layer 21 (
) shown surrounded by a dashed line in FIG. 2 has been formed.

Roughly speaking, in the transfer gate region 13 mentioned above,
Gate electrode formation regions 23a and 23b and a drain region 25 between the gate electrode formation regions 23a and 23b are formed.
A contact hole 29 is formed to connect a bit line 27 of the semiconductor memory device. In addition, first grooves 31a and 311 are formed in the gate electrode forming regions 23a and 23b.
) are formed in the first grooves 31a and 31b,
Gate electrodes 35a and 35b are respectively provided with gate oxide films 33a and 33b in between.

On the other hand, plate electrode insulating oxide films 37a and 37b are formed on the surfaces of the plate electrodes 19a and +9b, respectively, and the insulating oxide films 37a and 37b,
Semiconductor substrate 1 corresponding to transfer gate region 13
A nitride film 39 is deposited on the upper side of 1.

As a structure similar to this, a gate electrode insulating oxide film 41a or 41 is provided on the surfaces of the gate electrodes 35a and 35b.
Roughly speaking, on the upper side of the insulating oxide films 41a and 41b and on the upper side of the above-mentioned nitride film 39,
A mask oxide film 43 is deposited to reduce the coupling capacitance around the gate electrodes 35a and 35b corresponding to word lines and the bit line 27, and to form the contact hole 29 in a self-aligned manner.

As described above, the first groove 31 is formed on the semiconductor substrate 11.
A transistor configured using the grooves 15a and 31b, and a capacitor configured using the second trench 15a and +5b7a are arranged, and these components are formed by forming a gate electrode insulating oxide film 4]a and 41b, and a plate. Oxide film for electrode insulation 3
7. The structure is such that the nitride film 39 and the mask oxide film 43 are covered.

Hereinafter, to the extent disclosed in the above-mentioned literature, this conventional method for manufacturing a semiconductor memory device, in particular, the process of forming the second groove constituting the plate electrode or the first groove constituting the gate electrode, and The process of arranging the contact wires will be briefly explained below.

In this device, after forming the second grooves 15a and 15111, plate electrodes 19a and +9b are formed by forming a capacitor oxide film 17, a polysilicon deposition process, and a photolithography process.

After that, the first grooves 31a and 31 are formed using photolithography.
After forming 1), forming gate oxide films 33a and 33b,
Gate electrodes 35a and 35b are formed by a polysilicon deposition process and a photolithography process.

In addition, the plate electrodes 19a and +9b and the gate electrode 35
A mask oxide film 43 is formed on the entire upper surface of the semiconductor substrate 11 with the semiconductor substrates 11a and 35t) insulated by the respective insulating oxide films.
Cover with.

Thereafter, at least the oxide film 43 deposited on the drain region Vt25 is removed by photolithography.

Roughly, an etching process for selectively removing silicon nitride is performed to remove the enriched film 39 remaining in the drain region 25, and a contact hole 29 for connecting the bit line 27 is opened.

Through such a process, the contact hole 29 can be formed in a self-aligned manner with respect to the gate electrodes 35a and 35b corresponding to one word line.

Thereafter, a bit line 27 made of, for example, tungsten silicide (WSi2) is deposited to obtain the semiconductor memory device shown in FIG. 2.

In the conventional semiconductor memory device described above, the gate electrode is formed embedded in the first groove formed in the semiconductor substrate, so there is no need to make the diffusion depth of the low resistance layer particularly shallow. , the apparent depth of the upper pn junction can be made shallower. Furthermore, since it is possible to effectively increase the channel length and channel width relative to the gate mask length and gate mask width, it is expected that short channel effects and narrow channel effects can be suppressed.

(Problems to be Solved by the Invention) However, in the above-described conventional method for manufacturing a semiconductor memory device, after forming the second groove constituting the plate electrode in the semiconductor substrate, the first groove constituting the gate electrode is formed. Form one. At this time, in forming the second grooves spaced apart with the transfer gate @fft in between, a photolithography process for forming the second grooves and a photolithography process for forming the first grooves are performed. During the photolithography process, it is necessary to allow a margin for alignment of the photomask. This causes the second groove and the first
There has been a problem in that it is difficult to miniaturize semiconductor memory devices by narrowing the spacing between the grooves and the grooves.

Furthermore, in the configuration of the conventional semiconductor memory device described above, before forming the first groove constituting the gate electrode, a low resistance layer is formed at a uniform depth in the semiconductor substrate corresponding to the transfer gate region. is formed. Therefore, the gate oxide film formed in the first trench and the gate oxide film and the v
aWi and near the end of the low-resistance layer that is diffused deepest in the depth direction of the semiconductor substrate (electric field concentration region 4 in Fig. 2).
Shown as 5. ), which causes local electric field concentration, leading to deterioration of gate breakdown voltage.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method of manufacturing a semiconductor memory device for producing a highly integrated and highly reliable semiconductor memory device with a high yield.

(Means for Solving the Problems) In order to achieve this object, the method for manufacturing a semiconductor memory device of the present invention includes a step of depositing a first oxide film on a semiconductor substrate, and a step of depositing a first oxide film on a semiconductor substrate as described above. a step of simultaneously forming a first opening and a second opening by etching away the first oxide film of the semiconductor substrate; a step of depositing a nitride film for sidewall formation on the semiconductor substrate; a step of etching away the above-mentioned sidewall forming nitride film to expose the above-mentioned second opening; and a step of forming a shallow second groove using the above-mentioned second opening by etching treatment. , a step of anisotropically etching the aforementioned sidewall forming nitride film to form a sidewall around the aforementioned first opening, and simultaneously forming the aforementioned second groove and first groove through the etching treatment. A step of simultaneously forming a gate oxide film and a capacitor oxide film by thermal oxidation treatment; A step of depositing a polysilicon layer on the semiconductor substrate described above, and then simultaneously forming a gate electrode and a plate electrode by an etch-back treatment. a step of etching away the first oxide film in the transfer gate region described above; a step of forming a low resistance layer by implanting impurity ions using the sidewalls, gate electrode, and plate electrode as masks; A step of forming a second oxide film on the above-mentioned semiconductor substrate by an oxidation method, a step of defining a lift-off resist pattern in the drain region on the above-mentioned semiconductor substrate, and a step of forming a third oxide film on the above-mentioned semiconductor substrate. a step of lifting off the above-mentioned lift-off resist pattern and a third oxide film deposited on the resist pattern; and a process capable of selectively removing silicon oxide from the above-mentioned semiconductor substrate. The method is characterized in that it includes a step of performing a trenching process to open a contact hole.

(Function) According to the method of manufacturing a semiconductor memory device of the present invention, a nitride film for sidewall formation patterned on a drain region and a first oxide film forming a first opening and a second opening are formed. As a mask, first, with a depth of β according to the design,
A second groove is formed with a self-alignment line related to the second opening.

Thereafter, the sidewall forming nitride film described above is anisotropically etched to form a side V around the first opening formed in the gate electrode forming region. Subsequently, a first groove with a depth I22 according to the design is formed using a dark self-line on the side wall, and at the same time, the above-mentioned second groove is formed with a depth β1+12.

Further, by thermally oxidizing the polysilicon forming the gate electrode or the plate electrode and the silicon forming the semiconductor substrate, a second oxide film as an intermediate insulating layer is grown. Next, when forming a contact hole for arranging a bit line, a third
After depositing an oxide film and increasing the thickness of the oxide film on the surface of the semiconductor substrate other than the drain region, the resist pattern described above is lifted off.

After that, an etching process that can selectively remove an oxide film is performed on the surface of the semiconductor substrate, and a contact hole is formed by removing at least the oxide film formed in the drain region. There is.

Roughly, using the side V provided around the upper side of the first groove for forming the gate electrode, ions are implanted into the semiconductor substrate corresponding to the source/drain regions to form a low resistance layer. The structure is as follows.

(Embodiments) Hereinafter, embodiments of the method for manufacturing a semiconductor memory device of the present invention will be described with reference to the drawings.

It should be noted that the embodiments described below are merely preferred examples of the present invention, and it should be understood that the present invention is not limited only to the following embodiments.

FIGS. 1A to 1L are manufacturing process diagrams of the present invention, and each figure shows a cross section of a wafer at a manufacturing process stage. Further, each figure is schematically illustrated to the extent that the present invention can be understood, and therefore, the shape, size, and arrangement relationship of each component are not limited to the illustrated example. In addition, in the figures, hatchings and the like indicating cross sections are omitted except for some parts, and as in Figure 2, constituent components made of the same constituent materials are indicated with the same hatchings. Components that are the same as those already explained with reference to FIG. 2 are denoted by the same reference numerals, except for the components that are characteristic of the present invention. In general, symbols in the figures may be omitted except for constituent components that are characteristic in each manufacturing process.

First, a semiconductor substrate 11 made of p-type silicon is separated into elements (not shown) by a selective oxidation method, and then a chemical vapor deposition (Chem.
ical Vapor Deposition:CVD
) Law 1. : The first oxide film 47 is deposited by any other suitable method. After that, by a conventionally known method,
Semiconductor substrate 11 corresponding to gate electrode formation regions 23a and 23b and plate electrode formation regions t149a and 49b
A first resist pattern 51 is defined so that the surface thereof is opened. Subsequently, the resist pattern 51
The first oxide film 4 in the predetermined region described above is etched using etching gas that can selectively remove silicon oxide using the mask as a mask.
7 is removed by etching to form first openings 53a and 53b and second openings 55a and 55b, as shown in FIG. 1(A).
A wafer in the state shown in is obtained.

Next, a sidewall-forming nitride film 57 is deposited over the entire upper surface of the semiconductor substrate 11 from which the first resist pattern 51 has been removed, for example, by CVD or any other suitable method. After that, at least the second openings 55a and 5
A second resist pattern 59Iv is defined so that the sidewall forming nitride film 57 deposited on the sidewalls 5b can be removed by etching, and the etching process is performed by using the resist pattern 59 as a mask to selectively remove only the nitride film. . Through this step, a wafer in the state shown in FIG. 1B is obtained in which the second openings 55a and 55b described above are exposed again.

Next, using the above-described second resist pattern 59 or the patterned sidewall forming nitride film 57 and first oxide film 47 as a mask, etching is performed by any suitable method capable of selectively etching away only silicon. For example, the depth β.

(Described later) Unfinished second grooves 61a and 6 having 8
1t) to obtain a wafer in the state shown in FIG. 1(C).

Subsequently, the sidewall forming nitride film 57 described above is subjected to, for example, reactive ion etching (Reactive IonE etching).
An anisotropic etching process such as tchinq (RIE) is performed, and the side surfaces of the first openings 53a and 53b, which are exposed again by this etching process, are formed around the gate electrode forming regions 23a and 23b. Side walls 63a and 63b are formed around the stepped portion, respectively, and the first
A wafer in the state shown in Figure (D) is obtained.

Next, the above-mentioned sides W63a and 63b and the first oxide film 47 are masked by any suitable method capable of selectively etching and removing only silicon, similar to the process already explained using FIG. 1(C). For example, the first grooves 65a and 65b having a depth β2 are formed by etching the grooves 65a and 65b.
, the second grooves 63a and 63b!
, Deep I! ++Az) second grooves 67a and 6
7b to obtain a wafer in the state shown in FIG. 1(E). Subsequently, the above-described wafer is subjected to thermal oxidation treatment to form the first grooves 65a and 65b and the second groove 67.
gate oxide films 69a and 69a and 67b, respectively.
b, capacitor oxide film 71a and ? +'b is formed. Thereafter, a polysilicon layer 73 (hereinafter also referred to as ρoly-3i layer 73) is deposited on the entire upper surface of the semiconductor substrate 11, for example, by CVD or any other suitable method. After that, the poly-3
A resist material 75 made of any suitable material is applied so as to fill in the irregularities generated on the surface of the i-layer 73, and the surface of the wafer is flattened to obtain a wafer in the state shown in FIG. 1(F).

Next, under etching conditions such that the etching speed of the resist material 75 and the poly-3i layer 73 are equal,
At least to the extent that the surface of the first oxide film 47 is exposed.
By etching back the resist material 75 and poly-3i layer 73, gate electrodes 77a and 7
7b and plate electrodes 79a and 79b are formed to obtain a wafer in the state shown in FIG. 1(G).

Subsequently, after defining the third resist pattern 81, the first oxide film 4 remaining in the transfer gate region 13 is etched by an etching method that can selectively remove silicon oxide.
Remove 7. After that, the third resist pattern 81 described above or the first oxide film 47 remaining after the aforementioned removal and the gate electrode? ? a and? 7b and plate electrode 79a
and 79b and the sides 163a and 63b as masks, for example, arsenic (^S) or any other suitable n-type impurity (indicated by arrow a in FIG. 1(H)) is ion-implanted. A wafer in the state shown in FIG. 1(H) on which a low resistance layer 83 (indicated by a dashed line in the figure) is formed is obtained.

The profile of the low resistance layer 83 formed by the above-described process is similar to that of the first grooves 65a and 65b for forming a transistor in a semiconductor memory device due to the effect of the sides W63a and 63b provided by the above-described process. It can be seen that the groove can be formed by shallowing the depth of ion implantation in the periphery and increasing the depth of ion implantation in the region away from the first trench. Such a profile essentially eliminates the electric field concentration region (see FIG. 2).

Next, after removing the third resist pattern 81 described above, a second oxide film 85 is formed by a thermal oxidation process to a desired thickness according to the design, and the wafer is placed in the state shown in FIG. 1(I). get.

The second oxide film 85 formed by the above-described process is generally formed to be thicker on the polysilicon surface than on the silicon surface.

Next, at least the gate electrode 77a of the above-mentioned wafer
A lift-off resist pattern 87 is defined to cover a region (corresponding to the drain region 25) where a contact hole is to be formed between the wafer and the gate electrode 77b, and a third oxide film 89 is deposited on the entire upper surface of the wafer. Figure 1 (J)
A wafer in the state shown in is obtained.

In order to avoid damaging the lift-off resist pattern 87, it is preferable to deposit the third oxide film 89 using a method that allows lamination at a low temperature, such as photo-CVD. It is.

Subsequently, the above-mentioned lift-off resist pattern 87 and the third oxide film 8 deposited on the upper side of the resist pattern 87 are formed.
9 and lift off. After that, a portion of the second oxide film 85 formed by the process described in FIG. 1(I) corresponding to the drain region 25 exposed on the wafer surface by the above-mentioned lift-off process is removed. For example, a contact hole 91 is opened by an etching process capable of selectively removing silicon oxide, thereby obtaining a wafer in the state shown in FIG. 1(K).

In the process of opening the contact hole 91 described above, the third M
The thickness of the oxide film 89 is reduced by at least an amount corresponding to the thickness of the second oxide film 85 formed in the drain region 25. Therefore, in the thermal oxidation treatment in the step of forming the second oxide film 85 described above (see FIG. 1(I)), the thickness of the second oxide film 85 remaining due to the silicon oxide etching step is reduced as an intermediate binding layer. It is preferable to use a film with a thickness that can sufficiently perform the functions described above.

Subsequently, a bit line 93 made of, for example, tungsten silicide (WSiz) or any other suitable material is formed by a process similar to the conventional method, and an intermediate insulating layer, wiring electrodes, or other structures according to the design are formed. A semiconductor memory device is completed by arranging components (not shown) (see FIG. 1 (
death)).

The embodiments of this invention have been described in detail above as preferred conditions for facilitating understanding of this invention. However, the present invention is not limited to the above embodiments. For example, in the steps described with reference to FIGS. 1(C) to (E), the second groove formed in the semiconductor substrate 11 is , the case where the groove is formed deeper than the first groove has been described. However, the etching step for forming the second grooves 61a and 61b explained in FIG. When forming the cylinder 2
The groove and the first groove can be formed to have the same depth.

It is clear that the dimensions of each component, film thickness conditions, deposition method, etching conditions, and other conditions may be arbitrarily changed or modified according to the design within the scope of the purpose of the present invention. .

(Effects of the Invention) As is clear from the above description, the method for manufacturing a semiconductor memory device of the present invention has the above-described structure, which reduces the depth of the low-resistance layer around the first trench constituting the transistor. Ion implantation can be carried out by making the depth of the low resistance layer shallower and increasing the depth of the low resistance layer in the region away from the first groove. Since the second groove is formed by a self-line using the same mask, there is no need for alignment of resist masks that accompanies miniaturization of semiconductor memory devices.

Therefore, a local electric field is generated near the gate oxide film formed in the first trench and the edge of the low resistance layer that is adjacent to the gate oxide film and is diffused deepest in the depth direction of the semiconductor substrate. Concentration can be suppressed, and a highly reliable semiconductor memory device having a high integration density can be simply and easily manufactured with a high yield.

[Brief explanation of drawings]

1A to 1L are schematic manufacturing process diagrams of a semiconductor memory device for explaining the present invention in detail. FIG. 2 is a diagram of a semiconductor memory device for explaining a conventional semiconductor memory device. FIG. 2 is a configuration diagram of the device shown in a schematic cross-sectional view. 11...Semiconductor substrate 13...Transfer gate region 15a, +5b
---M2 grooves 17, 71a, 71b...Capacitor oxide film 19
a, 19b, 79a, 79b---Plate electrodes 21, 83...Low resistance layers 23a, 23b...Gate electrode formation region 25...
・Drain region, 27.93...Bit line 29, 9
1...Contact holes 31a, 31b...First grooves 33a, 33b, 69a, 69b=gate oxide films 35a, 35b, 77a, ? 7b...gate electrode 3
7a, 37b...Oxide film 39 for plate electrode insulation
...Nitride film 4! a, 41b...Oxide film 43 for gate electrode insulation
...Mask oxide film, 45...Electric field concentration region 47
...First oxide films 49a, 49b...Plate electrode formation region 51...
...First resist pattern 53a, 53b...First opening 55a, 55b...Second opening 57...Nitride film for sidewall formation 59...Resist pattern 61a of ivy 2 , 61b...-Second groove (depth β,) 63a
, 63b ----Side wall 65a, 65b = first groove (depth β2) 67a
, 67b = second groove (depth β1+122) 73...
... Polysilicon (poly-Si) layer 75 ... Resist material 81 ... Third resist pattern 85 ... Second oxide film 87 ... Resist pattern for lift-off 89 ...
-Third oxide film, a...n-type impurity. Patent applicant: Oki Electric Chestnut Co., Ltd.

Heshi) ) Todo □ 11 no m-'S+To＼ To, Mi~-〆

Claims (1)

[Claims] (1) A second layer comprising a capacitor oxide film and a plate electrode.
A semiconductor memory device is manufactured in which a first trench including a low resistance layer, a gate oxide film and a gate electrode, and a bit line connected to a drain region are disposed on a semiconductor substrate. a step of depositing a first oxide film on the semiconductor substrate; a step of etching away the first oxide film on the semiconductor substrate to simultaneously form a first opening and a second opening; a step of depositing a sidewall-forming nitride film on the substrate; a step of etching away the sidewall-forming nitride film deposited on the plate electrode forming region to expose the second opening; and a step of exposing the second opening by etching the second opening. Use the second opening to open the second
forming a shallow groove around the first opening by anisotropic etching the sidewall forming nitride film; forming a sidewall around the first opening by etching the second groove and the first opening; A step of simultaneously forming a groove, a step of simultaneously forming a gate oxide film and a capacitor oxide film by thermal oxidation treatment, and a step of depositing a polysilicon layer on the semiconductor substrate and then forming a gate electrode and a plate electrode by an etch-back treatment. a step of etching away the first oxide film in the transfer gate region; and a step of forming a low resistance layer by implanting impurity ions using the sidewalls, gate electrode, and plate electrode as masks; forming a second oxide film on the semiconductor substrate by a thermal oxidation method; defining a lift-off resist pattern in a drain region on the semiconductor substrate; and depositing a third oxide film on the semiconductor substrate. Lifting off the lift-off resist pattern and a third oxide film deposited on the resist pattern; and etching the semiconductor substrate to open a contact hole. A method for manufacturing a semiconductor memory device.