JPH07273225A - Non-volatile semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To enhance a non-volatile semiconductor memory device having a floating gate in data reliability. CONSTITUTION:A floating gate 23 is disposed on a silicon substrate 21, and a control gate 25 is arranged partially overlapping the floating gate 23. The surface of the silicon substrate is stepped, and the control gate 25 is set so as to make its base located below that of the floating gate 23. By this setup, a protrusion produced on the control gate 25 facing the float,ing gate 23 is separated from the floating gate 23, and an FN conduction hardly occurs between the protrusion of the control gate 25 and the floating gate 23. Therefore, no charge is injected into the floating gate 23 in a non-selection state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a method of manufacturing the same.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: El
(ectrically Erasable Programmable ROM)
Each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a memory cell transistor having a double gate structure, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Data is erased by extracting charges from the floating gate to the control gate by FN conduction (Fowler-Nordheim tunneling).

FIG. 9 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate, FIG.
0 is the XX sectional view. This figure shows a split gate structure in which the control gate is arranged side by side with the floating gate. An oxide film (LOCO) that is selectively thickly formed on the surface region of the P-type silicon substrate 1
A plurality of isolation regions 2 made of S) are formed in a strip shape to partition the element region. The floating gate 4 is arranged on the silicon substrate 1 with the oxide film 3 interposed therebetween so as to extend between the isolation regions 2. This floating gate 4
It is arranged independently for each memory cell. In addition, the oxide film 5 on the floating gate 4 is
Is thickly formed in the central portion of the floating gate 4 and the end portion of the floating gate 4 is formed at an acute angle to facilitate electric field concentration. Silicon substrate 1 on which a plurality of floating gates 4 are arranged
Control gates 6 are arranged on the floating gates 4 corresponding to respective columns. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3.
Further, the floating gates 4 and the control gates 6 are arranged such that adjacent columns are line-symmetrical to each other. An N type drain region 7 and a source region 8 are formed in the substrate region between the control gates 6 and in the substrate region between the floating gates 4. The drain region 7 is
The source regions 8 are surrounded by the isolation regions 2 between the control gates 6 and are independent of each other, and the source regions 8 are continuous in the direction in which the control gates 6 extend. The floating gate 4, the control gate 6, the drain region 7 and the source region 8 form a memory cell transistor. Then, the aluminum wiring 10 is arranged on the control gate 6 with the oxide film 9 interposed therebetween in a direction crossing the control gate 6. The aluminum wiring 10 is connected to the drain region 7 through the contact holes 11.

In the case of such a memory cell transistor having a double gate structure, the current flowing between the source and the drain varies depending on the amount of charges injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the drain current of a specific memory cell transistor is changed, and the difference in operating characteristics caused thereby is associated with the write data.

FIG. 11 is a circuit diagram of the memory cell portion shown in FIG. In the memory cell transistor 12 having a double gate structure arranged in 3 rows × 3 columns, each gate has a word line 1
3, the drain is connected to the bit line 14 and the source is grounded. In practice, the control gate 6 itself is the word line 13 and the aluminum wiring 10 is the bit line 14. Then, the word line 13 is connected to the row decoder, and the bit line 14 is connected to the column decoder.
Each is selectively activated. As a result, the specific memory cell transistor 12 is designated in response to the row address and the column address.

[0006]

In the memory cell transistor having the split gate structure as described above, the protrusion 15 is formed on the floating gate 4 side at the portion where the control gate 6 contacts the silicon substrate 1 as shown in FIG. . The protrusion 15 insulates the floating gate 4 and the control gate 6 from each other.
This is due to the depression of the oxide film 3 caused by the floating edge of the floating gate 4 when the oxide is thermally oxidized. Therefore, FN conduction is likely to occur between the protrusion 15 of the control gate 6 and the floating gate 4, and when the potential of the source region 8 that is common to each column is increased when writing data, the FN conduction occurs. In some memory cell transistors, electric charges may be injected into the floating gate 4. Therefore, the data written in each memory cell is no longer maintained, leading to a decrease in reliability.

Therefore, it is an object of the present invention to prevent charges from being injected into the floating gate of a memory cell transistor in a non-selected state and improve reliability.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is a semiconductor substrate of one conductivity type and is disposed on the semiconductor substrate in an electrically independent state. A floating gate, a control gate adjacent to the floating gate and at least partially overlapped with each other, and a reverse conductivity type formed in a substrate region opposite to a side of the floating gate facing the control gate. A first semiconductor region; and a second semiconductor region of opposite conductivity type formed in a substrate region opposite to a side of the control gate facing the floating gate,
It is characterized in that there is provided a step having a lower side on the control gate side between a surface region of the semiconductor substrate on which the floating gate is arranged and a surface region of the semiconductor substrate on which the control gate is arranged.

Then, in the manufacturing method, a step of forming an oxidation resistant film having an opening corresponding to a formation position of the floating gate on the first gate material layer laminated on the semiconductor substrate of one conductivity type; A step of selectively oxidizing the first gate material layer according to the opening of the oxidation resistant film to form an island-shaped thick oxide film; and the gate material layer located under the island-shaped thick oxide film The gate material layer and a part of the surface of the semiconductor substrate are selectively removed by etching to leave an electrically independent floating gate, and a step is formed on the semiconductor substrate at a position where the floating gate is formed. A step of forming an interlayer insulating film by oxidizing the exposed surfaces of the floating gate and the semiconductor substrate, and a step of stacking on the interlayer insulating film. Selectively removing the gate material layer by etching to form a control gate that at least partially overlaps the floating gate, and an impurity of an opposite conductivity type in the substrate region adjacent to the floating gate and the control gate. Is formed to form first and second semiconductor regions of opposite conductivity type.

[0010]

According to the nonvolatile semiconductor memory device of the present invention,
By providing a step between the surface of the control gate in contact with the semiconductor substrate and the surface of the floating gate in contact with the semiconductor substrate, the protrusion on the floating gate side of the control gate is separated from the floating gate. Therefore, FN conduction is less likely to occur between the floating gate and the floating gate. Therefore, even if the potential of the source region of a specific memory cell transistor is increased to write data, no charge is injected into the floating gate in the memory cell transistor having the common source region.

According to the manufacturing method of the present invention, the first
When the floating gate is formed by selectively etching the gate material layer of, a part of the surface of the semiconductor substrate is also etched at the same time, so that the surface of the semiconductor substrate becomes low at the part where the control gate is formed, The protrusion generated on the floating gate side of the control gate separates from the floating gate. Further, when the exposed surface of the floating gate is oxidized to form the interlayer insulating film, the oxide film is less likely to have a recess between the semiconductor substrate and the floating gate, and thus the control gate formed along the interlayer insulating film is not affected. Causes no large protrusions and makes it difficult for electric field concentration to occur on the floating gate side of the control gate.

[0012]

1 is a sectional view of a memory cell portion of a non-volatile semiconductor memory device of the present invention, and FIG. 2 is an enlarged sectional view showing a main portion of a memory cell transistor. A plurality of floating gates 23 are independently arranged on a P-type silicon substrate 21 with an oxide film 22 interposed therebetween. The floating gate 23 is arranged so as to straddle a plurality of strip-shaped isolation regions that partition the element region on the surface of the silicon substrate 21. In addition, the floating gate 23
The oxide film 24 covering the gate electrode is thickly formed in the central portion of the floating gate 23, and the end portion of the floating gate 23 is formed at an acute angle. Each floating gate 2 is formed on the silicon substrate 21 on which the floating gate 23 is arranged.
The control gate 25 is arranged corresponding to 3. The control gate 25 is arranged so that a part thereof overlaps the floating gate 23 via the oxide film 24 and the remaining part contacts the silicon substrate 21 via the oxide film 22. Also,
The surface of the silicon substrate 21 is provided with a step between a portion in contact with the control gate 25 and a portion in contact with the floating gate 23 so that the bottom surface of the control gate 25 is lower than the bottom surface of the floating gate 23. These floating gate 23 and control gate 25
Are arranged so that each column is line-symmetric. An N-type drain region 26 and a source region 27 are formed in the substrate region between the adjacent control gates 25 and the substrate region between the floating gates 23. The drain region 26 is surrounded by the isolation region between the control gates 25 and is independent of each other, and the source region 27 is continuous in the direction in which the control gate 25 extends. The positions where the floating gate 23, the control gate 25, the drain region 26, and the source region 27 are arranged are the same as those in the conventional memory device, and correspond to the plan view shown in FIG. Then, on the control gate 25, an aluminum wiring 29 is arranged via the oxide film 28 in a direction intersecting the control gate 6, and the aluminum wiring 29 is connected to the drain regions 26 through the contact holes 30, respectively.

The larger the level difference provided on the surface of the silicon substrate 21, the higher the effect can be expected. However, if step coverage is taken into consideration, the two levels of the level difference that occur in the semiconductor substrate 1 in the conventional memory cell transistor (FIG. 12) can be expected. It is preferably about 3 times. For example, in the conventional memory cell transistor, the step difference of the semiconductor substrate 1 is about 180 Å, while the step difference of about 500 Å is provided.

Each operation of writing, erasing and reading data in the above memory device is performed as follows, for example. In the write operation, the potential of the control gate 25 is 2V and the potential of the drain region 26 is 0.8V.
V, and the potential of the source region 27 is 12V. As a result, hot electrons generated near the drain region 26 are accelerated toward the floating gate 23, and the oxide film 2
It is injected into the floating gate 23 through 2 to write data. At this time, in the memory cell transistor in which the source region 27 is common and in the non-selected state, the potential of the floating gate 23 rises due to the capacitive coupling between the floating gate 23 and the source region 27, but the bottom surface of the floating gate 23 and the control gate Due to the step provided between the control gate 25 and the bottom surface of the floating gate 25, no charge is injected from the control gate 25 to the floating gate 23 by FN conduction. That is, since the step is provided between the bottom surface of the floating gate 23 and the bottom surface of the control gate 25, as shown in FIG.
The protrusion generated on the floating gate 23 side is separated from the floating gate 23, and FN conduction does not easily occur.

On the other hand, in the erase operation, the potentials of the drain region 26 and the source region 27 are set to 0V and the control gate 25 is set to 14V. As a result, the electric charge held in the floating gate 23 is transferred to the oxide film 2 by FN conduction from an acute angle portion of the end of the floating gate 23.
The data is erased by passing through 2 and being discharged to the control gate 25. In data erasing, batch erasing is possible by uniformly applying a voltage to all memory cell transistors. Then, in the read operation, the potential of the control gate 25 is set to 4 V and the drain region 2
6 is set to 2V and the source region 27 is set to 0V. At this time, if charges are injected into the floating gate 23, the potential of the floating gate 23 becomes low, so that a channel is formed under the floating gate 23 and a drain current flows. On the contrary, if no charge is injected into the floating gate 23, the floating gate 23
, The channel is formed under the floating gate 23 and the drain current flows. Therefore, the current flowing out from the drain region 26 is detected by a sense amplifier to turn on / off the memory cell transistor.
The determination of OFF, that is, the determination of written data is performed.

3 to 8 are cross-sectional views of respective steps for explaining the method of manufacturing the nonvolatile semiconductor memory device of the present invention. FIG. 3: First Step A polycrystalline silicon layer 32 is laminated on a P-type silicon substrate 21 with an oxide film 31 interposed therebetween, and an oxide film 33 is formed on the surface of this polycrystalline silicon layer 32. Further, a nitride film 34 serving as an oxidation resistant mask is formed on the oxide film 33, and the nitride film 34 is formed.
Is patterned by a well-known photolithography technique, and an opening 35 is formed at a position where the floating gate 23 will be formed later.

FIG. 4: Second Step The oxide film 33 is selectively oxidized by using the nitride film 34 as an anti-oxidation mask, and a thick oxide film 36 is formed in the opening 35 portion of the nitride film 34.
To form. The thick oxide film 36 is formed by growing the oxide film 33 on the surface side and the polycrystalline silicon layer 32 side.
The polycrystalline silicon layer 32 has a thin film thickness at that portion.

FIG. 5: Third step After removing the nitride film 33, the polycrystalline silicon layer 32 and the oxide film 31 are etched leaving the portion below the thick oxide film 36, thereby forming the floating gate 23. At this time, the surface of the silicon substrate 21 is over-etched to form a step on the surface of the silicon substrate 21.

FIG. 6: Fourth Step By thermally oxidizing the exposed surface of the silicon substrate 21 and the side surface of the floating gate 23, the control gate 2 is formed.
Then, the oxide film 22 serving as the gate insulating film and the oxide film 37 serving as the interlayer insulating film are formed. In this thermal oxidation, the oxide film 36 left on the floating gate 23 grows and becomes the oxide film 24 that insulates the floating gate 23 and the control gate 25 from each other.

FIG. 7: Fifth Step A polycrystalline silicon layer 38 is laminated so as to cover the floating gate 23, and the polycrystalline silicon layer 38 is patterned to form the control gate 25. In the control gate 25 thus formed, the surface in contact with the silicon substrate 21 is lower than that of the floating gate 23, and the protrusion generated on the floating gate 23 side is shown in FIG.
It is smaller than the protrusion 15 generated in the conventional control gate 6 shown in FIG.

FIG. 8: Sixth step Using the floating gate 23 and the control gate 25 as a mask, N type impurity ions are introduced into the substrate region between the floating gates 23 and the substrate region between the control gates 25.
For example, phosphorus ions (P) are implanted to form the drain region 26 and the source region 27. By the way, source area 2
Regarding No. 7, it is necessary to expand to the region below the floating gate 23 in order to be able to control the potential of the floating gate 23 by being combined with the floating gate 23. Therefore, the formation of the drain region 26 and the formation of the source region 27 are performed in different steps, and the implantation energy of phosphorus ions at the time of forming the source region 27 is increased so that the N-type impurity ions can easily spread. Alternatively, the source region 27 is formed by implanting twice to make the impurity concentration of the source region 27 higher than that of the drain region 28.

In the subsequent process, the surface of the control gate 25 and the exposed surface of the oxide film 22 are thermally oxidized and a new oxide film 28 is formed.
Then, a contact hole 30 is formed in the drain region 26, and then an aluminum wiring 29 connected to the drain region 26 is formed. Therefore, as shown in FIG. 1, a memory cell transistor in which the bottom surface of the control gate 25 is lower than the bottom surface of the floating gate 23 is formed.

In the above embodiment, the N type drain region 26 and the source region 27 are formed on the P type silicon substrate 21.
Although the case of the N-channel type for forming the is illustrated, it is also possible to configure the P-channel type using an N-type silicon substrate.

[0024]

According to the present invention, the step provided between the bottom surface of the control gate of the memory cell transistor and the bottom surface of the floating gate separates the projection of the control gate from the floating gate, and the floating gate is separated from the control gate. It becomes difficult for FN conduction to occur. Therefore, when writing data to a specific memory cell, it is possible to prevent charges from being injected into the floating gate in a memory cell transistor having a common source region.
The reliability of the data can be improved by preventing the once written data from being arbitrarily inverted.

Further, according to the manufacturing method of the present invention, when the interlayer insulating film between the floating gate and the control gate is formed, the oxide film on the side surface of the floating gate is unlikely to be dented. The protrusions on Therefore, electric field concentration is less likely to occur at the protrusions of the control gate, and in addition to increasing the distance between the protrusions of the control gate and the floating gate,
The effect of preventing FN conduction from the control gate to the floating gate is great.

Furthermore, since the step is provided between the floating gate and the control gate, the charge is accelerated at the step and injected into the floating gate, so that the efficiency of data writing can be improved. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a memory cell portion of a semiconductor memory device of the present invention.

FIG. 2 is an enlarged cross-sectional view of a memory cell transistor of the semiconductor memory device of the present invention.

FIG. 3 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor memory device of the present invention.

FIG. 4 is a sectional view showing a second step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 5 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 6 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 7 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 8 is a cross-sectional view showing a sixth step of the method for manufacturing a semiconductor memory device of the present invention.

FIG. 9 is a plan view of a memory cell portion of a conventional semiconductor memory device.

FIG. 10 is a cross-sectional view of a memory cell portion of a conventional semiconductor memory device.

FIG. 11 is a circuit diagram of a memory cell portion.

FIG. 12 is an enlarged cross-sectional view of a memory cell transistor of a conventional semiconductor memory device.

[Explanation of symbols]

1, 21 Semiconductor substrate 2 Separation region 3, 5, 9, 22, 28, 31, 33, 36, 37 Oxide film 4, 23 Floating gate 6, 25 Control gate 7, 26 Drain region 8, 27 Source region 10, 29 Aluminum wiring 11, 30 Contact hole 12 Memory cell transistor 13 Word line 14 Bit line 32, 38 Polycrystalline silicon layer 34 Nitride film 35 Opening

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, a floating gate arranged on the semiconductor substrate in an electrically independent state, and a control gate adjacent to the floating gate and at least partially overlapped with each other. A first semiconductor region of opposite conductivity type formed in a substrate region of the floating gate opposite to the side facing the control gate, and a side opposite to the side of the control gate facing the floating gate. A second semiconductor region of opposite conductivity type formed in the substrate region of the semiconductor substrate, the surface region of the semiconductor substrate on which the floating gate is disposed, and the surface region of the semiconductor substrate on which the control gate is disposed. A non-volatile semiconductor memory device, characterized in that a step is formed between the control gate and the control gate. 2. A step of forming an oxidation resistant film having an opening corresponding to a formation position of a floating gate on a first gate material layer laminated on a semiconductor substrate of one conductivity type, and the first gate material. Selectively oxidizing the layer in accordance with the opening of the oxidation resistant film to form an island-shaped thick oxide film, and leaving the gate material layer under the island-shaped thick oxide film, leaving the gate A step of selectively removing a material layer and a part of the surface of the semiconductor substrate by etching to form an electrically independent floating gate and forming a step on the surface of the semiconductor substrate that becomes higher at a position where the floating gate is formed. And a step of oxidizing the exposed surfaces of the floating gate and the semiconductor substrate to form an interlayer insulating film, and etching a second gate material layer stacked on the interlayer insulating film. By selectively removing the floating gate to form a control gate that at least partially overlaps the floating gate, and by implanting an impurity of a reverse conductivity type into a substrate region adjacent to the floating gate and the control gate. And a step of forming first and second semiconductor regions, the method for manufacturing a non-volatile semiconductor memory device.