KR100278332B1 - Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a method of manufacturing the same. A conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate in an electrically independent state, a control gate adjacent to the floating gate and at least partially overlapping the floating gate, and facing the control gate of the floating gate; A first semiconductor region of reverse conductivity type formed in the substrate region on the opposite side from the side of the side, and a second semiconductor region of reverse conductivity type formed in the substrate region on the side of the control gate opposite to the floating gate. The center portion is formed thinner than the end portion in the direction in which the thickness of the floating gate crosses the control gate, and is formed almost uniformly in the direction parallel to the control gate.

Description

Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof

1 is a plan view of a memory cell portion of a conventional semiconductor memory device.

2 is a cross-sectional view of the X-X ray portion of FIG.

3 is a cross-sectional view of the Y-Y line portion of FIG.

4 is a circuit diagram of a memory cell portion.

5 is an enlarged cross-sectional view of a conventional memory cell transistor.

6 is a perspective view of a memory cell portion of the semiconductor memory device of Embodiment 1;

7 is a cross-sectional view of the X-X ray portion of FIG.

8 is a cross-sectional view of the Y-Y line portion of FIG.

9 is a sectional view showing a first step of the manufacturing method of Example 1. FIG.

10 is a cross-sectional view showing a second step of the manufacturing method of Example 1. FIG.

11 is a sectional view showing a third step of the manufacturing method of Example 1. FIG.

12 is a sectional view showing a fourth step of the manufacturing method of Example 1. FIG.

FIG. 13 is a sectional view showing a fifth step of the manufacturing method of Example 1. FIG.

14 is a sectional view showing the sixth step of the manufacturing method of Example 1. FIG.

FIG. 15 is a sectional view of a memory cell portion of the semiconductor memory device of Embodiment 2. FIG.

16 is an enlarged cross-sectional view of the memory cell transistor of Embodiment 2. FIG.

17 is a sectional view showing the first step of the manufacturing method of Example 2. FIG.

18 is a cross-sectional view showing a second step of the manufacturing method of Example 2. FIG.

19 is a sectional view showing a third step of the manufacturing method of Example 2. FIG.

20 is a sectional view showing a fourth step of the manufacturing method of Example 2. FIG.

21 is a sectional view showing the fifth step of the manufacturing method of Example 2. FIG.

FIG. 22 is a sectional view showing the sixth step of the manufacturing method of Example 2. FIG.

FIG. 23 is a plan view of a memory cell portion of the semiconductor memory device of Embodiment 3. FIG.

FIG. 24 is a sectional view of the X-X ray part of FIG.

25 is a sectional view showing the first step of the manufacturing method of Example 3. FIG.

26 is a sectional view showing the second step of the manufacturing method of Example 3. FIG.

27 is a sectional view showing the third step of the manufacturing method of Example 3. FIG.

28 is a sectional view showing the fourth step of the manufacturing method of Example 3. FIG.

29 is a sectional view showing the fifth step of the manufacturing method of Example 3. FIG.

FIG. 30 is a sectional view of a memory cell portion of another semiconductor memory device of Embodiment 3. FIG.

31 is a sectional view showing a first additional step of the manufacturing method of Example 3. FIG.

32 is a cross-sectional view showing a second additional step of the manufacturing method of Example 3. FIG.

33 is a plan view of a memory cell portion of the semiconductor memory device of Embodiment 4;

FIG. 34 is a cross-sectional view of the X-X ray portion of FIG.

35 is a sectional view showing the first step of the manufacturing method of Example 4. FIG.

36 is a cross-sectional view showing a second step of the manufacturing method of Example 4. FIG.

37 is a sectional view showing the third step of the manufacturing method of Example 4. FIG.

38 is a sectional view showing the fourth step of the manufacturing method of Example 4. FIG.

39 is a sectional view showing the fifth step of the manufacturing method of Example 4. FIG.

40 is a cross-sectional view showing the sixth step of the manufacturing method of Example 4. FIG.

41 is a cross-sectional view showing a seventh step of the manufacturing method of Example 4. FIG.

42 is a plan view of a memory cell portion of the semiconductor memory device of Embodiment 5. FIG.

43 is a sectional view of the X-X-ray part of FIG. 42;

FIG. 44 is a circuit diagram of a memory cell portion of the semiconductor memory device of Embodiment 5. FIG.

45 is a sectional view showing the first step of the manufacturing method of Example 4. FIG.

46 is a cross-sectional view showing a second step of the manufacturing method of Example 4. FIG.

47 is a sectional view showing the third step of the manufacturing method in Example 4. FIG.

48 is a sectional view showing the fourth step of the manufacturing method of Example 4. FIG.

49 is a sectional view showing the fifth step of the manufacturing method of Example 4. FIG.

* Explanation of symbols for main parts of the drawings

21 silicon substrate 22 isolation region

23,25 oxide film 24 floating gate

26: control gate 27: drain region

28: predetermined area

The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a method of manufacturing the same.

In electrically erasable programmable ROM (EEPROM) in which a memory cell is composed of a single transistor, each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a double gate structure memory cell transistor, data writing is performed by accelerating and injecting hot electrons generated at the drain region side of the floating gate into the floating gate. Then, data is erased by releasing charge from the floating gate to the control gate by FN conduction (Fowler-Nordheim tunneling).

1 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate, and FIGS. 2 and 3 are cross-sectional views of its X-X and Y-Y lines. In this figure, the split gate structure in which the control gate is arranged in parallel with the floating gate is shown.

A plurality of separation regions 2 made of an oxide film LOCUS formed thickly in the surface region of the P-type silicon substrate 1 are formed in a single-cell shape to partition the element region. The floating gate 4 is arranged to sandwich the oxide film 3 on the silicon substrate 1 and span the separation region 2. This floating gate 4 is arranged independently for each memory cell. In addition, the oxide film 5 on the floating gate 4 is formed thick at the center portion of the floating gate 4, so that an end portion of the floating gate 4 is formed at an acute angle so that electric field concentration easily occurs. The control gate 6 is disposed corresponding to each column of the floating gate 4 on the silicon substrate 1 on which the plurality of floating gates 4 are arranged. This control gate 6 is arranged so that a portion overlaps the floating gate 4 and the remaining portion is cut to the silicon substrate 1 through the oxide film 3.

In addition, these floating gates 4 and control gates 6 are arranged so that neighboring columns are linearly symmetric with each other. An N-type drain region 7 and a source region 8 are formed in the substrate region between the control gate 6 and the substrate region between the floating gate 4. The drain region 7 is surrounded by the isolation region 2 between the control gates 6 and is independent of each other, and the source region 8 continues in the extending direction of the control gate 6. The floating gate 4, the control gate 6, the drain region 7 and the source region 8 constitute a memory cell transistor. Then, the aluminum wiring 10 is disposed on the control gate 5 in the direction crossing the control gate 6 via the oxide film 7. These aluminum eyes 10 are connected to the drain regions 7 through the contact holes 11, respectively.

In the case of the memory cell transistor having the double gate structure as described above, the line flow flowing between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting electric charge into the floating gate 4, the drain current of a particular memory cell transistor is varied, and the difference in operating characteristics generated thereby is matched with the write data.

4 is a circuit diagram of a portion of the memory cell shown in FIG.

In the double-gate structure memory cell transistor 12 arranged in three rows by three columns, each gate is connected to a word line 13, a drain is connected to a bit line 14, and a source is grounded. In practice, the control gate 6 itself is a word line 13, and the aluminum wiring 10 is a bit line 14. Then, while the word line 13 is transferred to the row decoder, the bit line 14 is connected to the column decoder so that each is selectively activated. As a result, a specific memory cell transistor 12 is designated in response to the row address and column address.

In the split gate structured memory cell transistor as described above, the side surface of the floating gate 4 is perpendicular to the semiconductor substrate 1, and is formed wider than the thickness of the center portion of the floating gate 4. Since three surfaces of the side surfaces of the floating gate 4 face the control gate 6 through the thin oxide film, the capacitance between the floating gate 4 and the control gate 6 becomes large, and the memory is increased. It causes deterioration of the operating characteristics of the cell transistor. In addition, since the floating gate 4 formed under the thick oxide film 5 is formed by etching using the oxide film formed thickly by selective oxidation, it is difficult to form each part at right angles. For this reason, the effective gate size of the memory cell transistor constituted by the floating gate 4 becomes smaller than the designed value, so that desired operating characteristics cannot be obtained.

In the memory cell transistor, as shown in FIG. 5, the protrusion 15 is formed on the floating gate 4 side at the portion where the control gate 6 is in contact with the silicon substrate 1. This projection 15 is an oxide film 3 which is generated when the floating gate 4 is thermally oxidized to insulate between the floating gate 4 and the control gate 6. This is due to the main part. For this reason, FN conduction tends to occur between the projection 15 of the control gate 6 and the floating gate 4, and when the data is written, the potential of the source region 8 which is common in each column is changed. When raised, charge may be injected into the floating gate 4 even in a memory cell transistor in an unselected state. Therefore, data written in each memory cell is not retained, resulting in a decrease in reliability.

By the way, in the semiconductor memory device, miniaturization of the memory cell transistor is inevitable when the capacity of the semiconductor device is increased. Since a self-aligned gate is adopted in the case of a general MOS transistor, there is little problem in matching between the gate, the source and the drain even in miniaturization. However, the following problem occurs in the case of the transistor having the above-described split gate structure.

The length of the portion where the control gate 6 is in contact with the semiconductor substrate 1, in other words, the distance between the floating gate 4 and the drain region 7 has a high precision of the control gate 6 with respect to the floating gate 4. The position matching precision, that is, the position matching precision of the mask when forming the control gate 6 is maintained. Therefore, as the transistor becomes more miniaturized and the gate length of the transistor becomes shorter, the influence of slight misalignment of the control gate 6 on the floating gate 4 cannot be ignored. For this reason, fluctuations occur in the threshold voltage of the memory cell transistor and the write voltage when the charge is injected into the floating gate 4, which may cause a malfunction. In addition, since it is necessary to connect the aluminum wiring 10 made of the bit lines 14 to the drain region 7 formed between the memory cell transistors adjacent in the bit line direction, the arrangement pitch of the memory cell transistors is reduced. Is an obstacle.

The present invention provides a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate in an electrically independent state, a control gate adjacent to the floating gate and at least partially overlapping the floating gate, and the control gate of the floating gate. A first semiconductor region of reverse conductivity type formed in a substrate region opposite to the side opposite to the second semiconductor region of the reverse conductivity type formed in a substrate region opposite to the side opposite to the floating gate of the control gate. And a center portion thinner than an end portion in a direction in which the thickness of the floating gate crosses the control gate, and is formed almost uniformly in a direction parallel to the control gate.

As a result, the thickness of the floating gate is made thinner at the center portion in the direction intersecting the control gate and made substantially uniform in the direction parallel to the control gate, thereby reducing the area of the side surface of the floating gate. Therefore, the area of the portion where the floating gate faces the control gate through the thin oxide film is reduced, and the capacitance between the floating gate and the control gate is reduced.

In the manufacturing method, a step of forming an oxidation resistant film having an opening extending in a first direction with a predetermined width on the first gate material layer laminated on one conductive semiconductor substrate and the first gate material layer Selectively oxidizing according to the opening of the oxidation resistant film to form a thick oxide film continuous in a first direction, and forming an etching-resistant layer on the thick oxide film having openings extending in a second direction perpendicular to the first direction. And etching the thick oxide film using the etched layer as a mask, separating the thick oxide film in a second direction to form a plurality of island shapes, and forming the first gate material layer under the thick oxide film. Selectively removing by etching and forming an electrically independent floating gate, leaving the portion located in the floating gate; Selectively removing the second gate material layer stacked over the substrate by etching to form a control gate overlapping at least a portion of the floating gate; and forming a reverse gate in the substrate region adjacent to the floating gate and the control gate. And impurity implantation to form a reverse conductive semiconductor region.

As a result, a thick sidewall parallel to the control gate of the floating gate in the first direction is formed in accordance with the oxide film, and a sidewall crossing the control gate of the floating gate extends in the second direction. Formed accordingly. Therefore, the thickness of the floating gate becomes thinner than the end portion in the direction crossing the control gate and becomes almost uniform in the direction parallel to the control gate. Further, after the shape of the floating gate is determined by etching using the inner etching layer as a mask, each portion of the floating gate is formed at right angles. Thus, the effective gate size of the memory cell transistor can be accurately formed.

The present invention also provides a semiconductor substrate of one conductivity type, a floating gate disposed on the semiconductor substrate in an electrically independent state, a control gate adjacent to the floating gate and at least partially overlapping the floating gate, and the control of the floating gate. A reverse conductive first semiconductor region formed in a substrate region opposite to the side opposite to the gate, and a reverse conductive type second semiconductor region formed in a substrate region opposite to the side opposite to the floating gate of the first gate; And a step for lowering the control gate side between the surface region of the semiconductor substrate where the floating gate is disposed and the surface region of the semiconductor substrate where the control gate is disposed.

As a result, a step is formed between the surface where the control gate is in contact with the semiconductor substrate and the surface where the floating gate is in contact with the semiconductor substrate, so that the projections generated on the floating gate side of the control gate are separated from the floating gate, and from the projection of the control gate. FN conduction is less likely to occur between floating gates. Therefore, even if the potential of the source region of a specific memory cell transistor is raised to write data, charges are not injected into the floating gate in the memory cell transistor having the common source region.

In the manufacturing method, a step of forming an oxidation resistant film having an opening corresponding to the position where the floating gate is formed on the first gate material layer laminated on the conductive semiconductor substrate, and the first gate material layer Is selectively oxidized along the opening of the oxidation resistant film to form an island-shaped thick oxide film, and the gate material layer and the gate material layer under the island-shaped thick oxide film Selectively removing a portion by etching to form an electrically independent floating gate, and forming a step that rises at the position where the floating gate is formed on the semiconductor substrate, and exposing the floating gate and the exposed surface of the semiconductor substrate. Oxidizing to form an interlayer insulating film, and a second gate stacked on the interlayer insulating film Selectively removing the material layer by etching and forming a control gate at least partially overlapping the floating gate; and injecting a reverse conductive type impurity into the floating gate and a substrate region adjacent to the control gate. Forming a first and a second semiconductor region.

Accordingly, when the first gate material layer is selectively etched to form the floating gate at the same time, part of the surface of the semiconductor substrate is also etched simultaneously, thereby lowering the surface of the semiconductor substrate at the portion where the control gate is formed. The projections on the side separate from the floating gate. In addition, when an exposed surface of the floating gate is oxidized to form an interlayer insulating film, recesses are less likely to occur in the oxide film between the semiconductor substrate and the floating gate, so that large protrusions do not occur in the control gate formed along the interlayer insulating film. This makes it difficult to concentrate the electric field on the floating gate side of the control gate.

The present invention also provides a semiconductor substrate of one conductivity type, a floating gate disposed on the semiconductor substrate, a first control gate disposed on the semiconductor substrate at a predetermined distance from the floating gate, the floating gate and the A second control gate disposed between the first control gate and overlapping at least a part of the floating gate, and a reverse conductive type formed in a substrate region on the side opposite to the side of the floating gate opposite to the first control gate; And a first semiconductor region and a second semiconductor region of reverse conductivity type formed in the substrate region on the side opposite to the side opposite to the floating gate of the first control gate.

Also, a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate, a first control gate disposed on the semiconductor substrate at a predetermined distance from the floating gate, the floating gate and the first control gate A control gate disposed between the first control gate and overlapping at least a part of the floating gate, and formed in a substrate region on the opposite side of the floating gate, the side opposite to the first control gate; And a reverse conductive second semiconductor region formed in the substrate region on the side opposite to the side opposite to the floating gate of the first control gate.

Thereby, since the floating gate and the 1st control gate can be formed simultaneously by a single mask, a relative position does not shift | deviate from each other. The second control gate is formed between the floating gate and the first control gate, so that the length of the second control gate in contact with the semiconductor substrate, that is, the gate length of the memory cell transistor is affected by the position shift of the second control gate. It is kept at a predetermined length without closing. Therefore, the positions of the floating gates do not shift with respect to the drain and the source formed by using these gates as self-alignment gates, so that each memory cell transistor obtains desired characteristics.

The present invention also provides a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate, a first semiconductor region of reverse conductivity type formed in the substrate region at a predetermined distance from the floating gate, and the first semiconductor region. A first control gate disposed on the semiconductor substrate, the second control gate overlapping a portion of the floating gate between the floating gate and the first control gate, and the first control gate disposed on the semiconductor substrate. A second semiconductor region of a reverse conductivity type formed in the substrate region opposite to the side opposite to the floating gate and continuous to the first semiconductor region, and on the side opposite to the side facing the first control gate of the floating gate. A third semiconductor region of reverse conductivity type formed in the substrate region is provided.

Accordingly, since the first semiconductor region formed in the substrate region under the first control gate is connected to the second semiconductor region and acts as a drain, the substantial gate length of the second control gate is determined by the floating gate and the first control gate. It depends on the distance between. Therefore, the gate length of the memory cell transistor becomes constant regardless of the relative positional relationship between the second gate and the floating gate.

In the manufacturing method, a step of forming an oxidation resistant film having an opening paired with a predetermined distance on the first gate material layer laminated on one conductive semiconductor substrate and one of the openings of the oxidation resistant film Punching through the first gate material layer from the substrate to implant impurity ions of reverse conductivity into the semiconductor substrate to form a first semiconductor region of reverse conductivity in a surface region of the semiconductor substrate; Selectively oxidizing the first gate material layer according to each opening of the oxidation resistant film, selectively etching away the first gate material layer, and forming a first control gate corresponding to one of the openings of the oxidation resistant film, Forming a floating gate corresponding to the side, and a second gay stacked on the semiconductor substrate to cover the first control gate and the floating gate; Selectively etching away the etch material layer and forming a second control gate between the first control gate and the floating gate, and a substrate on the side opposite to the side of the first control gate facing the floating gate. Implanting impurity ions of a reverse conductivity type into the region using the first control gate as a mask to form a second semiconductor region of a reverse conductivity type continuous to the first semiconductor region, and to the first control gate of the floating gate And a step of forming a third semiconductor region of a reverse conductivity type by implanting impurity ions of a reverse conductivity type into the substrate region on the opposite side to the opposite side as a mask.

Accordingly, by forming the first semiconductor region and the first control gate by the same mask, the position of the first control gate with respect to the position of the first semiconductor region coincides. By simultaneously forming the floating gate and the first control gate in the same process, the distance between the floating gate and the first control gate is maintained at a predetermined value. Accordingly, the length of the second control gate formed between the floating gate and the first control gate in contact with the semiconductor substrate, that is, the substantial gate length of the memory cell transistor is not affected by the positional shift of the second control gate relative to the floating gate. do.

In addition, the present invention provides a semiconductor substrate of one conductivity type, a plurality of floating gates arranged in a matrix on the semiconductor substrate, and are formed in the surface region of the semiconductor substrate at a predetermined distance from the floating gate and are continuous in the column direction of the floating gate. A plurality of reverse conductive first semiconductor regions, a simulated gate overlapping the first semiconductor region and disposed in parallel with the floating gate on the semiconductor substrate, and disposed on the floating gate and the simulated gate and floating A plurality of control gates continuous in the row direction of the gate and a reverse conductive type formed in the surface region of the semiconductor substrate on the side opposite to the side opposite to the simulated gate of the floating gate and continuous in the column direction of the floating gate; It is characterized by including two semiconductor regions.

As a result, since the first semiconductor region formed in the substrate region below the simulation gate acts as a drain, the substantial gate length of the control gate is determined according to the distance between the floating gate and the simulation gate. Therefore, the position shift of the control gate with respect to the floating gate is less likely to be affected by the threshold voltage of the memory cell transistor, so that the gate length can be shortened. In addition, since the bit lines do not need to be connected to each drain region of each memory cell transistor, the drain pitch can be reduced to reduce the arrangement pitch of the memory cell transistors.

In the manufacturing method, a step of forming an oxidation resistant film having a plurality of openings arranged in pairs at a predetermined distance and arranged in a matrix on a first gate material layer stacked on a conductive semiconductor substrate; And punching through the first gate material layer from one side of each opening of the oxidation resistant film to inject impurity ions of reverse conductivity into a surface region of the semiconductor substrate to form a first semiconductor region of reverse conductivity. Selectively oxidizing the one-gate material layer in accordance with the opening of the oxidation resistant film, selectively etching away the first gate material layer, and forming a simulated gate corresponding to one of each opening of the oxidation resistant film. Forming a floating gate corresponding to the side of the semiconductor substrate; and the semiconductor substrate on the side opposite to the side of the floating gate that is opposite to the simulated gate. Implanting impurity ions of a reverse conductivity type into the surface region as a mask, and forming a second semiconductor region continuous in the column direction; and a surface region of the semiconductor substrate between the simulation gates adjacent in the column direction. Forming a third semiconductor region for implanting impurity ions of a reverse conductivity type and connecting the first semiconductor region in a column direction; and a second gate material layer covering the simulation gate and floating gate and stacked on the semiconductor substrate. And selectively removing the etching and forming a control gate continuous in the row direction on the first control gate and the floating gate.

Accordingly, the first semiconductor region and the simulated gate are formed by the same mask, whereby the position of the simulated gate with respect to the position of the first semiconductor region coincides. Then, by forming the simulation gate and the floating gate in the same process, the distance between the simulation gate and the floating gate is maintained at a predetermined value. Therefore, the length of the control gate in contact with the semiconductor substrate between the simulation gate and the floating gate, that is, the substantial gate length of the memory cell transistor, is not affected by the positional shift of the control gate relative to the floating gate.

Example 1

6 is a perspective view of a memory cell portion of the nonvolatile semiconductor memory device of the present invention, and FIGS. 7 and 8 are cross-sectional views of X-X lines and Y-Y lines.

In the surface region on the P-type silicon substrate 21, a plurality of separation regions 22 made of an oxide film thickly formed by selective oxidation are arranged to partition the element region. The separation region 22 may be a high concentration P-type region. A plurality of floating gates 24 are disposed between the adjacent isolation regions 22 through the oxide film 23 on the silicon substrate 21 on which the isolation regions 22 are formed. The oxide film 25 covering the floating gate 24 is formed thick at the center portion of the floating gate 24, and the end of the floating gate 24 is acute to facilitate electric field concentration. However, the floating gate 24 has a side surface 24a intersecting with the separation region 22 having a wider and more uniform width than the substantial thickness of the floating gate 24 and having a side surface 24b parallel to the separation region 22. It is formed to narrow in the center. That is, the floating gate 24 is formed to have a substantially uniform thickness in the thin and parallel direction at the center portion in the direction crossing with the control gate 26 to be described later, and the side surface parallel to the control gate 26 ( It is difficult to generate electric field concentration outside the end of 24a). The control gate 26 is disposed on the silicon substrate 21 on which the floating gate 24 is disposed in a direction crossing the separation region 22 in correspondence with each floating gate 24. The control gate 26 is continuous in the direction intersecting with the isolation region 22, a part of which is superimposed on the floating gate 24 through the oxide film 25, and the other part of the control gate 26 is interposed through the oxide film 23. 21). These floating gates 24 and control gates 26 are arranged such that each column is linearly symmetrical. N-type drain regions 27 and source regions 28 are formed in the substrate region between adjacent control gates 26 and the substrate region between floating gates 24. The drain region 27 is surrounded by the isolation region 22 between the control gates 26 and each is independent, and the source region 28 is continuous in the direction in which the control gate 25 extends.

As described above, the oxide film 29 is formed on the silicon substrate 21 on which the floating gate 24 and the control gate 26 are disposed to cover the floating gate 24 and the control gate 26. The aluminum wiring 30 connected with the drain region 28 is arrange | positioned at this. In addition, the oxide film 29 and the aluminum wiring 30 are abbreviate | omitted in FIG.

The operations of writing, erasing and reading data in this memory device are performed as follows, for example. First, in the write operation, the potential of the control gate 26 is 2V, the potential of the drain region 27 is 0.8V, and the potential of the source region 28 is 12V. As a result, hot electrons generated in the vicinity of the drain region 27 are accelerated toward the floating gate 24 and injected into the floating gate 24 through the oxide film 23 to write data. On the other hand, the potential of the drain region 27 and the source region 28 in the erase operation is set to 0V, and the control gate 26 is set to 14V. As a result, the charge retained in the floating gate 24 is punched through the oxide film 23 by FN conduction from the acute angle portion at the end of the floating gate 24 and discharged to the control gate 26 to erase data. Further, in erasing data, batch erasing is possible by supplying a constant voltage to all the memory cell transistors. In the read operation, the potential of the control gate 26 is 4V, the drain region 27 is 2V, and the source region 28 is 0V. At this time, when charge is injected into the floating gate 23, since the potential of the floating gate 23 is lowered, no channel is formed under the floating gate 23, and no drain current flows. On the contrary, if no charge is injected into the floating gate 23, the potential of the floating gate 23 becomes high, so that a channel is formed under the floating gate 23 and a drain current flows. Thus, by detecting the current flowing out of the drain region 27 by means of a sense amplifier, determination of on / off of the memory cell transistor, that is, determination of recorded data is made.

In the above-described memory device, the area of the side surface 24b of the floating gate 24 intersecting with the control gate 26 becomes small, and the area of the portion facing the control gate 26 becomes small, so that the floating gate 24 And the capacitance between and the control gate 76 become small.

9 to 14 are cross-sectional views illustrating processes for manufacturing the nonvolatile semiconductor memory device of the present invention. In each figure, the right side corresponds to the cross section of the X-X line of FIG. 1, and the left side corresponds to the cross section of the Y-Y line of FIG.

[Step 1: FIG. 9]

First, the isolation region 22 made of a thick oxide film is formed by selectively oxidizing the surface of the P-type silicon substrate 21. Regarding the selective oxidation method, description thereof will be omitted by a well-known method. Then, the polycrystalline silicon layer 31 is laminated on the silicon substrate 21 via the oxide film 23, and the oxide film 32 is formed on the surface of the polycrystalline silicon layer 31. Further, a nitride film 33 serving as an oxidation mask is formed on the oxide film 32, and the nitride film 33 is patterned by a well-known photolithography technique to correspond to the position at which the floating gate 24 is formed later. 34). The opening 34 extends in a direction crossing the separation region 22 with a constant width.

Second Process: FIG. 10

The oxide film 32 is selectively oxidized using the nitride film 33 as an oxidation mask, and a thick oxide film 35 is formed in the opening 34 portion of the nitride film 33 in a direction crossing the separation region 22. do. In the oxide film 35, the oxide film 32 is grown on the surface side and the polycrystalline silicon layer 31 side, and the polycrystalline silicon layer 31 becomes thinner at that portion.

[Step 3: FIG. 11]

After the nitride film 33 is removed, a resist layer 36 serving as an etching mask is laminated on the oxide films 32 and 35, and parallel to the isolation region 22 on the isolation region 22 of the resist layer 36. The opening 37 extending in the direction is formed. The oxide film 35 is etched along the opening 37 to separate the oxide film 35 on the separation region 22 to form an island shape between the adjacent separation regions 22. In this manner, when the resist layer 36 is etched as a mask, each portion of the oxide film 35 formed in an island shape is formed in a desired shape, that is, at a right angle. In addition, the polycrystalline silicon layer 31 under the oxide film 35 is formed to have a thin center in the direction parallel to the isolation region 22, and to have a uniform thickness in the crossing direction.

[4th Step: FIG. 12]

After removing the resist layer 36, the polycrystalline silicon layer 31 is etched leaving the lower portion of the thick oxide film 35 to form the floating gate 24. At this time, since each part of the oxide film 35 forms a right angle, each part also forms a right angle with respect to the floating gate 24 which becomes a shape matched with the oxide film 35. In addition, the thickness of the floating gate 24 is formed to be thin in the center portion in the direction parallel to the isolation region 22 in the same manner as the polycrystalline silicon layer 31 under the oxide film 35 and uniformly formed in the crossing direction.

[Step 5: FIG. 13]

After thermally oxidizing the exposed surface of the floating gate 24 to form an interlayer insulating film, a polycrystalline silicon layer 38 is laminated to cover the floating gate 24, and the polycrystalline silicon layer 38 is patterned to control the gate 26. ). When the control gate 26 is formed, the oxide film 23 on the silicon substrate 21 is once removed, and then the oxide film is formed again, whereby a good gate insulating film can be obtained.

[Step 6: Fig. 14]

Using the floating gate 24 and the control gate 26 as a mask, an N-type impurity ion, for example, phosphorus ion P, is applied to the substrate region between the floating gate 24 and the substrate region between the control gate 25. The drain region 27 and the source region 28 are formed. However, the source region 28 needs to be enlarged to the region below the floating gate 24 in order to be capacitively coupled to the floating gate 24 to control the potential of the floating gate 24. Therefore, the formation of the drain region 27 and the formation of the source region 28 are performed in separate processes, and the implantation energy of phosphorus ions is increased at the time of forming the source region 28 so that the N-type impurity ions can be easily diffused. Alternatively, impurity ions are implanted twice into the source region 28 so that the impurity concentration of the source region 28 is higher than that of the drain region 27.

In a subsequent step, the surface of the control gate 26 and the exposed surface of the oxide film 23 are thermally oxidized to form a new oxide film 29, and a contact hole is formed in the drain region 27, and then the drain region ( The aluminum wiring 30 exclusively transmitted to 27 is formed.

By the way, in the formation of the floating gate 24, the polycrystalline silicon layer 31 is separated in the direction parallel to the separation region 22 in the third process, and then etched according to the thick oxide film 35 in the fourth process. The fourth step may be performed before the third step. In other words, the polycrystalline silicon film 31 is etched according to the thick oxide film 35 to leave a strip in the direction crossing the isolation region, and the etched layer formed after the polycrystalline silicon film 31 as a resist layer is masked. A plurality of floating gates 24 are formed by separating on the separation region 22 by etching.

In the first embodiment described above, the case of the N-channel type in which the N-type drain region 27 and the source region 28 are formed in the P-type silicon substrate 21 is illustrated. It may be.

According to the first embodiment, by decreasing the area of the floating gate side surface that intersects the control gate, the area facing the control gate is reduced, so that the capacitance generated between the floating gate and the control gate is reduced. For this reason, the deterioration of the operating characteristics of the memory cell transistor due to the increase in the parasitic capacitance can be prevented.

Further, in the manufacturing method of the first embodiment, since each portion of the floating gate is perpendicular to each other, it is possible to reduce the manufacturing error of the gate size of the memory cell transistor and to form a memory cell transistor having desired operating characteristics according to the design value. . Therefore, even when the size of the memory cell transistor is reduced, desired operating characteristics can be obtained, which is advantageous in miniaturizing the memory cell, that is, increasing the memory capacity.

Example 2

FIG. 15 is a sectional view of a memory cell portion of the nonvolatile semiconductor memory device of the present invention, and FIG. 16 is an enlarged sectional view showing a main portion of a memory cell transceiver.

A plurality of floating gates 43 are independently disposed on the P-type silicon substrate 41 via the oxide film 42. The floating gate 43 is arranged so as to span between the plurality of separation regions of a single step that divides the element region on the surface of the silicon substrate 41. In addition, the oxide film 44 covering the floating gate 43 is formed thick at the center of the floating gate 43, and an end portion of the floating gate 43 is formed at an acute angle. The control gate 45 is disposed corresponding to each floating gate 43 on the silicon substrate 41 on which the floating gate 43 is disposed. The control gate 45 is disposed so that a part thereof overlaps the floating gate 43 through the oxide film 44, and the remaining part contacts the silicon substrate 41 through the oxide film 42. In addition, a step is provided on the surface of the silicon substrate 41 between a portion where the control gate 45 is in contact with a portion where the floating gate 73 is in contact, and a bottom surface of the control gate 45 is at the bottom of the floating gate 43. It is designed to be lower than cotton. These floating gates 43 and control gates 45 are arranged such that each row is linearly symmetrical. N-type drain region 46 and source region 47 are formed in the substrate region between adjacent control gates 45 and the substrate region between floating gate 43. The drain region 47 is surrounded by an isolation region between the control gates 45 and is independent of each other, and the source region 47 is continuous in the direction in which the control gate 45 extends. The position itself in which the floating gate 43, the control gate 45, the drain region 46, and the source region 47 are disposed is the same as that of the conventional memory device, and coincides with the plan view shown in FIG. Then, the aluminum wiring 49 is disposed on the control gate 45 in the direction crossing the control gate 45 through the oxide film 48, and the aluminum wiring 49 is drain region through the contact hole 50, respectively. It is connected to 46.

The larger the step height provided on the surface of the silicon substrate 41, the higher the effect can be expected. However, in consideration of step coverage, about 2 to 3 times higher than the step height 15 generated in the conventional memory cell transistor (FIG. 5). desirable. For example, a step of about 500 mW is provided while the step 15 of the conventional memory cell transistor is about 180 mW.

The operations of writing, erasing, and reading data in the above memory device correspond to those of the first embodiment shown in FIG. In the write operation, in the memory cell transistor in which the source region 47 is commonly in an unselected state, the potential of the floating gate 43 rises due to the capacitive coupling of the floating gate 43 and the source region 47, but the floating Due to the step provided between the bottom surface of the gate 43 and the bottom surface of the control gate 45, the injection of charge due to FN conduction from the control gate 45 to the floating gate 43 does not occur. That is, as a step is provided between the bottom surface of the floating gate 43 and the bottom surface of the control gate 45, projections generated on the floating gate 43 side of the control gate 45 as shown in FIG. 16. By falling away from the floating gate 43, FN conduction does not occur easily.

17 to 22 are cross-sectional views illustrating processes for manufacturing the nonvolatile semiconductor memory device of the present invention.

[Step 1: Figure 17]

The polycrystalline silicon layer 52 is laminated on the P-type silicon substrate 41 via the oxide film 51, and the oxide film 53 is formed on the surface of the polycrystalline silicon layer 52. In addition, an nitride film 54 serving as an oxidation mask is formed on the oxide film 53, and the nitride film 54 is patterned by a known photolithography technique to later form the openings corresponding to the positions at which the floating gate 43 is formed. 55).

[Step 2: FIG. 18]

The oxide film 53 is selectively oxidized using the nitride film 54 as an oxidation mask, and a thick oxide film 56 is formed in the opening 55 of the nitride film 54. In this thick oxide film 56, the oxide film 53 grows to the surface side and the polycrystalline silicon layer 52 side, and the polycrystalline silicon layer 52 becomes thinner at that portion.

[3rd process: FIG. 19]

After the nitride film 53 is removed, the polycrystalline silicon layer 52 and the oxide film 51 are etched leaving the thick oxide film 56 underneath to form the floating gate 43. At this time, a step is formed on the surface of the silicon substrate 41 by overetching to the surface of the silicon substrate 41.

[4th Step: FIG. 20]

The surface of the exposed silicon substrate 41 and the side surface of the floating gate 43 are thermally oxidized to form an oxide film 42 serving as the gate insulating film of the control gate 45 and an oxide film 57 serving as the interlayer insulating film. In this thermal oxidation, the oxide film 56 left on the floating gate 43 grows and becomes an oxide film 44 which insulates between the floating gate 43 and the control gate 45.

[Step 5: FIG. 21]

The polycrystalline silicon layer 58 is laminated so as to cover the floating gate 43, and the polycrystalline silicon layer 58 is patterned to form the control gate 45. The control gate 45 formed in this way has a surface in contact with the silicon substrate 41 lower than the floating gate 43, and the projections generated on the floating gate 43 side have the conventional control gate shown in FIG. It becomes small compared with the protrusion 15 which arises in (6).

[Step 6: Fig. 22]

Using the floating gate 43 and the control gate 45 as a mask, an N-type impurity ion, for example, phosphorus ion P, is applied to the substrate region between the floating gate 43 and the substrate region between the control gate 45. And a drain region 46 and a source region 47 are formed. By the way, the source region 47 needs to diffuse to the region below the floating gate 43 because it is coupled with the floating gate 43 so that the potential of the floating gate 43 can be controlled. Therefore, the formation of the drain region 46 and the formation of the source region 47 are performed in separate steps, and the implantation energy of phosphorus ions is increased at the time of forming the source region 47 so that the N-type impurity ions can be easily diffused. Alternatively, the source region 47 is formed by two injections so that the impurity concentration of the source region 47 is higher than the drain region 48.

In a subsequent step, the surface of the control gate 45 and the exposed surface of the oxide film 42 are thermally oxidized to form a new oxide film 48, and the contact hole 50 is formed in the drain region 46 portion. The aluminum wiring 49 connected to the drain region 46 is formed. Thus, as shown in FIG. 15, a memory cell transistor in which the bottom surface of the control gate 45 is lowered relative to the bottom surface of the floating gate 43 is formed.

In Example 2 described above, the N-channel type in which the N-type drain region 46 and the source region 47 are formed in the P-type silicon substrate 41 is illustrated. It may be.

According to the second embodiment, the distance between the control gate and the floating gate is separated by the step provided between the bottom surface of the control gate of the memory cell transistor and the bottom surface of the floating gate so that FN conduction from the control gate to the floating gate occurs. Becomes difficult. As a result, when data is written to a specific memory cell, charges can be prevented from being injected into the floating gate in a memory cell transistor having a common source region, so that data written once is not inverted arbitrarily. Reliability can be improved.

Moreover, in the manufacturing method of Example 2, when forming the interlayer insulation film between the floating gate and the control gate, recesses are hardly formed in the side thin film of the floating gate. Becomes smaller. Therefore, electric field concentration hardly occurs in the protruding portion of the control gate, and in addition to separating the distance between the protruding portion of the control gate and the floating gate, the effect of preventing FN conduction from the control gate to the floating gate is large.

In addition, by providing a step between the floating gate and the control gate, charge is accelerated at the stepped portion and injected into the floating gate, thereby improving data writing efficiency.

Example 3

FIG. 23 is a plan view of a memory cell portion of the apparatus of the nonvolatile semiconductor memory of the present invention, and FIG. 24 is an X-ray cross-sectional view thereof.

In the surface region of the P-type semiconductor substrate 60, a plurality of isolation regions 61 made of LOCOS are formed, and the element region is partitioned. A plurality of floating gates 63 are independently disposed on the semiconductor substrate 60 so as to span between adjacent isolation regions 61 through the oxide film 62. In addition, a plurality of first control gates 64 are arranged at a predetermined distance from each floating gate 63. The first control gate 64 is continuous in each column and extends in the direction crossing the separation region 61. A second control gate 65 parallel to each first control gate 64 is disposed between each floating gate 63 and the first control gate 64. Both ends of the second control gate 65 overlap the floating gate 63 and the first control gate 64, and the remaining portion of the second control gate 65 is disposed between the floating gate 63 and the first control electrode 64. ) To be in contact with the semiconductor substrate 60. Further, these floating gates 64, the first control gate 64 and the second control gate 65 are arranged so that adjacent columns are mutually symmetric with each other. An N-type drain region 66 and a source region 67 are formed in the substrate region between the first control gate 64 and the substrate region between the floating gate 63, respectively. The drain region 66 is surrounded by the isolation region 61 between the first control gates 64 and is independent of each other, and the source region 67 extends between the first control gate 64 and the second control gate 65. Continuous in the direction. Therefore, the memory cell transistor is configured by the floating gate 63, the first and second control gates 64 and 65, the drain region 66, and the source region 67.

The aluminum wiring 67 is disposed on the second control gate 65 in the direction crossing the first control gate 64 and the second control gate 65 through the oxide film 68. The aluminum wirings 69 are connected to the drain regions 66 through the contact holes 70, respectively.

Each operation of writing, erasing, and reading data in the semiconductor memory device is performed as follows, for example. In the write operation, the potential of the first control gate 64 is 5V, the potential of the second control gate 65 is 2V, the drain region 66 is 0.5V, and the source region 67 is 12V. As a result, hot electrons generated in the vicinity of the drain region 66 are accelerated toward the floating gate 53 and injected into the floating gate 63 through the oxide film 62 to write data. In contrast, in the erasing operation, the potentials of the drain region 66 and the source region 67 are set to OV, the first control gate 64 is set at 5V, and the second control gate 65 is set at 14V. As a result, charges held in the floating gate 63 are punched through the oxide film 62 by FN tunneling from an acute angle portion at the end of the floating gate 63 to be discharged to the second control gate 65 to erase data. . Further, in erasing data, batch erasing is possible by supplying a constant voltage to all the memory cell transistors. In the read operation, the potential of the first control gate 64 is 5V, the potential of the second control gate 65 is 4V, the drain region 66 is 2V, and the source region 67 is OV. When charge is injected into the floating gate 53, the potential of the floating gate 63 is lowered, and no channel is formed under the floating gate 63, so that current flows from the drain region 66 to the source region 67. Do not. On the contrary, when no charge is injected into the floating gate 63, the potential of the floating gate 63 becomes high, and a channel is formed below the floating gate 63 so that current flows from the drain region 66 to the source region 67. Thus, by detecting the current flowing out of the drain region 66 by the sense amplifier, determination of on / off of the memory cell transistor, that is, determination of written data is made. Here, although the first control gate 64 is set at 5 V under each operating condition, the same operation can be performed even when driven by the same potential as the second control gate 65.

In the semiconductor memory device as described above, the distance from the floating gate 63 to the drain region 66 is determined according to the distance between the floating gate 63 and the first control gate 64 and the length of the first control gate 64. do. Therefore, even if the position shift of the second control gate 65 with respect to the floating gate 63 occurs, the threshold voltage of the memory cell transistor and the write voltage required for injecting hot electrons into the floating gate 63 do not change.

25 to 29 are cross-sectional views illustrating processes for manufacturing a nonvolatile semiconductor memory device of the present invention.

[Step 1: FIG. 25]

The polycrystalline silicon layer 71 is laminated on the P-type semiconductor substrate 60 via the oxide film 62, and an oxide film 72 is formed on the surface of the polycrystalline silicon layer 71. Further, a nitride film 73 serving as an oxidation mask is formed on the oxide film 72, and after opening the patterned oxide film 73, an opening is formed in a portion serving as a gate electrode.

Second Process: FIG. 26

The oxide film 72 is selectively oxidized using the nitride film 73 as an oxidation mask. According to this oxidation, the oxide film 72 grows on the white side and the polycrystalline silicon layer 71 side at the opening of the nitride film 73 to form a thick oxide film 74. As a result, the film thickness of the polycrystalline silicon layer 71 is partially thinned.

[3rd process: FIG. 27]

The floating gate 63 and the first control gate 64 are formed by removing the nitride film 73 and leaving the polycrystalline silicon layer 71 under the thick oxide film 74 remaining.

[Step 4: Figure 28]

The polycrystalline silicon layer 75 is stacked to cover the floating gate 63 and the oxide film 74 on the first control gate 64, and the polycrystalline silicon layer 75 is patterned to form the second control gate 55. . As for the floating gate 63 and the 1st control gate 64 formed in this way, the edge part of the upper surface side has V shape.

[Step 5: FIG. 29]

N-type impurity ions in the substrate region between the floating gate 63 and the substrate region between the first control gate 64, for example, using the floating gate 63 and the first and second control gates 64 and 65 as masks. For example, phosphorus ions P are implanted to form the drain region 66 and the source region 67. By the way, the source region 67 needs to be extended to the region under the floating gate 63 so that the potential of the floating gate 63 can be controlled in combination with the floating gate 63. Therefore, the formation of the drain region 66 and the formation of the source region 67 are performed in separate processes to increase the implantation energy of phosphorus ions when forming the source region 67 so that the N-type impurity ions are easily expanded.

In a subsequent step, the surface of the second control gate 65 and the exposed surface of the oxide film 62 are reversed to form a new oxide film 68, and a contact hole 70 is formed in the drain region 66 portion. After that, the aluminum wiring 69 is formed.

30 is a cross-sectional view showing another configuration of the invention, showing the same portion as in FIG.

The floating gate 63, the drain region 66, and the source region 67 have the same shape as FIG. 24. That is, the floating gate 63 and the first control gate 64 are disposed on the semiconductor substrate 60 at regular intervals so that the drain region 66 is provided between the first control gate 64 and the floating gate ( A source region 67 is formed between the 63. Here, the characteristic feature is that the second control gate 65 is disposed between the floating gate 63 and the first gate 64 so as to be connected to the first control gate 64, and the composite control gate 80 is disposed. It is in the form. The composite control gate 80, in which the first control gate 64 and the second control gate 65 are electrically connected to each other, operates as a single control gate. It becomes the same as the conventional semiconductor memory device shown in FIG.

For such a composite control gate 80, the length of contact with the semiconductor substrate 60 is determined by the length of the first control gate 64 and the distance between the floating gate 63 and the first control gate 64. Therefore, when the floating gate 63 and the first control gate 64 are formed in the same process, and the drain region 66 and the source region 67 are formed using these as self-alignment gates, the second control gate 65 is formed. The position shift of does not affect the operating characteristics of the memory cell transistor.

Steps for connecting the first control gate 64 and the second control gate 65 to the manufacturing method described with reference to FIGS. 25 to 29 for the manufacturing method of the semiconductor memory device having the composite control gate 80. Good to add Specifically, the following steps shown in FIGS. 31 and 32 are added after the third step of forming the floating gate 63 and the first control gate 64.

[First Process: Fig. 31]

The resist layer 81 is formed to cover the floating gate 63, the first control gate 54, and the oxide film 62, and the back gate 63 and the first control are etched back by etching the resist layer 81. The surface of the oxide film 74 on the gate 64 is exposed. As a result, the resist layer 82 is formed only in the gap portions of the floating gate 63 and the first control gate 64.

Second Process: FIG. 32

A new resist layer 73 is formed, and an opening 84 is formed at a position where contact between the first control gate 64 and the second control gate 65 should be made. Thus, the resist layer 83 is used as a mask for etching, and a part of the oxide film 74 covering the first control gate 64 is removed. At this time, even if part of the first control gate 64 is removed at the same time, the second control electrode 65 is supplemented by the second control electrode 65. In addition, since the resist layer 82 formed in the previous step is provided at the bottom of the opening 84, the oxide film 62 on the surface of the silicon substrate 60 made of the gate insulating film does not deteriorate.

After the resist layers 82 and 83 are removed, the second control gate is formed in connection with the fourth process shown in FIG. As a result, the second control gate 65 is electrically connected to the first control gate 64 to form the composite control gate 80 as shown in FIG.

In Example 3 described above, the case of the N-channel type in which the N-type drain region 66 and the source region 67 are formed in the P-type semiconductor substrate 60 is illustrated. However, the P-channel type using the N-type semiconductor substrate is illustrated. It is also possible to configure.

According to the third embodiment, since there is no variation in the threshold voltage due to the positional shift of the control gate of the memory cell transistor, the memory cell transistor can be miniaturized. In particular, it is effective when the gate size of the memory cell transistor is 1 占 퐉 or less, and the capacity of the memory cell can be increased.

Example 4

33 is a plan view of a portion of a memory cell of the nonvolatile semiconductor memory device of Example 4, and FIG. 34 is an X-ray cross-sectional view thereof.

A plurality of isolation regions 91 made of LOCOS are formed in the surface region of the P-type semiconductor substrate 90 to partition the element region. A plurality of floating gates 92 are disposed independently on the semiconductor substrate 90 so as to span the adjacent isolation regions 91 through the oxide film 92. An N-type auxiliary drain region 94 is formed in the substrate region spaced apart from each floating gate 93 with the isolation region 91 therebetween. In addition, a plurality of first control gates 95 are disposed on the semiconductor substrate 90 through the oxide film 92 so as to coincide with the auxiliary drain region 94. The first control gate 95 is continuous in each column and extends in the direction crossing the separation region 91. A second control gate 76 parallel to the first control gate 95 is disposed between each floating gate 93 and the first control gate 95. Both ends of the second control gate 96 overlap the floating gate 93 and the first control gate 95, and the remaining portions of the second control gate 96 are disposed between the floating gate 93 and the first control gate 95. ) To be in contact with the semiconductor substrate 90. In addition, these floating gates 93, the auxiliary drain region 94, the first control gate 95, and the second control gate 96 are arranged so that neighboring columns are linearly symmetric with each other. N-type drain regions 97 and source regions 98 are formed in the substrate region between the first control gate 95 and the substrate region between the floating gate 93, respectively. The drain region 97 is continuous to the auxiliary drain region 94 and is surrounded by the isolation region 91 between the first control gates 95 so as to be independent of each other. The source region 98 is not partitioned by the isolation region 91 in the column direction, but continues in the direction in which the first control gate 95 and the second control gate 96 extend. These floating gates 93, first and second control gates 95 and 96, auxiliary drain region 94, drain region 97 and source region 98 constitute a memory cell transistor.

The aluminum wiring 100 is disposed on the second control gate 96 in the direction crossing the first control gate 95 and the second control gate 96 through the oxide film 99. The aluminum wirings 100 are connected to the drain regions 97 through the contact holes 101, respectively.

Each operation of writing, erasing and reading data in this semiconductor memory device is the same as that of the memory device of the third embodiment shown in FIG. In each operation, the first control gate 95 is set to the same potential or floating state as the second control gate 96.

In the semiconductor memory device described above, since the auxiliary drain region 94 operates in the same manner as the drain zero wing 94, the substantial distance from the floating gate 93 to the drain region 97 is determined by the floating gate 93. Only the distance between one control gate 94 is determined. Therefore, even if the position shift of the second control gate 96 with respect to the floating gate 93 occurs, there is no change in the gate length of the memory cell transistor, and writing is performed when a threshold voltage or hot electrons are injected into the floating gate 93. Voltage fluctuations do not occur.

35 to 41 are cross-sectional views illustrating processes for manufacturing the nonvolatile semiconductor memory device of the present invention.

[Step 1: FIG. 35]

The polycrystalline silicon layer 111 is laminated on the P-type semiconductor substrate 90 through the oxide film 92, and the oxide film 112 and the nitride film 113 are formed on the surface of the polycrystalline silicon layer 111. And as shown in FIG. 3, the resist pattern 114 which has an opening in the position which forms the floating gate 93 and the 1st control gate 95 is formed, and this resist pattern 114 is masked. The nitride film 113 is removed by etching.

Second Process: FIG. 36

A new resist pattern 115 is formed to cover the opening corresponding to the position where the floating gate 93 is formed, and the N-type impurity is formed using the resist pattern 115 and the resist pattern 114 formed in the first process as a mask. Ions, for example, phosphorus ions P are implanted. As a result, an N-type injection region 116 is formed on the surface of the semiconductor substrate 90 corresponding to the formation position of the first control gate 95.

[3rd process: FIG. 37]

After the resist patterns 114 and 115 are removed, a resist pattern 117 is formed to cover the portion where the N-type implanted region 116 is formed. The resist pattern 117 and the nitride film 113 are used as a mask, and the P-type is formed. Impurity ions, for example, boron ions (B) are implanted. As a result, the impurity concentration on the surface of the semiconductor substrate 90 corresponding to the position where the floating gate 93 is formed is controlled so that the memory cell transistor exhibits predetermined operating characteristics.

Fourth Step: FIG. 38

The diffusion film 112 is selectively oxidized using the nitride film 113 as an oxidation mask. According to this oxidation, the oxide film 112 grows to the surface side and the polycrystalline silicon layer 111 side in the opening portion of the nitride film 113 to form a thick oxide film 118, thereby forming a film of the polycrystalline silicon layer 111. The thickness is partially thinned. In addition, by the heat treatment at this time, the N-type injection region 116 is diffused to form the auxiliary drain region 94.

[Step 5: Fig. 39]

The floating gate 93 and the first control gate 95 are formed by removing the nitride film 113 and leaving the polycrystalline silicon layer 111 under the thick oxide film 118 remaining. As for the floating gate 93 and the 1st control gate 95 formed in this way, the edge part of an upper surface side has V shape.

[Step 6: Fig. 40]

The polysilicon layer 119 is stacked to cover the floating gate 93 and the oxide film 118 on the first control gate 75, and the polysilicon layer 119 is patterned to form the second control gate 96. Form.

[Step 7: Fig. 41]

Example of N-type impurity ions in the substrate region between the floating gate 93 and the substrate region between the first control gate 95 using the floating gate 93 and the first and second control gates 95 and 96 as a mask. For example, phosphorus ions P are implanted to form the drain region 97 and the source region 98. By the way, the source region 98 needs to be extended to the region under the floating gate 93 so that the potential of the floating gate 93 can be controlled in combination with the floating gate 93. Therefore, the formation of the drain region 96 and the formation of the source region 98 are performed in separate processes to increase the implantation energy of phosphorus ions when forming the source region 98 so that the N-type region is easily expanded.

In a subsequent step, the surface of the second control gate 96 and the exposed surface of the oxide film 92 are thermally oxidized to form a new oxide film 99, and the contact hole 101 is formed in the drain region 97. After that, the aluminum wiring 100 is formed.

According to the above manufacturing method, since the same mask is used in the implantation of impurity ions for forming the auxiliary drain region 94 and in the formation of the first control gate 95, the first control for the auxiliary drain region 94 is performed. There is no manufacturing variation in the relative position of the gate 95. In addition, since the floating gate 93 and the first control gate 95 are formed in the same process, the distance between them is always kept at a predetermined value, and the second control in contact with the semiconductor substrate 90 therebetween. The length of the electrode 96 is also always kept at a predetermined value.

According to the third embodiment, since there is no variation in the threshold voltage due to the positional shift of the control gate of the memory cell transistor, the memory cell transistor can be miniaturized. In particular, it is effective when the gate size of the memory cell transistor is 1 占 퐉 or less, and the capacity of the memory cell can be increased.

Example 5

FIG. 42 is a plan view of a memory cell portion of the nonvolatile semiconductor memory device of the present invention, and FIG. 43 is an X-ray cross-sectional view thereof.

A plurality of isolation regions 121 made of LOCOS are formed in the surface region of the P-type semiconductor substrate 120 to partition the device region. A plurality of floating gates 123 are independently disposed on the semiconductor substrate 20 so as to span the adjacent isolation regions 121 through the oxide film 22. An N-type drain region 124 continuous in the column direction is formed in the substrate region at a predetermined distance from each floating gate 123. In addition, a plurality of dummy gates 125 are disposed on the semiconductor substrate 120 through the oxide film 122 so as to coincide with the drain region 124. The dummy gate 120 is disposed so as to be positioned between the two floating gates 123, and the floating gate 123 is linearly symmetrical with respect to the dummy gate 125 (or the drain region 124). The pattern is formed as much as possible. Here, the oxide film 126 covering the floating gate 123 and the dummy gate 125 is formed to have a thin film thickness at each end to form an upper end of the upper surface of the floating gate 123 at an acute angle. N-type source regions 127 continuous in the column direction are formed in the substrate region between each floating gate 123. In addition, a plurality of control gates 128 continuous in the column direction intersecting with the drain region 124 and the source region 127 are formed in parallel with each other so as to cover the floating gate 123 and the dummy gate 125. These floating gates 123, the control gate 128, the drain region 124, and the source region 127 constitute a memory cell transistor.

Each operation of writing, erasing, and reading data in the semiconductor memory device is performed as follows, for example. In the write operation, the potential of the control gate 128 is 2V, the drain region 124 is 0.5V, and the source region 127 is 12V.

Accordingly, the hot electrons generated in the vicinity of the drain region 124 are accelerated toward the floating gate 123 and injected into the floating gate 123 through the oxide film 122 to write data. In contrast, in the erasing operation, the potentials of the drain region 124 and the source region 127 are set to 0V, and the potential of the control gate 128 is set to 14V. As a result, the charges retained in the floating gate 123 are punched through the oxide film 122 by F-N tunneling at the end on the upper surface side, and are discharged to the control gate 128 to erase data. In erasing this data, collective erase is possible by applying a voltage to all the memory cell transistors constantly. In the read operation, the potential of the control gate 128 is 4V, the drain region 124 is 2V, and the source region 127 is 0V. At this time, when charge is injected into the floating gate 63, since the potential of the floating gate 63 is lowered and no channel is formed below the floating gate 63, the source region 127 in the drain region 124. No current flows through the furnace. Conversely, if no charge is injected into the floating gate 63, the potential of the floating gate 63 becomes high, and a channel is formed below the floating gate 63, so that the drain region 124 is moved from the drain region 124 to the source region 127. FIG. The current flows. Thus, by detecting the current flowing out of the drain wing 124 by the sense amplifier, determination of on / off of the memory cell transistor, that is, determination of written data is made. The dummy gate 125 is electrically independent of the floating gate 123 in the same manner as the floating gate 123, and in any operation, the dummy gate 125 is in a floating state.

In the semiconductor memory device described above, the substantial gate length of the memory cell transistor, that is, the distance from the floating gate 123 to the drain region 124 is only the distance between the floating gate 123 and the dummy gate 125. Is determined. Therefore, even if the position shift of the control gate 128 with respect to the floating gate 123 occurs, there is no change in the gate length of the memory cell transistor, and the manufacturing of the write voltage when the threshold voltage or the hot electrons are injected into the floating gate 123 is performed. No deviation occurs. Since the aluminum wiring need not be connected to each drain region 124 of each memory cell transistor, and the drain region 124 becomes smaller, the arrangement pitch of the memory cell transistors in the row direction is reduced.

FIG. 44 is a circuit diagram of the memory cell portion shown in FIG.

In a double gate structure memory cell transistor 130 having three rows by four columns, each gate is connected to a word line 131, and a drain and a source are connected to the first and second bit lines 132 and 133, respectively. do. In reality, the control gate 128 itself forms the bit line 131, and the drain region 124 and the source region 127 continuous in the column direction form the first and second bit lines 132 and 133, respectively. Then, the word line 131 is connected to the X decoder 134 which performs row selection, and the first and second bit lines 132 and 133 are respectively connected to the YD decoder 135 and YS decoder 136 which perform column selection. Connected. Here, the YD decoder 135 activates one of the first bit lines 136, that is, the drain regions 124, according to the address data, and the YS decoder 135 activates the first bit lines 133, that is, the source region. Activate one of (127). Accordingly, the memory cell transistors in the column disposed between the activated drain region 124 and the source region 127 are selected.

45 through 49 are cross-sectional views illustrating processes for manufacturing the nonvolatile semiconductor memory device of the present invention.

[Step 1: Degree 45]

The polycrystalline silicon layer 140 is laminated on the P-type semiconductor substrate 120 through the oxide film 122, and the nitride film 43 is formed on the surface of the polycrystalline silicon layer 140. Then, a resist pattern 143 having an opening 142 is formed at a position where the floating gate 123 and the dummy gate 125 are formed, and the nitride film 141 is etched away using the resist pattern 143 as a mask. do. In this step, it is assumed that the oxide film 122 is selectively oxidized by a known selective oxidation method (L0COS) to form the isolation region 121.

Second Step: Fig. 46

A new resist pattern 144 is formed to cover the opening 142 corresponding to the formation position of the floating gate 123, and the resist pattern 144 and the resist pattern 143 formed in the first process are used as masks. For example, phosphorus ions P are implanted. As a result, the N-type injection region 145 is formed on the surface of the semiconductor substrate 120 corresponding to the formation position of the dummy gate 125.

[3rd process: FIG. 47]

The polycrystalline silicon layer 140 is selectively oxidized using the nitride film 141 as an oxidation mask. According to this oxidation, the oxidation of the polycrystalline silicon layer 140 grows in the sharp axis and the deep portion of the polycrystalline silicon layer 141 at the portion of the opening 142 of the nitride film 141, so that the thick oxide film 146 is formed. It is done. As a result, the film thickness of the polycrystalline silicon layer 140 is partially thinned. In addition, the N-type injection region 145 is diffused by the heat treatment at this time to form the auxiliary drain region 124.

[Step 4: Fig. 48]

The floating gate 123 and the dummy gate 125 are formed by removing the nitride film 141 and leaving the polycrystalline silicon layer 140 under the thick oxide film 146 behind. The floating gate 123 and the dummy gate 125 thus formed have an Y-shaped end portion at the upper surface side thereof.

[Step 5: Fig. 49]

The floating gate 123 and the dummy gate 125 are thermally oxidized together with the oxide film 146, and an oxide film 126 is formed to cover the floating gate 123 and the dummy gate 125. A resist pattern 147 is formed to cover the floating gate 123 and the dummy gate 125, and the substrate between the floating gate 123 using the resist pattern 147 and the floating gate 123 as a mask. The source region 127 is formed by implanting an N-type impurity ion, for example, phosphorus ion P, into the region. At this time, in order to connect the drain regions 124 in the column direction, N-type impurity ions are implanted into the substrate regions (not shown) between the dummy gates 125 adjacent to each other in the column direction. However, the source region 127 needs to diffuse to the region below the floating gate 123 in order to be coupled to the floating gate 123 so as to control the potential of the floating gate 124. Therefore, the implantation energy of phosphorus ions at the time of forming the source region 127 is made higher than at the time of forming the drain region 124 so that the N-type region is easily diffused. The above-described N-type impurity ion implantation may be performed before the floating gate 123 and the dummy gate 125 are oxidized.

In the subsequent step, after removing the resist pattern 147, the polycrystalline silicon layer is laminated again, and the polycrystalline silicon layer 140 is patterned to correspond to each row of the floating gate 123 and the dummy gate 125, thereby extending in the row direction. The control gate 128 is formed.

According to the above manufacturing method, since the same mask is used at the time of implantation of the impurity ions for forming the drain region 124 and the formation of the dummy gate 125, the dummy gate 24 with respect to the drain region 124 is used. There is no deviation of the relative position. In addition, since the floating gate 123 and the dummy gate 125 are formed in the same process, the distance between each other is always kept at a predetermined value so that the length of the control gate 128 in contact with the semiconductor substrate 120 therebetween. Is always kept at a predetermined value.

According to the fifth embodiment, since the drain region between the two memory cell transistors can be made the same as the source region, the arrangement pitch in the row direction of the memory cell transistors can be reduced. In addition, since there is no variation in the threshold voltage due to the positional shift of the control gate of the memory cell transistor, the memory cell transistor can be miniaturized, and is effective for increasing the memory cell capacity while reducing the arrangement pitch of the memory cell transistor.

Claims (11)

A non-volatile semiconductor memory device, comprising: a conductive semiconductor substrate, at least one pair of isolation regions formed on the semiconductor substrate, and a floating gate disposed in an electrically independent state between the isolation regions on the semiconductor substrate; And a first semiconductor region of a reverse conductivity type formed in the substrate region on the side opposite to the side of the floating gate opposite to the control gate, and formed in the substrate region on the side opposite to the side opposite to the floating gate of the control gate. A second semiconductor region having a reverse conductivity type, the floating gate extends over the separation region, and a thickness of the floating gate is formed to be thinner than an end portion in a direction crossing the control gate. Non-volatile semiconductor memo characterized in that it is formed almost uniformly in the parallel direction Lee device. A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a separation region extending in a first direction on a conductive semiconductor substrate at a predetermined interval, and forming the separation region on the semiconductor substrate including the separation region. Laminating a one-gate material layer, forming a resistive oxide film having an opening extending in a second direction perpendicular to the first direction at a predetermined width on the first gate material layer; The one-gate material layer is selectively oxidized along the opening of the oxidation resistant film to form an oxide film having a thicker film thickness than the oxide film under the oxidation resistant film, which is continuous in the second direction, and extends in the second direction. Forming an inner etching layer having an opening on the thick oxide film, and etching the thick oxide film using the inner etching layer as a mask. Forming a plurality of island shapes by separating the cloud oxide film in the first direction, and selectively removing the first gate material layer leaving a portion positioned below the thick oxide film continuous in the first direction. Forming a plurality of electrically independent floating gates, and selectively removing a second gate material layer covering the floating gates, wherein the control gates overlap at least a portion of the floating gates and continue in the second direction. Forming a reverse conductive semiconductor region by implanting impurities of a reverse conductivity into a substrate region adjacent to the floating gate and the control gate; and forming a reverse conductive semiconductor region. . A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a separation region extending in a first direction on a conductive semiconductor substrate at a predetermined interval, and forming the separation region on the semiconductor substrate including the separation region. Laminating a one-gate material layer, forming a oxidation resistant film having an opening extending in a second direction orthogonal to the first direction with a predetermined width on the first gate material layer, and the first gate material Selectively oxidizing the layer along the opening of the oxidation resistant film to form an oxide film having a thicker film thickness than the oxide film under the oxidation resistant film, continuing in the second direction, and a portion located below the thick oxide film. Selectively removing the first gate material layer, and leaving the first gate material layer corresponding to the thick oxide film. Forming a etched layer having the first gate opening extending in the first direction, etching the first gate material layer extending in the second direction using the etched layer as a mask, Forming a plurality of electrically independent floating gates by separating in the first direction, selectively removing a second gate material layer covering and covering the floating gates, wherein at least a portion of the floating gates overlaps with the floating gates; Forming a control gate that is continuous in two directions, and forming a reverse conductive semiconductor region by implanting a reverse conductive impurity into the floating gate and a substrate region adjacent to the control gate; Method of manufacturing volatile semiconductor memory device. A nonvolatile semiconductor memory device, comprising: a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate in an electrically independent state, a control gate adjacent to the floating gate and at least partially overlapping the floating gate; A control gate disposed adjacent to the floating gate and overlapping at least a portion thereof, a first non-conductive type semiconductor region formed in the substrate region on the opposite side of the floating gate from the side opposite to the control gate, and the floating of the control gate A second semiconductor region having a reverse conductivity type formed in the substrate region on the opposite side to the side opposite to the gate, wherein the surface region of the semiconductor substrate on which the floating gate is latched and the surface region of the semiconductor substrate on which the control gate is disposed And a step in which the control gate side is lowered between is formed. A nonvolatile semiconductor memory device made with a gong. A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming an oxidation resistant film having an opening corresponding to a formation position of a floating gate on a first gate material layer stacked on a conductive semiconductor substrate; Selectively oxidizing a gate material layer along the opening of the oxidation resistant film to form an island-shaped oxide film having a thicker thickness than the oxide film under the oxide resistant film; Leaving a gate material layer and selectively removing a portion of the surface of the gate material layer and the surface of the semiconductor substrate by etching, and forming an electrically independent floating gate, at a position where the floating gate is formed on the surface of the semiconductor substrate. Forming an elevated step, and oxidizing the floating gate and the exposed surface of the semiconductor substrate. Forming an interlayer insulating film, selectively removing a second gate material layer stacked on the interlayer insulating film by etching, and forming a control gate at least partially overlapping the floating gate; And injecting an impurity of a reverse conductivity into a substrate region adjacent to the control gate to form first and second semiconductor regions of a reverse conductivity. A non-volatile semiconductor memory device comprising: a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate, a first control gate disposed on the semiconductor substrate at a predetermined distance from the floating gate, and the floating A second control gate disposed between the gate and the first control gate and overlapping at least a part of the floating gate, and a substrate region on the opposite side to the side of the floating gate facing the rigid first control gate; A non-conductive semiconductor having a reverse conductive type first semiconductor region formed and a reverse conductive type second semiconductor region formed in a substrate region on a side opposite to the side opposite to the floating gate of the first control gate. Memory device. A non-volatile semiconductor memory device comprising: a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate, a first control gate disposed on the semiconductor substrate at a predetermined distance from the floating gate, and the floating A control gate connected between the gate and the first control gate and connected to the first control gate and disposed to overlap at least a part of the floating gate, and to face the first control gate of the floating gate; A first semiconductor region of reverse conductivity type formed in the substrate region on the side opposite to the side, and a second semiconductor region of reverse conductivity type formed in the substrate region on the side opposite to the side opposite to the floating gate of the first control gate. Non-volatile semiconductor memory device, characterized in that. A nonvolatile semiconductor memory device, comprising: a conductive semiconductor substrate, a floating gate disposed on the semiconductor substrate, a first conductive region of a reverse conductivity type formed in a substrate region at a predetermined distance from the floating gate, and the first semiconductor region. A first control gate overlapping the first semiconductor region and disposed on the semiconductor substrate, a second control gate interposed between the floating gate and the first control gate, and overlapping at least a portion of the floating gate; A second semiconductor region of a reverse conductivity type formed in the substrate region on the side opposite to the side of the floating gate opposite to the floating gate, and continuous to the first semiconductor region; and the side opposite to the first control gate of the floating gate. And a non-conducting third semiconductor region formed in the substrate region on the opposite side of the substrate. Memory device. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising: forming an oxide film having openings paired at a predetermined distance on a first gate material layer stacked on a conductive semiconductor substrate; Punching through the first gate material layer from one of the openings to implant reverse conductive impurity ions into the semiconductor substrate to form a reverse conductive first semiconductor region in the surface region of the semiconductor substrate; Selectively oxidizing the gate material layer according to each opening of the oxidation resistant film, selectively etching away the first gate material layer, and forming a first control gate corresponding to one of the openings of the oxidation resistant film; Forming a floating gate corresponding to the other side of the opening together, and covering the first control gate and the floating gate together with the semiconductor substrate. Selectively etching away the second gate material layer deposited on the substrate, and forming a second control gate between the first control gate and the floating gate, and facing the floating gate of the first control gate. Forming a second semiconductor region of a reverse conductivity type in the first semiconductor region by implanting impurity ions of a reverse conductivity type into the substrate region on the opposite side of the semiconductor substrate by using the first control gate as a mask; And forming a third semiconductor region of a reverse conductivity type by implanting impurity ions of a reverse conductivity type into the substrate region on the side opposite to the side of the first control gate. A method of manufacturing a volatile semiconductor memory device. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate of one conductivity type, a plurality of floating gates arranged in a matrix on the semiconductor substrate, and formed in a surface region of the semiconductor substrate at a predetermined distance from the floating gate, wherein the floating A plurality of reverse conductive first semiconductor regions continuous in the column direction of the gate, a simulated gate overlapping the first semiconductor region and disposed in parallel with the floating gate on the semiconductor substrate, the floating gate and the simulated gate A plurality of control gates arranged on the substrate and continuous in the row direction of the floating gate, and formed in a surface region of the semiconductor substrate on the side opposite to the side of the floating gate that faces the simulation gate; Non-volatile, characterized in that the second semiconductor region of the reverse conductivity type continuous in the direction Semiconductor memory device. A method of manufacturing a nonvolatile semiconductor memory device, comprising: an oxide film having a plurality of openings arranged in pairs at a predetermined distance and arranged in a matrix on a first gate material layer stacked on a conductive semiconductor substrate. Forming a first semiconductor region by punching through the first gate material layer from one side of each opening of the oxidation resistant film and implanting reverse conductive impurity ions into a surface region of the semiconductor substrate; And selectively oxidizing the first gate material layer in accordance with the opening of the oxidation resistant film, selectively etching away the first gate material layer, and forming a simulated gate corresponding to one of each opening of the oxidation resistant film. And forming a floating gate corresponding to the other side, and a side opposite to the side of the floating gate that faces the simulated gate. Forming a second semiconductor region continuous in the column direction by implanting impurity ions of a reverse conductivity type into the surface region of the semiconductor substrate using the floating gate as a mask; and forming a second semiconductor region continuous in the column direction. Implanting impurity ions of a reverse conductivity into a surface region, and forming a third semiconductor region connecting the first semiconductor region in a column direction, and covering the simulation gate and the floating gate and stacked on the semiconductor substrate. And selectively removing the two-gate material layer and forming a control gate that is continuous in the row direction on the first control gate and the floating gate.