JPH07273198A - Multilayer wiring structure for semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To eliminate the need of filling a through hole with a metal, e.g. the need of a W plug, for a contact between metallizations while achieving a positive contact through an easy process and to make a contact having no overlap while making thin the layer insulating film. CONSTITUTION:The multilayer metallization structure for semiconductor device comprises more than two metal layers formed on an underlying layer wherein the odd number metal layers 11, counted from the underlying layer side, constitute a metallization layer whereas the even number metal layers provide connection between the metallization layers, e.g. connection between upper and lower wirings 2, 16 or connection between wirings 2a, 2b through a same odd number metal layer. The connection layer between respective metallization layers are formed by reflow after high temperature sputtering or low temperature sputtering.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure of a semiconductor device and a manufacturing method thereof. INDUSTRIAL APPLICABILITY The present invention can be suitably used, for example, as a multilayer wiring structure in a miniaturized / integrated semiconductor device and as a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device, a multilayer wiring structure having a structure in which two or more metal wiring patterns are laminated is used.

FIG. 13 shows a cross-sectional schematic view of the most common multilayer aluminum wiring device at present as a typical conventional example of the multilayer wiring structure. In FIG. 13, reference numeral 1 is an interlayer insulating film forming a base layer, 2 is a first layer aluminum wiring, 4'is an interlayer insulating film on the base layer 1 and the first layer aluminum wiring 2,
Reference numeral 11 is a second layer aluminum wiring, 3'is a through hole for conduction between the first and second layer aluminum wirings 2 and 11, and
Is a W plug in the through hole 2, 8'is an interlayer insulating film on the second layer aluminum wiring 11, 16 is a third layer aluminum wiring, 7'is a second and third layer aluminum wiring 1
A through hole for conduction between 1 and 16 and 9'is a W plug in the through hole 7 '.

Generally, when a multilayer aluminum wiring is automatically laid out, the first layer aluminum wiring 2 is basically laid out in the X direction, and the third layer aluminum wiring 16 is the same as the first layer aluminum wiring 2. Laid out in the direction.

Further, in the example of FIG. 13, the through holes are filled with W plugs, but in the devices of the 0.35 μm generation or later in which the aspect ratio of the through holes becomes high, such through holes having such a fine and high aspect ratio are formed. Nevertheless, it is considered that a technique for achieving good connection is indispensable, and a technique for embedding a metal such as a W plug is also indispensable.

However, when the W plug is used, there is a problem that a new equipment is required and the wafer cost is increased due to the increase in the number of steps.

When the film thickness between the aluminum wiring layers is large as in the conventional example shown in FIG. 13, when a through hole is formed in the aluminum wiring layer, the aluminum of the through hole portion is prevented so that the through hole does not come off from the lower layer aluminum wiring. It was necessary to make the part thicker, which hindered high integration.

If the through hole is deviated from the underlying wiring 2 as shown in FIG. 14, the amount of contact etching is large because the interlayer insulating film 4'in the deviated portion is thick. It is difficult to embed even with a W plug, for example. In FIG. 14, reference numeral 5
1 indicates a deep groove portion which requires such deep filling.

[0009]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art and eliminates the need to bury a metal in a through hole such as a W plug for a contact between metal wirings, and achieves a reliable connection in an easy process. Further, it is an object of the present invention to provide a highly integrated multi-layer wiring structure of a semiconductor device, which enables a thin interlayer insulating film, and also enables overlapless contact, and a method for forming the same.

[0010]

The invention according to claim 1 of the present application is a multilayer metal wiring structure of a semiconductor device comprising three or more metal layers on a base, wherein the metal layer is an odd-numbered metal layer from the base side. A multi-layer wiring structure of a semiconductor device, characterized in that a metal wiring layer is constituted by and a connection layer for connecting between the metal wiring layers is constituted by an even-numbered metal layer from a base side. Is achieved.

According to a second aspect of the present invention, the connection between the metal wiring layers by the even-numbered metal layers from the base side is a connection between upper and lower wirings. A multilayer wiring structure of a device, which achieves the above object.

The invention of claim 3 of the present application is characterized in that the connection between the metal wiring layers by the even-numbered metal layers from the base side is the connection between the wirings by the same odd-numbered metal layer. A multilayer wiring structure of a semiconductor device according to claim 1, wherein the above object is achieved.

The invention according to claim 4 of the present application comprises three or more metal layers on the underlayer, the metal wiring layer is constituted by the odd-numbered metal layers from the underlayer side, and the even-numbered metal layer from the underlayer side. A method of manufacturing a multilayer wiring structure of a semiconductor device, comprising a connection layer for connecting between the metal wiring layers by layers, wherein the formation of the connection layer between each metal wiring layer is performed by a metal sputtering method. A method for manufacturing a multilayer wiring structure of a semiconductor device, which achieves the above object.

The invention of claim 5 of the present application comprises three or more metal layers on the underlayer, the metal wiring layer is constituted by the odd-numbered metal layers from the underlayer side, and the even-numbered metal layers from the underlayer side. A method of manufacturing a multilayer wiring structure of a semiconductor device, comprising a connection layer for connecting the metal wiring layers by layers, wherein each metal wiring layer is formed of aluminum sputtered at 500 ° C. or lower. A method for manufacturing a multilayer wiring structure of a semiconductor device, which achieves the above object.

According to the invention of claim 6 of the present application, the metal wiring layer is provided with three or more metal layers on the underlayer, and the metal wiring layer is composed of the odd-numbered metal layers from the underlayer side. A method of manufacturing a multilayer wiring structure of a semiconductor device, comprising a connection layer for connecting between the metal wiring layers by layers, wherein the metal wiring layers of the respective layers are sputtered with aluminum at a low temperature of 300 ° C. or lower, and then 400 ° C. A method of manufacturing a multilayer wiring structure of a semiconductor device, which is characterized in that aluminum is made to flow by applying the above temperature, and thereby the above object is achieved.

[0016]

In the present invention, since the metal wiring layers are connected by the even-numbered metal layers, it is not necessary to fill the through holes such as W plugs with metal. Therefore, it is not necessary to form the through hole, and the displacement of the through hole from the wiring layer does not occur. A reliable connection can be achieved by an easy process without a connection failure due to an embedding failure. Moreover, the interlayer insulating film can be thinned. As a result, overlapless contact is possible and high integration is possible.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. However, it should be understood that the present invention is not limited to the illustrated embodiments.

Example 1 As shown in FIG. 1, the semiconductor device connection structure of this example is such that three or more metal layers (first metal layer, which is the first aluminum layer, second metal layer 2 and second metal layer) are formed on the underlayer. A multi-layer metal wiring structure of a semiconductor device comprising a second metal layer 11 made of aluminum and a third metal layer 16 made of aluminum, the metal layers 2 and 16 being an odd number from the base side. A wiring layer is formed, and a connection layer for connecting the metal wiring layers 2 and 6 (connection between upper and lower wirings) is formed by the even numbered metal layer 11 from the base side. In the present embodiment, the even-numbered metal layer 11 is used to connect the wirings 2a and 2b in the same layer therebelow from the base side (connection between wirings by the same odd-numbered metal layer). .

When manufacturing the connection structure of this embodiment, the connection layer (metal layer 11) between the metal wiring layers 2 and 16 is formed by the metal sputtering method.

More specifically, the connection structure of this embodiment is manufactured by the following steps. Please refer to FIG. 2 to FIG. First, referring to FIG.

In advance, a semiconductor substrate 1a (here, a Si substrate.
1), an element isolation region is formed, a gate oxide film is formed, and a transistor is formed (not shown). On top of this, an interlayer insulating film 1 as a base of wiring is formed with SiO ₂ , PS.
It is formed of G, BPSG, or the like. After that, a contact hole is formed in the interlayer insulating film 1 (not shown), and the first layer of aluminum (1Al) is sputtered. Thus, the aluminum film 21 for forming the first metal layer 2 is formed. In this embodiment, the first layer of aluminum forming the first metal layer 2 is a composite film of, for example, Ti, TiN, AlCu (AlSiCu) or the like.

SiO ₂ 3 is deposited on the first metal layer 2 by CVD of several tens of nm to several hundreds of nm, and then Pol of several hundreds of nm is continuously formed.
CVD of y-Si at a low temperature of 450 ° C. or lower, or Pol
An intermediate layer 4 made of y-Si, Ti, TiN or the like is formed on the SiO ₂ 3 by several hundred nm by a sputtering method, and further, the first metal layer 2 is formed.
A resist pattern 5 for patterning (1Al) is formed. From the above, the structure shown in FIG. 2 is obtained.

Using the resist pattern 5 as a mask,
Poly-Si (or Ti, TiN) intermediate layer 4 and Si
Aluminum film 21 for forming O ₂ film 3 and first metal layer 2
Is continuously RIEed, and thereafter, the SiO ₂ film 6 is formed by plasma TEOS or the like, and then the O ₃ TEOS-NSG film 7 is formed.
Then, the gap between the metal layers (aluminum-aluminum) is filled. For a rather wide metal layer (aluminum-aluminum film), the resist 8 is embedded in the gap by the resist etch back method. As described above, the structure of FIG. 3 in which the first metal layer 2 is patterned is obtained.

The resist 8 is used as a mask to etch back the entire surface of the NSG film 7 to remove the resist 8.
The surface of the device is flattened by coating SOG9 having a thickness of about m to several hundreds nm. With the above, the structure of FIG. 4 is obtained.

A resist is applied and patterned, and using the obtained resist pattern 10 as a mask,
The SOG 9 is etched to expose the Poly-Si (or Ti, TiN) intermediate layer 4 on the first metal layer (1Al), and then this Poly-Si intermediate layer 4 is removed by using an etching gas such as SF _6. Selectively etch. With the above, the structure of FIG. 5 is obtained.

Subsequently, using the resist pattern 10 as a mask, the SiO ₂ film 3 on the first metal layer 2 (1Al) is RI.
After E, the first metal layer 2 (1Al) is partially exposed, and then the resist pattern 10 is removed. This portion (see FIG. 6) where the first metal layer 2 (1Al) is partially exposed becomes a connection portion with the upper metal wiring layer. Therefore, a contact is made in the thin opening where the thin SiO ₂ film 3 is removed.

After that, the above-mentioned first metal layer 2 (1A
The second-layer metal layer 11 (2Al) is formed and patterned by exactly the same method as 1).

As described above, the second metal layer 11 (2A
l) is formed, the second metal layer 11 (2Al) is formed.
Is connected to the first-layer metal layer 2 (1Al) by a through hole opened in a very thin interlayer insulating film (SiO ₂ film 3), so that tungsten or the like for filling the through hole is not necessary.

In this embodiment, the interlayer aluminum which is the second metal layer 11 is formed by the sputtering method at a temperature of room temperature to 500 ° C. With the above, the structure of FIG. 6 is obtained.

The second metal layer 11 (2Al) and the first metal layer 2 (1Al) are very thin interlayer insulating film SiO.
Since they are separated by the _two films 3, the second-layer metal layer 11 (2Al) and the first-layer metal layer 2 are separated from the viewpoint of wiring capacitance and interlayer breakdown voltage.
(1Al) is not laid out so as to face each other, and as shown in FIG. 6, for connecting adjacent first-layer metal layer (1Al) wirings (in particular, shown by reference numerals 2a and 2b in FIG. 6). , And plays a role of connecting the first metal layer 2 and the third metal layer 16 (1Al and 3Al). In addition, in the portion where a large current flows like the power supply wiring, the first layer, the second layer
The layer metal layers 2 and 11 (1Al, 2Al) are stacked to have a film thickness and are used for ensuring electromigration resistance.

After the second metal layer 11 (2Al) is flattened in the same manner as the first metal layer 2 (1Al), the third metal layer 16 (3Al) is wired. Formed as a layer. This is the first layer, the second metal layer 2, 11
It is formed by the same method as (1Al, 2Al). From the above, the structure of FIG. 7 is obtained. 12 'is a SiO ₂ film, 13
Is a polysilicon film.

In this embodiment, the third metal layer 16 (3
Al) is automatically laid out in a direction orthogonal to the first metal layer 2 (1Al).

In the same manner, the odd-numbered metal layer (odd-layer aluminum wiring) is used as a normal aluminum wiring, and the even-numbered aluminum wiring is used as a short wiring, a connection wiring, and a power supply wiring thick film. The structure.

Through the above steps, the third metal layer 16 shown in FIG.
(3Al) is formed to complete the device. In the figure, reference numeral 17 is an overpassivation film forming a protective layer.

As is clear from the above description, in this embodiment, a metal plug such as a W plug is not required to connect the multi-layer wiring layers, and the wafer cost can be reduced. Figure 1
In the figure, reference numeral 18 is a W plug buried in a connection hole opened in the insulating film which is the base 1, which is formed in the diffusion region of the substrate (base layer 1a) and the first metal layer 2 (1A
l) to make a connection.

In the present embodiment, the interlayer insulating film (SiO ₂
Since 3) is thin, overlapless contact is possible and high integration is possible.

Embodiment 2 FIGS. 8 to 12 show the steps of Embodiment 2.

In the case of this embodiment, S on aluminum is used.
iO _2, Poly-Si indicates a simple process no.

Referring to FIG. Also in this embodiment, an element isolation region, a gate oxide film, and a transistor (not shown) are formed on the semiconductor substrate 1a (here, the Si substrate) in advance, and a wiring underlying layer is formed on the element isolation region. The interlayer insulating film 1 is formed of SiO ₂ , PSG, BPSG, or the like, and then a contact hole is formed in the interlayer insulating film 1 (not shown), and the first layer of aluminum (1Al) is formed as in Example 1. Sputtering is performed to form an aluminum film 21 for forming the first metal layer 2.

In the present embodiment, a film (such as SiO ₂ 3 or Po in Embodiment 1) is formed on the film 21 for forming the first metal layer.
The resist pattern 5 for patterning the first metal layer 2 (1Al) is formed without forming the layer 4) such as ly-Si. From the above, the structure shown in FIG. 8 is obtained.

Using the resist pattern 5 as a mask,
RIE is performed on the aluminum film 21 for forming the first metal layer 2. Thereafter, the SiO ₂ film 6 is formed by plasma TEOS or the like as in the first embodiment, and then the O ₃ TEOS-NSG film 7 is formed.
Then, the gap between the metal layers (aluminum-aluminum) is filled. For a rather wide metal layer (aluminum-aluminum film), the resist 8 is embedded in the gap by the resist etch back method. With the above, the structure of FIG. 9 is obtained.

The resist 8 is used as a mask to etch back the entire surface of the NSG film 7 to remove the resist 8.
The device surface is flattened by coating the insulating film 91 with SOG or the like having a thickness of about m to several hundred nm. A resist is applied and its patterning is performed. With the above, the structure of FIG. 10 is obtained.

The insulating film 91 is etched using the obtained resist pattern 10 as a mask to etch the first metal layer 2 (1
Al) is partially exposed. Then, the resist pattern 10 is removed. After this, the above-mentioned first metal layer 2
In the same manner as (1Al), the second metal layer 11 (2A
l) is formed and patterned.

When the second layer metal layer 11 (2Al) is formed by removing the boundary of the SiO ₂ film as described above, this second layer metal layer 11 (2Al) is formed in the very thin interlayer insulating film 91. The first metal layer 2 (1
Since it is connected to Al), tungsten or the like for filling the through hole is not necessary.

Here, in this embodiment, the interlayer aluminum which is the second metal layer 11 is formed by the sputtering method at a temperature of room temperature to 500 ° C. With the above, the structure of FIG. 11 is obtained.

The second metal layer 11 (2Al) and the first metal layer 2 (1Al) are made of SiO, which is a thinner interlayer insulating film.
Since they are separated by the _two films 3, the second-layer metal layer 11 (2Al) and the first-layer metal layer 2 are separated from the viewpoint of wiring capacitance and interlayer breakdown voltage.
(1Al) is not laid out to face each other, and as shown in FIG. 11, for connecting adjacent first-layer metal layer (1Al) wirings (in particular, shown by reference numerals 2a and 2b in FIG. 11). , The first metal layer 2 and the third metal layer 16 (1A
1 and 3Al). Also in this embodiment, the first layer and the second layer metal layers 2 and 11 (1Al, 2Al) are provided in the portion where a large current flows like the power supply wiring.
Is used to obtain a film thickness by stacking and to ensure electromigration resistance.

After flattening the second metal layer 11 (2Al) in the same manner as the first metal layer 2 (1Al), the third metal layer 16 (3Al) is wired. Formed as a layer. This is the first layer, the second metal layer 2, 11
It is formed by the same method as (1Al, 2Al). From the above, the structure of FIG. 12 is obtained.

The present embodiment has a simpler structure than that of the first embodiment, and the same effect can be obtained.

Embodiments 3 and 4 In these embodiments, the second metal wiring layer 11 in Embodiments 1 and 2 is formed by sputtering aluminum at a low temperature of about 280 ° C., which is 300 ° C. or less, and 400 ° C. or more. It was formed by heating to a reflowable temperature of about 450 ° C. and flowing. Others were the same as in Examples 1 and 2.

Also in this embodiment, the second metal wiring layer 1
1, the connection of the first layer and the second layer metal wiring layers 2 and 16;
Also, the connection between the wirings 2a and 2b in the same layer was satisfactorily achieved, and the same effect as that of the above-described embodiment could be obtained.

[0051]

As described above, according to the present invention, it is necessary to bury a metal in a through hole such as a W plug as a connection between multi-layer metal wirings, a reliable connection can be achieved by an easy process, and an interlayer insulating film can be achieved. Thus, it is possible to provide a multilayer wiring structure of a semiconductor device which can be made into a thin film and which enables an overlapless contact and can be highly integrated, and a method for forming the same.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a connection structure of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the first embodiment (1).

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device connection structure according to the first embodiment (2).

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device connection structure according to the first embodiment (3).

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device connection structure according to the first embodiment (4).

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device connection structure according to the first embodiment (5).

FIG. 7 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the first embodiment (6).

FIG. 8 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the second embodiment (1).

FIG. 9 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the second embodiment (2).

FIG. 10 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the second embodiment (3).

FIG. 11 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the second embodiment (4).

FIG. 12 is a cross-sectional view showing the manufacturing process of the connection structure of the semiconductor device according to the second embodiment (5).

FIG. 13 is a diagram showing a conventional multilayer wiring structure.

FIG. 14 is a diagram showing a problem of the conventional technique.

[Explanation of symbols]

First interlayer insulating film 2 first-layer aluminum wiring (first layer metal layer) 2a, the wiring 3 SiO ₂ 4 intermediate layer 2b same odd layers (first layer aluminum) (Poly-Si, Ti, TiN
Film 5 Resist pattern 6 P-TEOS, P-SiO, SiO ₂ 7 O ₃ TEOSSiO ₂ 8 Resist 9 SOG 10 Contact window opening resist pattern 11 Second layer aluminum wiring (second layer metal layer) 12 SiO ₂ 13 Poly -Si, Ti, TiN 14 Interlayer insulating film 15 Via contact 16 Third layer aluminum wiring (third layer metal layer) 17 Protective layer (overpassivation film) 18 Metal (W) plug for connection to underlying substrate 91 Thin interlayer Insulation film

Claims (6)

[Claims] 1. A multi-layer metal wiring structure of a semiconductor device comprising three or more metal layers on an underlayer, wherein the metal wiring layer is composed of an odd number of metal layers from the underside, and an even number layer from the underside. A multi-layer wiring structure for a semiconductor device, characterized in that a connection layer for connecting the metal wiring layers is constituted by the metal layer. 2. The multilayer wiring structure of a semiconductor device according to claim 1, wherein the connection between the metal wiring layers by the even-numbered metal layers from the base side is a connection between upper and lower wirings. 3. The semiconductor device according to claim 1, wherein the connection between the metal wiring layers by the even-numbered metal layers from the base side is the connection between the wirings by the same odd-numbered metal layer. Multi-layer wiring structure. 4. A metal wiring layer comprising three or more metal layers on the underlayer, wherein the metal wiring layers are composed of odd-numbered metal layers from the ground side, and the metal wiring layers are connected by even-numbered metal layers from the ground side. A method of manufacturing a multilayer wiring structure of a semiconductor device having a connection layer configured to perform a method of manufacturing a multilayer wiring structure of a semiconductor device, characterized in that a connection layer between each metal wiring layer is formed by a metal sputtering method. Method. 5. A metal wiring layer comprising three or more metal layers on an underlayer, wherein the metal wiring layers are composed of odd-numbered metal layers from the underlying side, and the metal wiring layers are connected by even-numbered metal layers from the underlying side. A method of manufacturing a multilayer wiring structure of a semiconductor device having a connection layer configured to perform a method of manufacturing a multilayer wiring structure of a semiconductor device, characterized in that the metal wiring layer of each layer is formed of aluminum sputtered at 500 ° C. or less. Method. 6. A metal wiring layer comprising three or more metal layers on an underlayer, wherein the metal wiring layer is composed of odd-numbered metal layers from the ground side, and the metal wiring layers are connected by even-numbered metal layers from the ground side. A method of manufacturing a multi-layer wiring structure for a semiconductor device having a connection layer configured to perform the following: sputtering aluminum at a low temperature of 300 ° C. or lower on each metal wiring layer, and then applying a temperature of 400 ° C. or higher to aluminum. A method of manufacturing a multi-layer wiring structure of a semiconductor device, which is characterized by being formed by flow.