JP3695771B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, when forming a lower electrode or a lower layer wiring and an upper layer wiring having a contact portion between the lower electrode and the lower wiring, an interlayer insulating film is formed on the lower electrode or the lower layer wiring, and the interlayer insulating film is contacted A hole is opened, an Al—Si film or the like is formed through the hole, and a wiring is formed by patterning into a predetermined pattern. However, with this method, it is difficult to flatten due to the level difference caused by the wiring. Therefore, for example, a structure in which a wiring is embedded in an insulating film as in JP-A-2-126654 is considered.
[0003]
Based on FIGS. 6 and 7, a method for connecting a semiconductor substrate and a wiring and a method for connecting a wiring and a wiring in a semiconductor device described in Japanese Patent Application Laid-Open No. 2-126654 will be described. First, as shown in FIG. 6A, a gate electrode 33 is disposed on a silicon substrate 31 on which an element isolation insulating film 32 is formed, and a source and a drain 34 are disposed to form a transistor. Thereafter, a BPSG film 35 is deposited on the substrate 31 as an interlayer insulating film by atmospheric pressure CVD, and annealed at 900 ° C. for 10 minutes to flatten the upper surface.
[0004]
Next, as shown in FIG. 6B, the source and drain 34 formed on the substrate 31 are formed on the BPSG film 35 by a photolithography process and an anisotropic dry etching technique using a resist (not shown). A contact hole 36 leading to the gate electrode 33 is formed.
Then, a resist (not shown) is processed into a wiring pattern by photolithography. Subsequently, as shown in FIG. 6C, for example, a 1 μm wiring groove 37 is formed on the contact hole 36 of the BPSG film 35 by anisotropic dry etching using this as a mask, and the resist is removed.
[0005]
Next, as shown in FIG. 6D, W38 is grown only in the contact hole 36 by selective CVD-W using WF ₆ + SiH ₄ . Next, AlSi is deposited as a first wiring layer by a bias sputtering method, a wiring groove 37 is buried, and excess AlSi is removed by anisotropic dry etching to form an AlSi wiring layer 39.
[0006]
After forming the AlSi wiring layer 39 as the first wiring layer in this way, as shown in FIG. 7E, a silicon oxide film 40 is deposited thickly on these wiring layers.
Next, as shown in FIG. 7F, a contact hole is formed in the silicon oxide film 40 and a wiring groove of the second wiring layer is formed by the same method as in the previous step.
Then, as shown in FIG. 7G, as in the previous step, the contact hole and the wiring groove are filled with W41 and AlSi42 to form the second wiring.
[0007]
However, in the above-described method, there is the next problem.
[0008]
That is, in the above method, since the self-alignment between the contact hole and the wiring groove cannot be performed, it is necessary to prevent photoalignment between the contact hole and the wiring groove on the contact hole . In the above method, because of this shift prevention, but is taking the width of the co Ntakutoho Le, which becomes possible to widen the wiring pitch, a problem for miniaturization of the element.
The problem to be solved by the present invention is to reduce the cell size without requiring an extra alignment margin.
[0010]
[Means for Solving the Problems]
According to the semiconductor device of the present invention, at least the lower wiring layer,
Wherein an interlayer insulating film on the lower wiring layer is connected to the lower wiring layer, and an upper wiring layer having a top surface which forms substantially the same surface as the upper surface of the interlayer insulating film,
The interlayer insulating film, at least a first insulating film,
A second insulating film having an etching rate smaller than that of the first insulating film ;
A third insulating film in this order ,
The second insulating film includes an opening having a major axis and a minor axis penetrating the second insulating film,
The third insulating film includes a wiring pattern groove in which the upper wiring layer is wired,
It said first insulation Enmaku is the previous SL and the opening and the wiring pattern groove comprises a contact hole consisting of only the portion which overlaps in a plan view, and the upper wiring layer and the lower wiring layer and the contact hole Connected through the opening in the overlapping portion in plan view ,
The shape of the opening is
Oite in a direction perpendicular to the extending direction of the wiring pattern groove is greater than the maximum dimension width of the wiring pattern groove and Oite the extending direction of the wiring pattern groove has a maximum dimension the wiring pattern There is provided a semiconductor device having a size substantially equal to the width of the groove .
[0011]
The semiconductor device of the present invention comprises at least a lower wiring layer, an interlayer insulating film that is a multilayer film, and an upper wiring layer. As a lower wiring layer, an interlayer insulating film or the like is formed on a substrate on which elements such as transistors and capacitors formed in a semiconductor device are formed, and a wiring layer having a desired pattern formed thereon, an impurity Including the semiconductor substrate itself into which is implanted. In the case of a wiring layer having a desired pattern, the material is not particularly limited as long as it is normally used as an electrode material. For example, AlSi, Al, Pt, Ti, W, Ta, AlCu , Cu, Ag, TiN, etc., or electrode materials such as Pt / Ti, Pt / Ta, AlCu / TiN, Cu / TiN, etc., in which two or more layers are laminated. The film thickness at this time can be adjusted as appropriate depending on the size of the device to be formed, and is preferably about 3000 to 6000 mm, for example.
[0012]
The interlayer insulating film of the semiconductor device in the present invention is formed on the lower wiring layer and is formed as a laminated film of at least three layers. Of the interlayer insulating films, the first insulating film formed immediately above the lower wiring layer is not particularly limited as long as it has good flatness and is usually used as an interlayer insulating film. ₂ , PSG, BPSG and the like. The film thickness at this time is preferably about 5000 to 20000 mm.
[0013]
The second insulating film formed on the first insulating film is not particularly limited as long as it has a property to serve as a dry etching barrier with respect to the material used as the first insulating film. . In other words, when dry etching is performed using an etching gas containing a fluorine-based or chlorine-based gas, the selectivity between the first insulating film and the second insulating film is about 10-30. For example, SiN, SiBN, BN, etc. may be mentioned. In particular, after forming a diffusion layer or wiring, it is preferable to form plasma at a low temperature in order to prevent re-diffusion and wiring melting. SiN etc. are mentioned. In this case, the second insulating film is preferably formed so that the thickness of the second insulating film is finally about 100 to 2000 mm on the first insulating film.
[0014]
Further, as the third insulating film formed on the second insulating film, it may be used the same material as the first insulating film. In this case, the same material may be used for the first insulating film and the third insulating film, but the same material may be used as long as it is not necessarily the same material. The film thickness at this time is preferably about 5000 to 10,000 mm.
As described above, when the interlayer insulating film is formed in a three-layer structure, the first insulating film includes a contact hole consisting only of a portion where the opening and the wiring pattern groove overlap in plan view, The lower wiring layer and the upper wiring layer are connected to each other through an opening that overlaps the contact hole in plan view .
On the other hand, the shape of the opening has a wide planar shape in a direction orthogonal to the extending direction of the wiring pattern groove to be described later, and the length in the extending direction (the width of one side that is not a wide side) is It is formed to be approximately equal to the width of a wiring pattern groove to be described later. For example, as the planar shape of the opening, a rectangle, an ellipse, or a shape as shown in FIG. 4 can be appropriately selected and used. In these cases, the major axis X of this opening is orthogonal to the extending direction of the upper wiring layer described later, and the minor axis Y is formed in substantially the same manner as the width of the upper wiring layer.
The lengths of the major axis X and the minor axis Y are not particularly limited, but are preferably about 0.5 to 1.2 μm and about 0.1 to 0.6 μm, respectively.
[0015]
In the third insulating film, a wiring pattern groove in which an upper wiring layer to be described later is disposed is formed, and the upper surface of the third insulating film and the upper surface of the upper wiring layer are substantially flush with each other. .
In the case where the interlayer insulating film is formed of four layers, a fourth insulating film may be formed on the third insulating film. In this case, the fourth insulating film can be formed using the same material as the second insulating film with the same film thickness. The fourth insulating film forms a wiring pattern groove together with the third insulating film.
[0016]
The upper wiring layer of the semiconductor device in the present invention, usually, is not particularly limited as long as it is used as an electrode material, for example, it can be used the same material as the lower wiring layer, Ya contact hole In order to improve the connection in the via hole, a barrier metal may be formed of Ti, TiW, TiN, W or the like. The film thickness at this time can be appropriately adjusted depending on the size of the device to be formed, the depth of the contact hole, and the like, and is preferably about 500 to 2000 mm, for example.
[0017]
Furthermore, according to the method for manufacturing a semiconductor device of the present invention, when connecting the lower wiring layer and the upper wiring layer,
(i) in the lower wiring layer, also forming a small second insulating film etching rate than the first insulating film a first insulating film,
(ii) Considering the shape of the wiring pattern groove to be formed in (iv ) below ,
The opening, as the long axis direction of the opening coincides with a direction orthogonal to the extending direction of the wiring pattern groove, One or
Minor axis direction of said opening, so as to coincide with the extending direction of the wiring pattern grooves, formed in the second insulating film,
(iii) a third insulating film is formed on the second insulating film including the opening,
(iv) by applying a third resist on the insulating film is patterned into a desired shape, the resist as a mask, by etching the third insulating film, the second insulating film on the third insulating film Forming the above-mentioned wiring pattern groove,
Through the opening, said etching the first insulating film under said opening in the wiring pattern grooves, a contact hole reaching the lower wiring layer is formed in a self-aligned manner,
(v) a metal material laminated to the contact hole and on said third insulating film including the wiring pattern groove, with burying the contact hole is patterned to form the upper wiring layer to the wiring pattern groove manufacturing method of the semiconductor device is provided, wherein.
[0018]
In step (i), first, the lower wiring layer described above is formed by a known method, and a first insulating film and a second insulating film having a lower etching rate than the first insulating film are sequentially formed on the lower wiring layer. To do. These insulating films can be formed by a known method such as a CVD method or a plasma CVD method.
Next, in step (ii), an opening is formed in the second insulating film. As this opening has been described above, taking into account the shape of the wiring pattern grooves that would be formed by the following (iv), the direction opening, the long axis direction of the opening, perpendicular to the extending direction of the wiring pattern groove It is formed by a known etching method, for example, a photolithography process, a dry etching method, or the like so as to match and the width of the short axis side of the opening matches the extending direction of the wiring pattern groove .
[0019]
In step (iii), on the second insulating film including an opening formed in step (ii), a third insulating film of the first insulating film and the same material.
In step (iv), a resist is applied on the third insulating film, the upper wiring layer is patterned into a desired shape, and the third insulating film is etched using the resist as a mask. The etching method at this time can be performed by a known method such as RIE, but is preferably performed by dry etching containing a fluorine-based gas. By this dry etching, a wiring pattern groove for forming an upper wiring layer having a desired shape is formed in the third insulating film. At this time, when etching of the third insulating film is completed, further etching is prevented by the etching barrier disposed under the third insulating film, that is, the second insulating film having a low etching rate, so that wiring is performed only on the third insulating film. A pattern groove is formed. In addition, when the third insulating film on the opening formed in the second insulating film is removed by etching, the first insulating film that exists below the opening in the wiring pattern trench is formed through the opening of the second insulating film that becomes an etching barrier. The insulating film is etched. Accordingly, a wiring pattern groove is formed in the third insulating film, and a contact hole that overlaps the wiring pattern groove and reaches the lower layer wiring is formed in a self-aligned manner.
[0020]
In step (v), the contact hole and the wiring pattern groove are sufficiently filled, and a metal material is laminated on the third insulating film. The metal material in this case is a material for forming the wiring layer, and can be formed by a known method such as sputtering, vapor deposition, CVD, ICB or the like. Further, in order to improve the connection between the wiring layers, it is preferable to form a barrier metal or a wiring metal having a thickness of about 1000 to 10000 mm in one layer, two layers, or three layers. Then, the entire surface of the metal material is etched to the upper surface of the third insulating film so as to bury the contact holes formed in the first and second insulating films, and is substantially flush with the upper surface of the third insulating film. An upper wiring layer having an upper surface can be formed. In the case where the interlayer insulating film is formed in a four-layer structure, when the third insulating film is formed, a fourth insulating film made of the same material as the second insulating film is formed, and a wiring pattern is formed on the third insulating film. When the trench is formed, the fourth insulating film can be patterned in the same manner by patterning the fourth insulating film simultaneously with the third insulating film.
[0021]
[Action]
According to the semiconductor device of the present invention, since the interlayer insulating film is formed with a structure of at least three layers having different etching rates, the contact hole is formed in a self-aligned manner with the wiring pattern of the upper wiring layer, It is not necessary to arrange an extra alignment margin, and the sail size can be reduced.
[0022]
Further, as an interlayer insulating film, and a four-layer structure, in the case of forming a small insulating film of the second insulating film and the same etching rate in the fourth layer, when to further connected to a wiring layer thereon an upper wiring layer Can be used effectively. Furthermore, in the past, in consideration of variations in the line width of the wiring layers, a reliable short circuit between the wiring layers was ensured even when misalignment occurred when forming a contact hole for connection between the lower wiring layer and the upper wiring layer. Therefore, an alignment margin was secured. However, according to the method for manufacturing a semiconductor device of the present invention, since an insulating film having a different etching rate is used as an interlayer insulating film in the laminated film, the wiring pattern of the upper wiring layer is formed by the opening formed in the second insulating film. At the same time, a contact hole with the lower wiring layer can be formed in a self-aligning manner. Therefore, it is not necessary to form an extra alignment margin, and the cell size can be reduced.
[0023]
Further, since a wiring pattern is formed only by embedding a metal material that is difficult to be finely processed by dry etching into a wiring pattern groove formed in the third insulating film and etching the entire surface, pattern control is advantageous.
[0024]
【Example】
Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
Example 1
First, as shown in FIG. 1A, after an element isolation oxide film 2 is formed on a silicon substrate 1, a gate electrode 3 having a desired shape is formed. On the silicon substrate 1 including the gate electrode 3, a BPSG film 4 is formed as an interlayer insulating film by atmospheric pressure CVD at about 5000 mm (used gas SiH ₄ 42 sccm, PH ₃ 115 sccm, B ₂ H ₆ 120 sccm, 0 ₂ 1.28 sccm, temperature). 430 ° C.) and about 300 mm of Si ₃ N ₄ film 5 were formed. Thereafter, in the Si ₃ N ₄ film 5, a rectangular opening (size 0.5 × 1.0 μm) was formed in a portion where a contact hole was required. The rectangular opening 6 is patterned so that the long side direction is perpendicular to the longitudinal direction of a metal wiring to be formed later. The patterning is performed by a photolithography process and dry etching (Si ₃ N ₄ film etching conditions: RF power 600 W, gas CF ₄ 480 sccm, pressure 400 Torr, temperature 50 ° C.).
[0025]
Next, as shown in FIG. 1B, a P-SiO ₂ film 7 is formed on the Si ₃ N ₄ film 5 in which the opening 6 is formed by CVD (TEOS / O ₂ = 700 sccm / 650 sccm, power 630 W, pressure 8). About 3000 tons and Si ₃ N ₄ film 8 to about 300 tons by CVD. Then, resist is coated on the silicon substrate 1 including these P-SiO ₂ film 7 and the Si ₃ N ₄ film 8, by a photolithography process, a resist pattern 9 having a desired pattern for the metal interconnect formation.
[0026]
Subsequently, dry etching is performed using the resist pattern 9 as a mask to form contact holes 11 and wiring pattern grooves 10 as shown in FIG. In this dry etching, as a first step, the Si ₃ N ₄ film 8 is etched under the above-mentioned Si ₃ N ₄ film etching conditions, and then, as a second step, the P-SiO ₂ film 7 is etched under the etching conditions (see FIG. Etching is performed with gas C ₄ F ₈ , power 500 W, pressure 5 mTorr, Si ₃ N ₄ / SiO ₂ selectivity 20). Through this series of etching steps, the portion where the wiring pattern groove 10 is formed is etched up to the Si ₃ N ₄ film 5, and the portion where the opening 6 is formed is etched as BPSG and etched as a contact hole 11 reaching the silicon substrate 1. Will be. At this time, since the selection ratio between Si ₃ N ₄ and BPSG is about 20, when etching the BPSG film of about 5000 mm, the Si ₃ N ₄ film 5 is etched about 250 mm, so that about 50 mm remains.
[0027]
Thereafter, as shown in FIG. 1D, metal wirings 12 are formed in the contact holes 11 and the wiring pattern grooves 10. The metal wiring 12 is composed of Ti, TiN, and W. Ti and TiN films are formed by sputtering (Ti film formation conditions: power 2 kW, pressure 10 mTorr, gas Ar 107 sccm, film thickness about 500 mm: TiN film formation conditions; power 5 kW, pressure 3.7 mTorr, gas Ar 25 sccm, N 135 sccm The W film is formed by CVD (conditions: temperature 475 ° C., pressure 80 Torr, gas WF ₆ 75 sccm, H ₂ 50 sccm, film thickness about 5000 mm). Then, the metal wiring 12 is formed by etching back the entire surface (conditions SF ₆ / Ar / He = 140/100/10 sccm, power 625 W, pressure 230 Torr). At this time, the wiring width of the metal wiring 12 is 0.5 μm, and the film thickness is 3000 mm, which is the same as the depth of the wiring pattern groove 10. Further, the Si ₃ N ₄ film 8 is exposed in all the insulating films other than the portion where the metal wiring 12 is formed. At this time, W on the Si ₃ N ₄ film 8 may be removed by using CMP (Chemical Mechanical Polising) instead of the entire surface etch back.
Example 2
As shown in FIG. 2E, a P-SiO ₂ film 13 is formed on the metal wiring 12 which is the first wiring layer formed by the method shown in the first embodiment by about 5000 mm by the same method as described above. Further, a P-SiN film 14 is further formed thereon by about 800 mm (N ₂ 1400 sccm, SiH ₄ 120 sccm, NH ₃ 50 sccm, RF power 420 W, pressure 5.5 Torr). Then, similarly to Example 1, a rectangular (1.0 × 0.5 μm) opening 15 is formed by dry etching.
[0028]
Next, as shown in FIG. 2F, on the P-SiN film 14 including the opening 15, a 5000-thick P-SiO film 16 and about 800-th P-SiN film 17 are formed. Note that the P-SiN films 14 and 17 have a selectivity ratio to SiO ₂ of 10 under the dry etching conditions shown in the first embodiment. Therefore, when the 5000 nm SiO ₂ film is etched, the P-SiN films 14 and 17 are etched by 500 mm. It will be. Therefore, the thickness of the P-SiN films 14 and 17 needs to be about 800 mm thicker than that. Thereafter, a resist is applied on the P-SiN film 17, and a resist pattern 18 having a desired pattern 19 for forming the second metal wiring is formed by a photolithography process.
[0029]
Subsequently, dry etching is performed using the resist pattern 18 as a mask to form self-aligned through holes and wiring pattern grooves as shown in FIG. Then, after a Ti film and a TiN film are formed on the P-SiN film 17 including the contact hole and the wiring pattern groove by a sputtering method, W is coated with about 5000 mm by a CVD method, etched back, and etched. Form.
[0030]
According to the above embodiment, as shown in FIG. 3, even if the opening 15 in the P-SiN film 14 is misaligned with respect to the first metal wiring 12, the portion where the metal wiring 12 is formed. Since the other portions are covered with the Si ₃ N ₄ film 5, etching does not proceed and a through hole having a stable shape can be formed. Even if the wiring pattern of the second metal wiring 20 is misaligned, the opening 15 in the P-SiN film 14 has a rectangular shape, so that the through hole always reaches the first metal wiring 20. It will be.
[0031]
As described above, in the embodiment of the present invention, a through hole having a stable shape can be formed even if misalignment occurs, and a reliable short circuit of the laminated wiring layer can be ensured. In addition, it is possible to further miniaturize the device compared with the conventional device while ensuring an alignment margin in consideration of such misalignment and variation in the line width of the wiring layer. That is, conventionally, as shown in FIG. 5, the second wiring layer 23 formed on the first wiring layer 24 via the insulating film is connected through the contact hole 25. Therefore, when forming a pattern having a layout with a wiring width and wiring interval of 0.5 μm, it is necessary to allow a margin of about 0.25 μm in consideration of misalignment, variation in line width, etc. 1.875 μm ² (1.5 × 1.25) was occupied per (region connecting the centers of the contact holes 25 in the portion closest to the contact hole 25). On the other hand, in the embodiment of the present invention, the occupied area per unit mesh similar to the above can be 1.0 μm ^2, and a reduction of about 53% can be realized.
[0032]
【The invention's effect】
According to the semiconductor device of the present invention, since the interlayer insulating film is formed with a structure of at least three layers having different etching rates, a contact hole is formed in a self-aligned manner with the wiring pattern of the upper wiring layer, and an extra portion is formed. It is not necessary to arrange an alignment margin, and the sail size can be reduced.
[0033]
In addition, when the interlayer insulating film has a four-layer structure and an insulating film having a low etching rate is formed on the fourth layer as in the case of the second insulating film, the upper wiring layer is further connected to the upper wiring layer. Can be used effectively.
Furthermore, according to the method for manufacturing a semiconductor device of the present invention, since an insulating film having a different etching rate is used as an interlayer insulating film in the laminated film, the wiring pattern of the upper wiring layer is formed by the contact hole formed in the second insulating film. At the same time, a contact hole with the lower wiring layer can be formed in a self-aligning manner. Therefore, it is not necessary to form an extra alignment margin, and the cell size can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic process diagram showing a manufacturing process of a semiconductor device of the present invention.
FIG. 2 is a schematic process diagram showing a manufacturing process of a semiconductor device of the present invention.
FIGS. 3A and 3B are a schematic plan view and a schematic cross-sectional view of a main part when an upper layer and a lower wiring layer of a semiconductor device of the present invention are formed. FIGS.
FIG. 4 is a plan view showing the shape of a contact hole of the semiconductor device of the present invention.
FIG. 5 is a schematic plan view of a main part when an upper layer and a lower layer wiring layer of a conventional semiconductor device are formed.
FIG. 6 is a schematic process diagram showing a manufacturing process of a conventional semiconductor device.
FIG. 7 is a schematic process diagram showing a manufacturing process of a conventional semiconductor device.
[Explanation of symbols]
1 silicon substrate 2 element isolation oxide film 3 gate electrode 3
4 BPSG film 5 Si ₃ N ₄ film 6, 15 Opening 7, 13, 16 P-SiO ₂ film 8 Si ₃ N ₄ film 9, 18 Resist pattern 10 Wiring pattern groove 11 Contact hole 1
12, 20 Metal wiring 14, 17 P-SiN film 19 Pattern

Claims (4)

At least the lower wiring layer,
Wherein an interlayer insulating film on the lower wiring layer is connected to the lower wiring layer, and an upper wiring layer having a top surface which forms substantially the same surface as the upper surface of the interlayer insulating film,
The interlayer insulating film, at least a first insulating film,
A second insulating film having an etching rate smaller than that of the first insulating film ;
A third insulating film in this order ,
The second insulating film includes an opening having a major axis and a minor axis penetrating the second insulating film,
The third insulating film includes a wiring pattern groove in which the upper wiring layer is wired,
It said first insulation Enmaku is the previous SL and the opening and the wiring pattern groove comprises a contact hole consisting of only the portion which overlaps in a plan view, and the upper wiring layer and the lower wiring layer and the contact hole Connected through the opening in the overlapping portion in plan view ,
The shape of the opening is
Oite in a direction perpendicular to the extending direction of the wiring pattern groove is greater than the maximum dimension width of the wiring pattern groove and Oite the extending direction of the wiring pattern groove has a maximum dimension the wiring pattern A semiconductor device having a size substantially equal to the width of the groove . The interlayer insulating film is further on the third insulating film, the semiconductor device according to claim 1, characterized in that it has a second fourth insulating film which is formed of the same material as the insulating film. When connecting the lower wiring layer and the upper wiring layer,
(i) in the lower wiring layer, also forming a small second insulating film etching rate than the first insulating film a first insulating film,
(ii) Considering the shape of the wiring pattern groove to be formed in (iv ) below ,
The opening, as the long axis direction of the opening coincides with a direction orthogonal to the extending direction of the wiring pattern groove, One or
Minor axis direction of said opening, so as to coincide with the extending direction of the wiring pattern grooves, formed in the second insulating film,
(iii) a third insulating film is formed on the second insulating film including the opening,
(iv) by applying a third resist on the insulating film is patterned into a desired shape, the resist as a mask, by etching the third insulating film, the second insulating film on the third insulating film Forming the above-mentioned wiring pattern groove,
Through the opening, said etching the first insulating film under said opening in the wiring pattern grooves, a contact hole reaching the lower wiring layer is formed in a self-aligned manner,
(v) a metal material laminated to the contact hole and on said third insulating film including the wiring pattern groove, with burying the contact hole is patterned to form the upper wiring layer to the wiring pattern groove The method of manufacturing a semiconductor device according to claim 1. On the third insulating film, further, the fourth insulating film serving as an etching barrier formed with respect to the third insulating film, by etching the fourth and the third insulating film, the fourth and the second 4. The method of manufacturing a semiconductor device according to claim 3, wherein the wiring pattern groove is formed in the three insulating films.

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