JPH07273188A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To prevent side etching beneath a single crystal layer by setting an insulating film on the main surface of a semiconductor layer thicker than an insulating film on the side wall face. CONSTITUTION:A semiconductor layer formed on an insulating substrate 101 is removed partially using a first patterned insulating film 104 as a mask. A second insulating film is then deposited followed by deposition of an insulating film 103 on the side wall of the semiconductor layer. Thickness B of the insulating film 103 is set thicker than the thickness A of the gate insulating film 104. The thicknesses are preferably set such that B>1.5A. This structure eliminates side etching of the insulating substrate 101 beneath the semiconductor layer and suppresses short circuit between wirings at the time of forming a gate electrode 105 or source-drain electrodes 109, 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a semiconductor layer electrically separated by grooving separation on an insulator surface and a method for manufacturing the same.

[0002]

2. Description of the Related Art A technique for forming a single crystal silicon semiconductor layer on an insulator is widely known as an SOI technique. By forming a semiconductor device using an SOI substrate, high integration (miniaturization), high speed (capacitance reduction), high breakdown voltage, latchup resistance (element isolation), cosmic ray resistance, etc. are excellent. It is also confirmed that the characteristics can be obtained. On the other hand, in order to further increase the degree of integration, as a method for element isolation, studies have been conducted from the isolation method by selective oxidation to mesa isolation or trench isolation.

[0003]

When the semiconductor layer on the insulator is to be separated by etching in order to manufacture a semiconductor element such as a MOS transistor on the SOI substrate, the following problems occur.

That is, as shown in FIG.
When the semiconductor layer 202 formed on 1 is etched using the patterned thermal oxide film 203 as a mask, when the thermal oxide film 203 serving as a mask is removed after etching, it is exposed as shown in FIG. Insulating substrate 2
The surface of 01 is also etched, and the semiconductor layer 202
There is a problem that the side-etched portion 205 is generated on the lower side, and the conductor 208 enters the side-etched portion due to the gate electrode 207 on the insulating film 206 and other wiring forming steps as shown in FIG.

[0005]

A semiconductor device of the present invention is a semiconductor layer provided on an insulator surface and electrically separated by trench isolation, and an insulating film provided on the semiconductor layer. In the semiconductor device having, the thickness of the insulating film on the side wall surface is larger than the thickness of the insulating film on the main surface of the semiconductor layer.

According to the method of manufacturing a semiconductor device of the present invention, a patterned first insulating film is formed on a semiconductor layer provided on an insulator surface, and the semiconductor layer is formed using the first insulating film as a mask. A step of partially removing, a step of further forming a second insulating film on the first insulating film and the semiconductor layer, and a step of differentiating at least the first and second insulating films on the main surface of the semiconductor layer. And a step of removing by means of isotropic etching.

According to the method for manufacturing a semiconductor device of the present invention, a patterned first oxide film and an oxidation resistant film are formed on a semiconductor layer provided on an insulator surface, and the oxidation resistant film is used as a mask. The method is characterized by including a step of partially removing the semiconductor layer, a step of forming a second oxide film on at least a sidewall surface of the semiconductor layer, and a step of removing at least the oxidation resistant film.

[0008]

The semiconductor device of the present invention prevents side etching under the single crystal layer by making the thickness of the insulating film on the side wall surface thicker than the thickness of the insulating film on the main surface of the semiconductor layer. Therefore, it is possible to suppress a short circuit between the wirings when the wirings are formed on the insulating film.

According to the method of manufacturing a semiconductor device of the present invention, the semiconductor layer provided on the insulator surface is partially removed by using the patterned first insulating film as a mask, and then the second insulating film is further formed. By forming the insulating film also on the sidewall portion of the semiconductor layer to prevent the insulating surface under the semiconductor layer from being etched in the subsequent etching process, and thereafter, at least the first and second insulating films on the main surface of the semiconductor layer are formed. The insulating film is removed by anisotropic etching.

In the method for manufacturing a semiconductor device of the present invention, the semiconductor layer provided on the insulating surface is partially removed by using the patterned oxidation resistant film as a mask, and then covered with the oxidation resistant film. By forming a second oxide film on at least the side wall surface of the semiconductor layer which is not exposed, an insulating film is also formed on the side wall portion of the semiconductor layer so that the insulating surface under the semiconductor layer is not etched in the subsequent etching process. After that, the oxidation resistant film is removed.

The above-mentioned manufacturing method of the present invention is one in which the insulator under the semiconductor layer is not side-etched by using the conventional technique such as the trench isolation method or the selective oxidation method, and a particularly novel device is introduced. Without doing so, it is possible to provide an inexpensive SOI type semiconductor device with small variations.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings. Note that, here, a case where a MOS transistor is formed on an SOI substrate will be described as an example. (Embodiment 1) FIG. 1 is a schematic sectional view of an SOI type MOS transistor according to the present invention. In the figure, 101 is an insulating substrate, 102 is a region of a semiconductor layer that serves as a channel portion of a MOS transistor, 103 is a thick insulating film, 104 is a gate insulating film, 105 is a gate electrode and wiring of a MOS transistor, and 106 and 107 are. Source and drain regions of the MOS transistor formed in the semiconductor layer, 108 is an interlayer insulating film, and 109 and 110 are extraction electrodes and wirings of the source and drain regions. The insulating substrate 101
The substrate itself may be an insulator or a substrate in which an insulating layer is formed on a non-insulator substrate. In the present invention, various SOI substrates such as a bonded substrate, SIMOX, SOS and the like can be used.

The feature of the present invention is that the gate insulating film 1 is formed.
04 insulating film thickness (A) and insulating film 103 insulating film thickness (B)
Is that A <B. That is, by making the insulating film thickness B larger than the insulating film thickness A, side etching is prevented from occurring in the insulating substrate 101 below the semiconductor layer. As a result, the gate electrode 105
It is possible to suppress a short circuit between wirings that occurs when the source / drain electrodes 109 and 110 are formed. When the insulating film (A) is etched, 50% over-etching is performed in consideration of the stabilization of the process. Therefore, the insulating film thickness is preferably B> 1.5A. Also, MO
Considering the Vth fluctuation of the S transistor, V on the main surface side
In order to determine th, it is desirable to have a good-quality insulating film of 1.5 times or more on the side wall surface.

Next, a method of manufacturing the SOI type MOS transistor will be described. First, as shown in FIG. 2, a thermal oxide film 3 as a mask material is obtained by thermally oxidizing a substrate having a silicon single crystal layer 302 provided on an insulating substrate 301.
Form 03. Subsequently, an oxide film is etched by resist patterning so as to leave an oxide film only in a region where an element (transistor or the like) is formed, and then the resist is removed. Using this oxide film as a mask material, the single crystal layer 3
02 is partially removed by etching. When etching, the selection ratio between the oxide film and the silicon single crystal layer should be taken into consideration. However, if the chlorine-based gas 304 is used and the etching is performed anisotropically in the RIE mode, the selection ratio can be about 5 to 10.
If the thickness of the single crystal layer is about 5000 Å, a thermal oxide film as a mask material of about 1000 Å is sufficient.

Next, as shown in FIG. 3, an insulating film 305 is formed on the entire surface of the substrate by using the CVD method or the like. continue,
The insulating film 305 is removed again by etching in the RIE mode. In this case, it should be noted that the etching rate of the insulating film is higher than that of the semiconductor layer, contrary to the above-mentioned etching. This includes CHF ₃ , CF
By using the fluorine-based etchant 306 such as ₄ , SF ₆ or the like, a selection ratio of about 30 can be obtained. In this way, it becomes possible to leave the thick insulating film 307 on the sidewall of the semiconductor layer, which is a feature of the present invention, as shown in FIG.

Thereafter, as shown in FIG. 5, a gate oxide film 308 is formed, polycrystalline silicon to be the gate electrode 309 is formed on the entire surface, and this is patterned to form polycrystalline silicon only when desired. It is possible to leave. Then, using this polycrystalline silicon as a mask, source / drain ion implantation is performed by self-alignment.
The dose of ions and the acceleration voltage are controlled so that the amount of ion implantation is 1E19 cm ⁻³ or more as the surface concentration.

Next, as shown in FIG. 6, an interlayer insulating film 312 is formed.
As a process, a BPSG film is formed by the CVD method and this is heat-treated. By this heat treatment, the ion-implanted layers (source / drain) are electrically activated, and the BPSG film is fluidized (reflowed) to reduce steps. In the figure, 310, 3
Reference numeral 11 is a source / drain region. Then, a window for leading out an electrode is formed in this insulating film. Finally, a metal such as Al is formed on the entire surface by a sputtering method, and this is patterned to form wirings 313 and 312.
A transistor is formed. After that, a heat treatment at about 400 ° C. is performed, so that characteristics having good ohmic contact and no short circuit between wirings can be obtained. In this embodiment, MOS
Although the transistor has been described, the same effect can be expected for a bipolar transistor. (Embodiment 2) In Embodiment 1, the present invention is realized by forming a sidewall, but in this embodiment, the present invention is realized by a selective oxidation method.

As shown in FIG. 7, a substrate provided with a silicon single crystal 402 on an insulating substrate 401 is thermally oxidized to form an oxide film 403, and then a nitride film 404 is formed by using LP-CVD. To do. Next, the nitride film 404 and the oxide film 403 are etched by resist patterning. Subsequently, the single crystal layer 402 is formed by using the nitride film 404 as a mask.
Are removed by etching using chlorine-based plasma 405. Here, it should be noted that the point is to form a thick nitride film so that the nitride film 404 remains up to 1000 angstroms even after the etching of the single crystal layer 402 is completed.

Next, as shown in FIG. 8, by thermally oxidizing this, a portion without the nitride film 404 is selectively oxidized, and a thick oxide film 406 can be formed only on the side wall of the single crystal layer. Become.

Thereafter, as shown in FIG. 9, the nitride film 404 is selectively removed by hot phosphoric acid to remove the oxide film 4 on the side wall.
It is possible to remove the nitride film while leaving 06. Finally, the oxide film (up to 300 Å) 403 formed for controlling the nitride film stress is removed, so that a thick insulating film can be left on the side wall of the semiconductor layer, which is a feature of the present invention. After this, as in the first embodiment, MO
It is possible to form a transistor such as an S transistor.

[0021]

As described above, according to the present invention, by making the insulating film on the side wall of the semiconductor layer thicker than the insulating film on the main surface, it is possible to suppress a short circuit between wirings.

Further, according to the present invention, the influence of the side wall of the semiconductor layer when forming a semiconductor element can be reduced. For example, in the MOS transistor according to the present invention, the influence of the side wall can be greatly reduced. FIG. 10 shows the dependence of the threshold voltage Vth of the MOS transistor on the W (gate width) when the present invention is used and when the conventional method is used. Although it affects the thickness of the semiconductor layer, when the semiconductor layer thickness is up to 5000 angstroms, Vth is W ≦ 20 μm in the conventional method.
Is observed, but when the present invention is used, W to 3 μm
It can be seen that Vth does not change up to. FIG. 11 shows the W dependence of the yield of the 500-stage shift register to which the present invention is applied. According to the present invention, the yield is improved, and particularly when W <10 μm, the effect of the improvement is remarkable. This means that there are more degrees of freedom in performing circuit calculations, etc.
It is important for improving performance.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an SOI type MOS transistor according to the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the SOI-type MOS transistor according to the second embodiment of the present invention.

FIG. 10 is a characteristic diagram showing W dependence of a MOS transistor to which the present invention is applied.

FIG. 11 is a characteristic diagram showing the W dependence of the yield of a 500-stage shift register to which the present invention is applied.

FIG. 12 is a cross-sectional view showing the manufacturing method when trench isolation is applied to the SOI substrate.

FIG. 13 is a cross-sectional view showing the manufacturing method when trench isolation is applied to the SOI substrate.

FIG. 14 is a cross-sectional view showing the manufacturing method when trench isolation is applied to the SOI substrate.

[Explanation of symbols]

101 Insulating Substrate 102 Region That Becomes Channel Portion of MOS Transistor 103 Thick Insulating Film 104 Gate Insulating Film 105 Gate Electrodes and Wirings 106, 107 Source / Drain Regions 108 Interlayer Insulating Films 109, 110 Extraction Electrodes and Wirings of Source and Drain Regions 301 Insulating substrate 302 Silicon single crystal layer 303 Thermal oxide film 304 Chlorine-based gas 305 Insulating film 306 Fluorine-based etchant 307 Thick insulating film 308 Gate oxide film 309 Gate electrode 310 Source region 311 Drain region 312 Interlayer insulating film (BPSG film) 313 Wiring 314 wiring 401 insulating substrate 402 silicon single crystal 403 oxide film 404 nitride film 405 plasma etching (chlorine gas) 406 thick oxide film

Claims (6)

[Claims] 1. A semiconductor device comprising a semiconductor layer provided on an insulator surface and electrically separated by trench isolation, and an insulating film provided on the semiconductor layer, comprising: A semiconductor device, wherein the thickness of the insulating film on the side wall surface is larger than the thickness of the insulating film on the main surface. 2. The semiconductor device according to claim 1, wherein the insulating film on the side wall surface is a thermal oxide film. 3. The semiconductor device according to claim 1, wherein the thickness of the insulating film on the side wall surface is 1.5 times or more the thickness of the insulating film on the main surface. 4. The semiconductor device according to claim 1, wherein a source / drain region is provided in the semiconductor layer, and a gate electrode is provided on an insulating film on a main surface of the semiconductor layer to form an insulated gate transistor. 5. A step of forming a patterned first insulating film on a semiconductor layer provided on an insulator surface, and partially removing the semiconductor layer using the first insulating film as a mask, Forming a second insulating film on the first insulating film and the semiconductor layer; and removing at least the first and second insulating films on the main surface of the semiconductor layer by anisotropic etching. A method for manufacturing a semiconductor device, comprising: 6. A patterned first oxide film and an oxidation resistant film are formed on a semiconductor layer provided on an insulator surface,
A step of partially removing the semiconductor layer using the oxidation resistant film as a mask; a step of forming a second oxide film on at least a sidewall surface of the semiconductor layer; a step of removing at least the oxidation resistant film; And a method for manufacturing a semiconductor device having the same.