JP2002368211A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce mechanical stresses applied to a semiconductor device, which has a flank structure including a silicon nitride film and is of <=0.14 μm in gate length. SOLUTION: This semiconductor device has on a silicon substrate 1 a gate electrode 5, which is formed while insulated from the substrate 1 and of <=0.14 μm in gate length and a sidewall 15, including a laminated structure of a silicon oxide film 9 which, is formed from the substrate 1 to the sidewall of the gate electrode 5, a silicon nitride film 11 which is formed on the silicon oxide film 9, and a silicon oxide film 13 which is formed on the silicon nitride film 11. Here, the ratio 'TSi O2 /TSi N' of the film thickness TSi O2 of the silicon oxide film 9 and the film thickness TSi N of the silicon nitride film is set >=0.5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOSFE having a sidewall insulating film on a gate sidewall.
About T.

[0002]

2. Description of the Related Art Conventionally, in MOSFETs, in order to ensure high breakdown voltage reliability and to suppress short channel effects,
LDD structures have been applied. In order to make the MOSFET have the LDD structure, a side wall is formed on the side wall of the gate electrode.

In recent years, in order to reduce the resistance of a gate electrode, a source region and a drain region, a so-called “salicide process” in which a silicide layer is formed in a self-aligned manner on a gate electrode, a source region and a drain region. A technology called is becoming essential.

When the "salicide process" is used, the side wall is required to be etched and retreated in a pretreatment before passing through the salicide process, that is, a hydrofluoric acid treatment for removing a natural oxide film and the like from the silicon surface. That is not to do. Therefore, a structure including a silicon nitride film whose etching rate by hydrofluoric acid is slower than that of a silicon oxide film is often used for the side wall. A sidewall structure including such a silicon nitride film is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-1960.
71 publication.

[0005]

In a MOSFET having a sidewall structure including a silicon nitride film, when the gate length Lg is reduced to 0.14 μm or less, the MOSF
The reliability of ET, such as hot carrier resistance, has become extremely poor.

The present inventor has proposed a semiconductor device such as a MOS device.
The mechanical stress applied to the FET, in particular, the mechanical stress applied near the interface between the gate oxide film and the substrate and the MOSF
We found that there is a correlation between the various reliability characteristics of ET.

FIG. 12 is a diagram showing distribution of mechanical stress applied to a MOSFET having a sidewall structure including a silicon nitride film.

As shown in FIG. 12, a silicon nitride film (Si
In a MOSFET with a sidewall structure containing (N), mechanical stress is concentrated from the center of the gate electrode (GATE) to the gate oxide film (GATE OXIDE), and further to the vicinity of the interface between the gate oxide film and the substrate. .

FIG. 13 shows the mechanical stress (Stress) applied to the vicinity of the interface between the gate oxide film and the substrate, and the values before and after the acceleration test.
FIG. 14 is a diagram illustrating a relationship with a later change amount (ΔIdsat / Idsat) of a drain saturation current.

In this accelerated test, for 3000 seconds,
Each of the gate voltage Vg and the drain voltage Vd is -2.0
An electric stress was applied to the MOSFET as V. In the drawing, “Idsat” is the amount of drain saturation current before the application of electrical stress, and “Δ (Idsat)” is the amount of change (reduction amount) of the drain saturation current after application of the electrical stress. Is shown.

As shown in FIG. 13, the greater the mechanical stress applied to the vicinity of the interface between the gate oxide film and the substrate, the greater the change (ΔIdsat / Idsat) in the drain saturation current. The amount of change (ΔIdsat / Idsat) is
The larger the amount of change, the more the hot carrier resistance is degraded.

Conventionally, an MO having a sidewall structure including a nitride film
In the SFET, no particular consideration is given to mechanical stress applied to the vicinity of the interface between the gate oxide film and the substrate. Therefore, when the gate length Lg is reduced to 0.14 μm or less, for example, 0.11 μm or less, the MOSFET
The control of the reliability of the equipment becomes strict.

The present invention has been made in view of the above circumstances, and has as its object to reduce the mechanical stress applied to a semiconductor device in a semiconductor device having a sidewall structure including a nitride film, thereby reducing reliability. An object of the present invention is to provide a semiconductor device capable of suppressing the above.

[0014]

In order to achieve the above object, according to the present invention, there is provided a semiconductor substrate, comprising: a semiconductor substrate formed on the semiconductor substrate;
a gate electrode having a gate length Lg of not more than μm, a first oxide film formed on the semiconductor substrate and on a side wall of the gate electrode having a gate length Lg of not more than 0.14 μm, and on the first oxide film And a side wall including a stacked structure of a second oxide film formed on the nitride film. Then, the thickness Tox of the first oxide film
The ratio “Tox / Tni” between the thickness of the nitride film and the film thickness Tni is set to 0.
It is characterized in that it is 5 or more.

Further, a semiconductor substrate, and 0.14 formed on the semiconductor substrate insulated from the semiconductor substrate.
a gate electrode having a gate length Lg of not more than .mu.m, a nitride film formed on the semiconductor substrate to a side wall of the gate electrode having a gate length Lg of not more than 0.14 .mu.m, and an oxide film formed on the nitride film. And a side wall including a layered structure of the film. The nitride film has a thickness of 10 nm or less.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 1 shows a MOS device as an example of a semiconductor device.
An FET is shown. On the N-type silicon substrate 1 (or N-type well), a gate oxide film 3 is formed. Gate oxide film 3 is made of, for example, silicon dioxide. On the gate oxide film 3, a gate electrode 5 is formed. Gate electrode 5 is made of, for example, conductive polysilicon.
In this example, the gate length Lg of the gate electrode 5 is about 0.11.
It is set to μm. In the N-type silicon substrate 1, a P-type electrode formed by using the gate electrode 5 as a mask for ion implantation is formed.
^- -type extension layer 7 is formed. The P ⁻ -type extension layer 7 is made of a so-called LDD (Lightly Doped D
rain) to form a structure.

An oxide film 9 is formed on the N-type silicon substrate 1 and on the side wall of the gate electrode 5. Oxide film 9 is made of, for example, silicon dioxide. One specific example of this silicon dioxide is tetraethoxysilane (TE
OS-) CVD-silicon dioxide deposited using a gas. In this example, the thickness T _SiO2 of the oxide film 9 is set to about 20 nm.

On oxide film 9, a nitride film 11 is formed. The nitride film 11 is made of, for example, silicon nitride. In this example, the thickness T _SiN of the nitride film 11 is set to the same thickness as the underlying oxide film 9, that is, about 20 nm. This allows
The ratio “T _SiO2 / T _SiN ” between the thickness T _SiO2 of the oxide film 9 and the thickness T _SiN of the nitride film 11 is about 1.0.

An oxide film 13 is formed on nitride film 11. Oxide film 13 is made of, for example, silicon dioxide. These oxide film 13, nitride film 11, and oxide film 9
The side wall 15 is formed.

FIG. 2 shows the thickness of the oxide film 9 (TEOS thickness).
FIG. 3 is a diagram showing a relationship between the mechanical stress and mechanical stress.

In FIG. 2, specifically, the thickness T _SiN of the nitride film 11 is 20 nm (Nitride = 20 nm) and 15 nm (Nitride = 15 nm).
nm), 10nm (Nitride = 10nm) MOSFET
And the thickness T _SiO2 of the oxide film 9 is set to 0 nm, respectively.
(That is, a structure without the oxide film 9), 10 nm, 20 nm, 3
This shows the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 when the thickness is changed to 0 nm.

As shown in FIG. 2, mechanical stress applied near the interface between the gate oxide film 3 and the substrate 1 is reduced by the oxide film 9.
It has been found that the thickness can be reduced by providing and increasing the thickness T _SiO2 .

For example, the thickness T _{SiN of the} nitride film 11 is 20 nm.
In the MOSFET having no oxide film 9, the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 is about 55 MPa.

On the other hand, when the oxide film 9 having a thickness T _SiO2 of 10 nm is provided, the mechanical stress is reduced to about 43 MPa (T _SiO2 / T _SiN = 10 nm / 20 nm = 0.5).

When the thickness T _SiO2 of the oxide film 9 is further increased to 20 nm, the thickness T _SiO2 is also reduced to about 33 MPa (T _SiO2 / T _SiN
= 20 nm / 20 nm = 1.0).

If the thickness T _SiO2 of the oxide film 9 is further increased to 30 nm, the thickness T _SiO2 is also reduced to about 25 MPa (T _SiO2 / T _SiN
= 30 nm / 20 nm = 1.5).

If the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 is reduced, for example, as shown in FIG.
(ΔIdsat / Idsat) becomes smaller, and the hot carrier resistance of the MOSFET becomes better.

Further, if the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 is reduced, not only the hot carrier resistance but also other reliability-related characteristics are improved.

FIG. 3A shows the time to failure (Time To Failu).
re) and the cumulative probability (Cumulative Probability). FIG. 3B shows the drain current (Idr) and the failure arrival time.
It is a figure which shows the relationship with (TimeTo Failure).

In FIG. 3A and FIG. 3B, “A” is an integrated circuit having a MOSFET with a mechanical stress of about 43 MPa applied near the interface between the gate oxide film 3 and the substrate 1. B "is an integrated circuit having a MOSFET also subjected to a mechanical stress of about 55 MPa, and" C "is a MOSF also subjected to a mechanical stress of about 33 MPa.
It is an integrated circuit having ET.

FIG. 3A shows that the film thickness (Tox) is 2.5 nm,
This is a plot of the time required to reach insulation failure when an electric field of 11 MV / cm is applied at 85 ° C. to the gate oxide film 3 having an area of 0.125 μm ² . This characteristic indicates that the insulation failure is less likely to occur in the direction of the arrow in FIG.

As shown in FIG. 3A, the gate oxide film 3
It has been found that as the mechanical stress applied near the interface between the substrate and the substrate 1 is smaller, insulation failure is less likely to occur and the durability of the integrated circuit is improved.

FIG. 3B also shows the characteristic relating to the durability of the integrated circuit, similarly to FIG. 3A. When the integrated circuit is continuously operated at a normal power supply voltage, the change ΔIdsat of the drain saturation current is obtained. Represents the time to reach 5%. This characteristic indicates that the drain saturation current becomes more difficult to change in the direction of the arrow in FIG.

As shown in FIG. 3B, the gate oxide film 3
As the mechanical stress applied near the interface between the substrate and the substrate 1 is smaller, the drain saturation current is less likely to change, and the durability of the integrated circuit is improved.

As described above, by reducing the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1,
A decrease in the reliability of the MOSFET can be suppressed. As a result, its reliability can be improved. The mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 can be reduced by providing the oxide film 9 under the nitride film 11. Therefore, by providing the oxide film 9 below the nitride film 11, the reliability of the MOSFET can be improved.

Further, based on the relationship shown in FIG.
It can be seen that the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 can also be reduced by reducing the film thickness T _SiN of FIG.

For example, the thickness T _{SiN of the} nitride film 11 is 10 nm.
In the MOSFET described above, even without the oxide film 9, the mechanical stress applied near the interface between the gate oxide film 3 and the substrate 1 is reduced to about 38 MPa. About 38 MPa is "T _SiO2
The mechanical stress applied to the MOSFET of / T _SiN = 10 nm / 20 nm = 0.5 ″ is smaller than about 43 MPa. That is, if the nitride film 11 has a thickness T _{SiN of} 10 nm or less, the same as above. The effect can be expected.

Of course, the thickness T _SiN of the nitride film 11 is set to 10
nm or less, and an oxide film 9 is further formed under the nitride film 11.
Is provided, the above effect can be further improved.

In a MOSFET having a side wall structure including a silicon nitride film, the gate length Lg is 0.1
It has been found that when the size is reduced to 4 μm or less, the reliability of the MOSFET, for example, the hot carrier resistance, is extremely deteriorated.

FIG. 4 is a diagram showing the relationship between the gate length (GATE length) and the amount of change (ΔIdsat / Idsat) of the drain saturation current before and after the acceleration test.

As shown in FIG. 4, the gate length Lg is 0.1
Up to about 4 μm, the change amount (ΔIdsat / Idsat) of the drain saturation current before / after the accelerated test does not change much, but when the gate length Lg becomes 0.14 μm or less, the change amount (ΔIds
at / Idsat) changes significantly.

This is presumably because as the gate length Lg decreases, the force applied from the nitride film formed on the side wall of the gate electrode has a greater effect.

FIGS. 5A to 5E respectively show MOS transistors.
FIG. 3 is a cross-sectional view showing an FET for each gate length.

As shown in FIGS. 5A to 5E, when the gate length Lg decreases, the size of the gate electrode 5 sandwiched between the nitride films 11 decreases. For this reason, a region including the interface between the gate oxide film 3 and the substrate 1 is narrowed, and mechanical stress is more likely to be concentrated near the interface between the gate oxide film 3 and the substrate 1.

From the results shown in FIG. 4, it is assumed that the gate length Lg is about 0.14 μm or that the ratio “Tg / Lg” of the gate electrode thickness Tg to the gate length Lg is about 1.42 as a critical point Is extremely unreliable.

Therefore, the present invention is particularly applicable to the gate length L
This is particularly effective when applied to a MOSFET having a g of 0.14 μm or less, or a MOSFET having a ratio “Tg / Lg” of the gate electrode thickness Tg to the gate length Lg of 1.42 or more.

The thickness T _SiO2 of the oxide film 9 and the nitride film 11
The ratio of the film thickness T _SiN to “T _SiO2 / T _SiN i” and the MOSFET
We also investigated the relationship with the credibility.

FIG. 6 shows the thickness T _SiO2 of the oxide film 9 and the nitride film 1.
FIG. 3 is a diagram showing a relationship between a ratio of a film thickness T _{SiN of} No. 1 to an average dielectric breakdown time (average TDDB).

As shown in FIG. 6, when the ratio “T _SiO2 / T _SiN ” becomes 0.5 or more, the average time to dielectric breakdown rapidly increases.

FIG. 7 also shows the relationship between the ratio between the thickness T _SiO2 of the oxide film 9 and the thickness T _SiN of the nitride film 11 and the amount of change in drain saturation current (ΔIdsat / Idsat) before and after the acceleration test. FIG.

As shown in FIG. 7, similarly, the amount of change in the drain saturation current sharply decreases when the ratio "T _SiO2 / T _SiN " becomes 0.5 or more.

From these findings, the thickness T _{SiO2 of the} oxide film 9
It has been found that the ratio between the thickness and the thickness T _SiN of the nitride film 11 is preferably set to 0.5 or more in order to suppress a decrease in reliability.

FIGS. 8A to 8D show the MOs, respectively.
The SFET is formed by forming the film thickness T _SiO2 of the oxide film 9 and the film thickness T of the nitride film 11.
FIG. 3 is a cross-sectional view showing the ratio with _respect to _SiN .

FIG. 8A shows that the ratio "T _SiO2 / T _SiN " is equal to 0.
25 MOSFETs. In this MOSFET, the thickness T _SiN is four times the thickness T _SiO2 , and the nitride film 11 is sufficiently thicker than the oxide film 9.

FIG. 8B shows that the ratio “T _SiO2 / T _SiN ” is 0.
5 MOSFET. In this MOSFET, the film thickness T _SiN is twice the film thickness T _SiO2 .

FIG. 8C shows that the ratio "T _SiO2 / T _SiN " is 1.
0 MOSFET. In this MOSFET, the film thickness T _SiN and the film thickness T _SiO2 are equal to each other.

FIG. 8D shows that the ratio “T _SiO2 / T _SiN ” is 2.
0 MOSFET. In this MOSFET, the thickness T _SiN is half of the thickness T _SiO2 , and the nitride film 11 is thinner than the oxide film 9.

According to the findings shown in FIGS. 6 and 7, in order to suppress a decrease in reliability, as shown in FIG. FIG. 8
The structures shown in FIGS. 8B to 8D are more preferable.

The MOSFE according to the first embodiment as described above
According to T, a gate electrode having a gate length Lg of 0.14 μm or less and a side wall 15 including a stacked structure of an oxide film 9, a nitride film 11, and an oxide film 13 are provided. Mechanical stress applied to the vicinity of the interface with the substrate can be reduced.

More preferably, the thickness T _{SiO2 of the} oxide film 9
By setting the ratio “T _SiO2 / T _SiN ” between the gate oxide film 3 and the substrate 1 to a thickness T _SiN of the nitride film 11 and the thickness T _SiN of 0.5 or more,
The mechanical stress applied to the vicinity of the interface can be further reduced.

As described above, the mechanical stress applied to the vicinity of the interface between the gate oxide film 3 and the substrate 1 can be reduced.
It is possible to suppress a decrease in characteristics related to the reliability of the OSFET, for example, hot carrier resistance, dielectric breakdown resistance, and the like. Further, it is also possible to improve these reliability-related characteristics.

(Second Embodiment) Next, an example of a specific MOSFET to which the present invention is applied will be described together with an example of its manufacturing method.

FIGS. 9 (A) to 9 (D) and FIGS. 10 (A) to 10 (A)
FIG. 10D is a sectional view showing a MOSFET according to a second embodiment of the present invention in each of main manufacturing steps.
FIG. 1 is a sectional view showing a MOSFET according to a second embodiment of the present invention.

First, as shown in FIG. 9A, the surface of an N-type silicon substrate (or N-type well) 1 is thermally oxidized, for example, to form a gate oxide film 3 having a thickness of, for example, about 2.5 nm.
To form Next, conductive polysilicon is deposited on the gate oxide film 3 to form a conductive polysilicon film having a thickness Tg of about 0.2 μm, for example. Next, the conductive polysilicon film and the gate oxide film 3 are patterned,
For example, a gate electrode 5 having a gate length Lg of about 0.11 μm is formed. Thereafter, if necessary, the surface of the N-type silicon substrate 1 and the surface of the gate electrode 5 are thinly thermally oxidized, that is, post-oxidized.

Next, as shown in FIG. 9B, P-type impurity ions, for example, boron ions are implanted shallowly at a low acceleration voltage into the N-type silicon substrate 1 using the gate electrode 5 as a mask. This is an ion implantation step for forming the P ⁻ type extension layer 7.

Next, as shown in FIG. 9C, silicon dioxide is deposited from the N-type silicon substrate 1 to the side wall of the gate electrode 5 to form an oxide film 9 having a thickness T _SiO2 of, for example, about 20 nm. Form. The oxide film 9 is desirably formed by a CVD method using tetraethoxysilane (TEOS) as a source gas. The CVD method using tetraethoxysilane as a source gas has excellent step coverage,
Oxide film 9 can be formed from N-type silicon substrate 1 to the side wall of gate electrode 5 without any step. Oxide film 9 can also be formed by thickly thermally oxidizing the surface of N-type silicon substrate 1 and the surface of gate electrode 5. However, the oxide film 9 is preferably formed by deposition rather than thermal oxidation. This is because if the surface of the N-type silicon substrate 1 is thermally oxidized to a large thickness, the oxide film 9 may be formed deeper than the junction depth of the P ⁻ -type extension layer 7. Next, silicon nitride is deposited on the oxide film 9 to form a nitride film 11 having a thickness T _SiN of, for example, about 20 nm. Then, depositing a silicon dioxide on the nitride film 11, to form an oxide film 13 having for example a thickness T2 _SiO2 of about 60 nm. The thickness T2 _SiO2 of the oxide film 13 is
It is set to match the final width of the side wall.

Next, as shown in FIG.
3, the nitride film 11 and the oxide film 9 are etched using an anisotropic dry etching method, and the oxide film 13 and the nitride film 1 are etched.
1 and a sidewall 15 including a stacked structure of the oxide film 9 is formed. In the anisotropic dry etching for forming the side wall 15, the etchants may be switched when the oxide films 13 and 9 are etched and when the nitride film 11 is etched. However, the oxide films 13 and 9
It is preferable that the etchant is not switched between the etching of the nitride film 11 and the etching of the nitride film 11 and the etching is continuously performed using an etchant having a small difference in etching rate between the oxide films 13 and 9 and the nitride film 11. This is because when the etchant is switched, the shape of the side wall 15 tends to be distorted. By successively etching the oxide film 13, the nitride film 11, and the oxide film 9 without switching the etchant, the sidewall 15 having a good shape can be formed as shown in FIG. 9D.

Next, as shown in FIG. 10A, P-type impurity ions, for example, boron ions are implanted into the N-type silicon substrate 1 using the gate electrode 5 and the side walls 15 as a mask. This is an ion implantation process for forming the P ⁺ type source / drain regions 17.

Next, as shown in FIG.
The structure shown in (A) is treated with hydrofluoric acid, and an N-type silicon substrate 1
The natural oxide film existing on the gate electrode 5 is removed. Next, a refractory metal is deposited from the N-type silicon substrate 1 to the sidewalls 15 and the upper surface of the gate electrode 5 to form a refractory metal film 19. The refractory metal may react with silicon to form a silicide layer having a lower resistance than silicon.

Next, as shown in FIG. 10C, for example, heat treatment is performed to cause the high melting point metal film 19 to react with silicon,
The surface portions of the ⁺ type source / drain region 17 and the gate electrode 5 are silicided.

Next, as shown in FIG. 10D, a portion of the high melting point metal film 19 that has not reacted with silicon is removed. Thereby, the silicide layer 21 is formed in the P ⁺ type source / drain region 17 and the gate electrode 5 in a self-aligned manner.

Next, as shown in FIG. 11, FIG.
A contact hole 25 reaching the silicide layer 21 is formed in the interlayer insulating film 23, and the silicide layer 21 is electrically connected to the silicide layer 21 through the contact hole 25 on the interlayer insulating film 23. By forming the contacting wiring layer 27, the P-channel MOSFET according to the second embodiment of the present invention is completed.

Also in the second embodiment, the thickness T _SiO2 of the oxide film 9 is 20 nm and the thickness T _{SiN of the} nitride film 11 is 20 nm.
Is 20 nm, and the ratio “T _SiO2 / T _SiN ” is 1.0. That is, the ratio "T _SiO2 / T _SiN " satisfies 0.5 or more. Therefore, similarly to the first embodiment, mechanical stress applied near the interface between the gate oxide film 3 and the N-type silicon substrate 1 can be reduced.

As described above, the present invention has been described with reference to the first and second embodiments. However, the present invention is not limited to each of these embodiments, and various modifications may be made without departing from the spirit of the invention. It is possible to transform to

Although the first and second embodiments can be implemented independently, they can of course be implemented in appropriate combinations.

Further, the first and second embodiments include inventions of various stages, and the invention of various stages is extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment. It is also possible.

[0079]

As described above, according to the present invention, in a semiconductor device having a sidewall structure including a nitride film, a semiconductor stress which can reduce the mechanical stress applied to the semiconductor device and can suppress a decrease in reliability. An apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a MOSF according to a first embodiment of the present invention;
Sectional drawing which shows ET.

FIG. 2 is a diagram showing a relationship between an oxide film thickness (TEOS thickness) and mechanical stress (Stress).

FIG. 3 (A) is a failure arrival time (Time To Failure).
FIG. 3B is a graph showing the relationship between the cumulative probability (Cumulative Probability) and the drain current (Idr) and the failure arrival time (Ti
FIG.

FIG. 4 shows the gate length (GATE length) and before the acceleration test /
FIG. 14 is a diagram showing a relationship with a change amount (ΔIdsat / Idsat) of a drain saturation current later.

FIGS. 5A to 5E show MOSFEs, respectively.
Sectional drawing which showed T for every gate length.

FIG. 6 is a graph showing the ratio of the thickness of the oxide film to the thickness of the nitride film (T
_The figure which shows the relationship between ( _SiO2 / _TSiN ) and average dielectric breakdown time (average TDDB).

FIG. 7 is a graph showing the ratio of the thickness of the oxide film to the thickness of the nitride film (T
FIG. 6 is a diagram showing a relationship between ( _SiO2 / T _SiN ) and a change amount (ΔIdsat / Idsat) of a drain saturation current before / after an acceleration test.

8 (A) to 8 (D) each show a MOSFE.
Sectional drawing which showed T for every ratio of the film thickness of the oxide film to the film thickness of the nitride film.

FIGS. 9A to 9D are cross-sectional views illustrating a MOSFET according to a second embodiment of the present invention for each of main manufacturing steps.

FIGS. 10A to 10D are cross-sectional views illustrating a MOSFET according to a second embodiment of the present invention for each of main manufacturing steps.

FIG. 11 is an MO according to a second embodiment of the present invention;
FIG. 4 is a cross-sectional view illustrating an SFET.

FIG. 12 is a view showing distribution of mechanical stress applied to a conventional MOSFET.

FIG. 13 is a graph showing mechanical stress (Stress) and change in drain saturation current before and after an acceleration test (ΔIdsat / Idsat).
FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N-type silicon substrate or N-type well, 3 ... Gate oxide film, 5 ... Gate electrode, 7 ... P ^- type extension layer, 9 ... Silicon oxide film, 11 ... Silicon nitride film, 13 ... Silicon oxide film, 15 ... Side walls, 17: P ⁺ type source / drain regions, 19: refractory metal film, 21: silicide layer, 23: interlayer insulating film, 25: contact hole, 27: wiring layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 4M104 AA01 BB01 BB24 BB40 CC01 CC05 DD02 DD04 DD06 DD23 DD66 DD67 DD91 EE03 EE05 EE09 EE12 EE16 EE17 EE20 FF13 FF14 GG09 HH14 5F058 BA04 BD02 BD04 BD10 BF02 BF02 A140 BF42 BG10 BG12 BG14 BG52 BH15 BJ01 BJ08 BK02 BK13 CD06

Claims (6)

[Claims] 1. A semiconductor substrate, a gate electrode formed on the semiconductor substrate and insulated from the semiconductor substrate and having a gate length Lg of 0.14 μm or less, and 0.14 μm or less from the semiconductor substrate. Formed on the side wall of the gate electrode having the gate length Lg.
An oxide film, a nitride film formed on the first oxide film, and a side wall including a stacked structure of a second oxide film formed on the nitride film. A semiconductor device, wherein the ratio "Tox / Tni" between the thickness Tox and the thickness Tni of the nitride film is 0.5 or more. 2. The semiconductor device according to claim 1, wherein the first oxide film is formed from the semiconductor substrate to a sidewall of the gate electrode having a gate length Lg of 0.14 μm or less without a step. 2. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein the thickness Tg of the gate electrode is larger than the gate length Lg. 4. The semiconductor device according to claim 3, wherein the ratio “Tg / Lg” of the thickness Tg of the gate electrode to the gate length Lg is 1.42 or more. 5. The semiconductor device according to claim 1, wherein the first oxide film is a silicon oxide deposited using tetraethoxysilane as a source gas. . 6. A semiconductor substrate, a gate electrode formed on the semiconductor substrate and insulated from the semiconductor substrate and having a gate length Lg of 0.14 μm or less, and 0.14 μm or less from the semiconductor substrate. A nitride film formed over a sidewall of a gate electrode having a gate length of Lg, and a sidewall including a stacked structure of an oxide film formed on the nitride film, wherein the nitride film has a thickness of 10 nm or less. A semiconductor device having: