JPH07253932A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make stored data secret and prevent them from being copied by providing a specific selection frequency detecting circuit, a readout inhibiting circuit, etc. CONSTITUTION:An address decoding circuit 13 decodes an input address signal and sends a select signal to a storage cell array 11 to select a storage cell array 12. While this operation is repeated, a selection frequency detecting circuit 27 detects how many times a specific storage cell array 12 among storage cell arrays 12 is selected. The readout inhibiting means inhibits at least some storage cell arrays 12 from being read out until the selection frequency detecting circuit 27 detects the specific storage cell array 12 being selected as many times as specified. Then when the selection frequency detecting circuit 27 detects the specific storage cell 12 being selected as many times as specified, the selection frequency detecting circuit 27 outputs a signal showing that to the readout inhabiting means, which resets the inhibition of the readout according to the output.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a custom LSI (Ap
application Specific Integrar
ROM as an aerated circuit (ASIC)
And the like, and more particularly to a semiconductor memory device capable of keeping stored data secret and preventing duplication.

[0002]

2. Description of the Related Art FIG. 17 is a circuit block diagram showing a conventional semiconductor memory device such as a ROM. In FIG. 17, 1 is a memory cell array in which normal MOS type memory cell columns 1a are arranged in the row direction, 2 is an address decode circuit for designating an address of the memory cell column 1a in the memory cell array 1, and 3 is an address decode circuit 2. The memory cell output select circuit 4 which selects the output from the memory cell column 1a designated by 1 in units of bit lines determines whether or not to receive the output from the memory cell output select circuit 3 and finally execute the read output. It is an output circuit for controlling. A0 to A8 are input address signals, D
0 to D7 are read output signals.

[0003]

In the conventional semiconductor memory device, since the stored data can be read by anyone, it is easy to duplicate the data or analyze the data. Therefore, even if a program or the like developed with a great deal of expense and labor is stored in a semiconductor memory device and sold, the data in the semiconductor memory device is easily imitated such that the program is copied or analyzed. I will end up. Since such imitation is performed at low cost, a program or the like equivalent to the original program or the like is easily developed and sold as an inexpensive product. Therefore, there is a problem that the profit of the developer of the original program is lost.

In view of the above problems, an object of the present invention is to provide a semiconductor memory device capable of keeping stored data secret and preventing duplication.

[0005]

According to a first aspect of the present invention, there is provided an address decoding circuit for decoding an input address signal, and a memory cell column selected by a selection signal from the address decoding circuit. An output circuit for detecting the output of the selected memory cell string and outputting data to the outside, and detecting that a predetermined memory cell string of the memory cell strings has been selected a preset number of times And a selection count detection circuit that prohibits reading of at least a part of the memory cell columns until the selection count detection circuit detects that the selection count detection circuit has selected a preset number of times. When it is detected that the selected number of times has been selected, a read prohibition unit that cancels the read prohibition according to the output from the selection number detection circuit is provided.

According to a second aspect of the present invention, an address decoding circuit for decoding an input address signal, a memory cell column selected by a selection signal from the address decoding circuit, and the selected memory cell are provided. An output circuit for detecting the output of the column and outputting the data to the outside, and a selection number detection circuit for detecting that a predetermined memory cell column among the memory cell columns has been selected a preset number of times. The input count signal is prohibited from being input to the address decode circuit until the selection count detection circuit detects that the selection count signal has been selected a preset number of times, and the selection count detection circuit is preset. When it is detected that the selected number of times has been selected, a predetermined number of the address decoding times of the input address signal are output according to the output from the selection number detection circuit. To cancel the input prohibition to and an address input inhibiting circuit.

According to a third aspect of the present invention, there is provided a means for solving the problems by receiving an address decode circuit for decoding an input address signal, a memory cell column selected by a selection signal from the address decode circuit, and an output enable signal. An output circuit for detecting the output of the memory cell string and outputting data to the outside, and a selection number for detecting that a predetermined memory cell column of the memory cell columns has been selected a preset number of times. The detection circuit and the selection number detection circuit prohibit the input of the output permission signal to the output circuit until it detects that the selection number of times has been selected a preset number of times, and the selection number detection circuit is set in advance. An output permission that releases the inhibition of the input of the output permission signal to the output circuit according to the output from the selection count detection circuit when it is detected that the selection count has been selected. And a signal input inhibiting circuit.

According to a fourth aspect of the present invention, there is provided a writable memory cell for storing the number of selection times of the predetermined memory cell column required for releasing the signal input prohibition in the address input prohibition circuit. To be

According to a fifth aspect of the present invention, there is provided a writable memory cell for storing an address of the predetermined memory cell column, the selection frequency of which is detected by the selection frequency detection circuit.

According to a sixth aspect of the present invention, there is provided data writing means for writing arbitrary data in the writable memory cell.

According to a seventh aspect of the present invention, there is provided a means for prohibiting reading by the reading prohibiting means between the selection number detecting circuit and the reading prohibiting means regardless of an output signal from the selection number detecting circuit. It further comprises a selection number detection signal invalidating circuit for canceling.

According to an eighth aspect of the present invention, a signal input of the address input prohibition circuit is provided between the selection count detection circuit and the address input prohibition circuit regardless of an output signal from the selection count detection circuit. A selection number detection signal invalidating circuit for canceling the prohibition is further provided.

[0013]

In the semiconductor memory device according to claim 1 of the present invention,
First, the address decoding circuit decodes the received input address signal and sends a selection signal to the memory cell array to select a memory cell column. While this operation is repeated, the number-of-times-of-selection detection circuit detects the number of times that a predetermined memory cell row of the memory cell rows has been selected. Here, the read prohibiting means prohibits reading of at least a part of the memory cell columns until the selection frequency detection circuit detects that the predetermined memory cell columns have been selected a preset number of times. Then, when the selection number detection circuit detects that the predetermined memory cell column has been selected a preset number of times, the selection number detection circuit outputs a signal to that effect to the read prohibition means, and outputs to such an output. Therefore, the read prohibition means releases the prohibition of reading. In this way, the reading of stored data can be prohibited, and the data can be kept secret from users who do not know the circumstances, unless a specific procedure such as selecting a predetermined storage cell row a preset number of times is taken. it can.

In the semiconductor memory device according to the second aspect of the present invention, when the data is kept secret, the address input prohibiting circuit prohibits the input of a predetermined input address signal to the address decoding circuit. As a result, when data is concealed, it becomes the same as when it is not input even when a predetermined input address signal is transmitted, and it is possible to conceal all data in a certain area corresponding to when the predetermined input address signal is input.

In the semiconductor memory device according to claim 3 of the present invention, when the data is kept secret, the output permission signal input prohibition circuit prohibits the input of the predetermined output permission signal to the output circuit.
As a result, at the time of concealing the data, even when the output permission signal is transmitted, the state is the same as when the signal is not transmitted. Since the output circuit is not driven, the data is not read out and all the data in the memory cell array can be concealed.

In the semiconductor memory device according to the fourth aspect of the present invention, the writable memory cell has a condition necessary for canceling the signal input prohibition in the address input prohibition circuit, that is, a selection serving as a reference of a predetermined memory cell column. You can freely write and store the number of times. Therefore, the configurator can freely set the data read conditions, making it difficult to decipher the read conditions and ensuring the confidentiality of the data.

In the semiconductor memory device according to the fifth aspect of the present invention, a writable memory cell is provided with an address of a memory cell column for detecting a predetermined number of times of selection necessary for releasing the signal input prohibition in the address input prohibition circuit. Can be written and stored in.
Therefore, the configurator can freely set the data read conditions, making it difficult to decipher the read conditions and ensuring the confidentiality of the data.

In the semiconductor memory device according to the sixth aspect of the present invention, when data is written in the writable memory cell, the data can be written by the data writing means.

In the semiconductor memory device according to claim 7 of the present invention, when it is desired to temporarily cancel the data concealment entirely at the time of inspection after manufacturing, etc., a signal is input to the selection number detection signal invalid circuit to prohibit reading. The prohibition of reading by means is released. Then, regardless of the output signal from the selection number detection circuit, the data confidentiality can be completely released.

In the semiconductor memory device according to the eighth aspect of the present invention, when it is desired to temporarily cancel the data concealment entirely at the time of inspection after manufacturing, etc., a signal is input to the selection number detection signal invalidation circuit to input the address. Cancel the signal input prohibition in the prohibition circuit. Then, regardless of the output signal from the selection number detection circuit, the data confidentiality can be completely released.

[0021]

【Example】

[First Embodiment] {Structure} FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, 11 is a memory cell array and 12
Is a memory cell column, 13 is an address decode circuit for designating an address of the memory cell column 12 in the memory cell array 11, and 14 is an output from the memory cell column 12 designated by the address decode circuit 13 in bit line units. The memory cell output select circuit selected by 1 is an output circuit which receives a signal from the memory cell output select circuit 14 and permits read output. Further, A0 to A8 in FIG. 1 are input address signals input to the address decoding circuit 13, and D0 to D7 are output signals from the output circuit 15. Of the input address signals A0 to A8, A0,
A1 is a signal for selecting eight output signals D0 to D7 among the outputs of the memory cell column 12, and A2 to A8 are signals for selecting one memory cell column out of the plurality of memory cell columns 12. Is.

As shown in FIG. 2, the memory cell column 12 is formed by arranging a plurality of memory cells Ms1 as N-channel MOS transistors in a column shape. By arranging the memory cells Ms1 in a row direction, the memory cell array 11 is formed. Constitute.

As shown in FIG. 3, the address decoding circuit 13 decodes the address signals A2 to A8 and selects one of the memory cell columns 12 according to the decoding result, and the cell column selecting means 21 and the address. Signal A
0, A1 are decoded, and the output selection signal sending means 22 for sending the decoding result to the memory cell output select circuit 14 is provided. The cell column selecting means 21 includes seven positive input inverters In1 and 2 ⁷ = 128 AND circuits An1.
Equipped with. Each AND circuit An1 has seven input terminals, and the input address signals A2 to A of the seven input terminals are provided.
8 corresponding to the input side (positive signal) A2D to A8D or the output side (inverted signal) of the positive input inverter In1
It is connected to A2B to A8B. (00H) to (7FH) in FIG. 3 are outputs of the AND circuit An1 and are connected to the corresponding memory cell column 12 in the memory cell array 11. The numbers in each of (00H) to (7FH) are in hexadecimal notation. Output selection signal transmitting means 2
2 includes two positive input inverters In2 and 2 ² = 4 AND circuits An2. Each AND circuit An2 has two input terminals and two input address signals A
0, A1 corresponding positive input inverter In2
The input side (positive signal) A0D, A1D or the output side (inverted signal) A0B, A1B is connected. (0H) in Fig. 3
Through (3H) are outputs of the AND circuit An2, which are connected to the memory cell output select circuit 14.

As shown in FIG. 4, the memory cell output select circuit 14 is composed of a selection element Ms2 as a selection N-channel MOS transistor connected to the bit line of the memory cell Ms1 in the memory cell column 12. . The gate of the selection element Ms2 has outputs (0H) to (3) of the output selection signal sending means 22 of the address decoding circuit 13.
H). The selection element Ms2 is 4
The groups are individually connected to each other, and their drains are commonly connected and connected to the output circuit 15. As a result, the memory cell output select circuit 14 has a function of selecting a signal from the memory cell column 12 based on the address signals A0 and A1 and consolidating it into eight output signals D0 to D7.

The output circuit 15, as shown in FIG.
Each of 0 to D7 is provided with a negative input type inverter In3 and a logic circuit Bf, and the input side of the inverter In3 is connected to the power source V _DD via the resistor R2. As shown in FIG. 6, the logic circuit Bf includes an inverter (Q1), a positive input NAND circuit (Q2), and a positive input NOR circuit (Q
3), a general switching circuit composed of a P channel MOS (Q4) and an N channel MOS (Q5). The output enable signal (bar OE) is input to the input terminal of the inverter (Q1) of the logic circuit Bf and one input terminal of the positive input NAND circuit (Q2).

In this embodiment, as shown in FIG. 1, the output signals (input address signals A0 to A8) from the address decoding circuit 13 are monitored and the input address signal A0 is monitored.
A security circuit 25 for prohibiting the input to the address decoding circuit 13 of A8 to A8 is provided. The security circuit 25 monitors the two input address signals A7 and A8 from the address decoding circuit 13, and detects the two storage cell columns 1
Until the number of times 2 is selected reaches the preset number,
The input address signals A7 and A8 are prohibited from being input to the address decoding circuit (that is, "L" is always input). As shown in FIG. 1, the security circuit 25 detects the number of selections for each memory cell column 12, and a selection number detection circuit 27, and an input to the cell column selection means 21 based on a signal from the selection number detection circuit 27. It is composed of an address input inhibition circuit 28 which inhibits the input of an address signal.

As shown in FIG. 7, the input side of the selection number detecting circuit 27 has two predetermined connecting lines (X1, X1) among the connecting lines from the address decoding circuit 13.
2) and an output permission signal (bar OE) for permitting output of the output circuit 15. And X1 and X
A memory function for storing in advance a specific combination of the two time-series signal transition combinations, and the actually detected X1
And a determination function of determining whether or not the combination of the signal transitions in time series of X2 is a signal transition having a specific regularity, and the combination of the signal transitions is specified based on the determination result of the determination function. It has a function of outputting the input address signals A7 and A8 to the address input prohibiting circuit 28 when it has regularity. Here, the specific combination of the signal transitions is limited to the signal transitions that can be easily determined by counting the number of accesses to the memory cell column 12, and specifically, first, the memory cell column 12 coupled to X1 is 2 This is limited to the case where the memory cell column 12 coupled to X2 is read immediately after being read repeatedly more than once. Whether or not the memory cell column 12 coupled to X1 or X2 is read can be detected based on the combination of the potential of X1 or X2 and the potential of the output permission signal (bar OE). Specifically, the potential of X1 or X2 is "
H "(the memory cell string to be combined with X1 is selected),
Moreover, it is determined whether or not the potential of the output permission signal (bar OE) becomes "L" (reading state). 31 in FIG. 7 is O
R circuit, 32 is the first AND circuit, 33 is the second AND circuit
Circuit, 34 is a third AND circuit, 35 is a fourth AND circuit, 36 is a negative input inverter circuit to which an output enable signal (bar OE) is input to an input terminal, 37 is a first flip-flop circuit, and 38 is Second flip-flop circuit, 39
Is a third flip-flop circuit, 40 is a fourth flip-flop circuit, R1 is a resistor, and C1 is a capacitor.
In each of the flip-flop circuits 37 to 40, T is a trigger input terminal, D is a data input terminal, and Q is an output terminal. The OR circuit 31 has three input terminals, and X1, X2, and output enable signals (bar OE) are input to the respective input terminals. The first AND circuit 32 has two input terminals, one input terminal of which is X1.
The other input terminal is connected to the output terminal of the inverter circuit 36. Like the first AND circuit 32, the second AND circuit 33 has two input terminals, one input terminal is connected to X1, and the other input terminal is connected to the output terminal of the inverter circuit 36. Has been done. The third AND circuit 34 has two input terminals, one input terminal is connected to X2, and the other input terminal is connected to the output terminal of the inverter circuit 36. The fourth AND circuit 35 has two input terminals, one input terminal is connected to the output terminal of the OR circuit 31, and the other input terminal is connected to the connection point of the resistor R1 and the capacitor C1. . Further, the output terminal of the fourth AND circuit 35 is inverted and input to the first flip-flop circuit 37 to the third flip-flop circuit 39. The trigger input terminal T of the first flip-flop circuit 37 is connected to the output terminal of the first AND circuit 32, and the data input terminal D is connected to the power supply V _DD . The trigger input terminal T of the second flip-flop circuit 38 is connected to the second AND circuit 33.
, And the data input terminal D is connected to the output terminal Q of the first flip-flop circuit 37. The trigger input terminal T of the third flip-flop circuit 39 is connected to the output terminal of the third AND circuit 34, and the data input terminal D is connected to the output terminal Q of the second flip-flop circuit 38. . The trigger input terminal T of the fourth flip-flop circuit 40 is connected to the output terminal of the third flip-flop circuit 39, and the data input terminal D is connected to the power supply V _DD . The resistance R
1 is connected to the power supply V _DD . The capacitor C1 is grounded.

The address input inhibit circuit 28, as shown in FIG. 1, includes the input address signals A7 and A to be inhibited.
Each AND is composed of AND circuits
The circuit has two input terminals, one input terminal for the corresponding input address signals A7 and A8, and the other input terminal for the output of the fourth flip-flop circuit 40 of the selection number detection circuit 27. They are connected to the terminals Q, respectively.

{Operation} First, the input address signals A0 to A
6 is input from an external control device or interface. However, at this point, the input address signals A7, A
The address input prohibition circuit 28 corresponding to No. 8 is in the input prohibition state. Upon receiving the input address signals A0 to A6, the cell column selecting means 21 decodes these signals and outputs the signals to the memory cell array 11 or the memory cell output select circuit 14.
Send to. Here, the predetermined specific connection line X1
Becomes "H" and the output enable signal (bar OE) becomes "H".
The selection number detection circuit 27 detects that it has become L ″ (read state). Subsequently, the input address signals A0 to A8.
Then, the selection number detection circuit 27 detects that X1 becomes "H" again and the output permission signal (bar OE) becomes "L" (reading state). Immediately after that, X2
Becomes "H" and the output enable signal (bar OE) becomes "H".
The selection count detection circuit 27 detects that the selection count detection circuit 27 has reached L ″ (reading state).
It is determined that the reading is performed in the order of 1 and X2, and the output signal is transmitted to the address input inhibition circuit 28. The address input prohibition circuit 28 releases the input prohibition of the input address signals A7 and A8 for the first time at this point, and all the signals can be input.

FIG. 8 shows an address map of the semiconductor memory device of this embodiment. As shown in FIG. 8, in the semiconductor memory device of the present embodiment, addresses (A8, A7, A6,
A5, A4, A3, A2, A1, A0) = (0,0,
0,0,0,0,0,0,0) to (0,0,1,1,
1, 1, 1, 1, 1) area (readable area) Ar
The data of 1 can be read correctly, but (0, 1,
0,0,0,0,0,0,1) to (1,1,1,1,
The area (concealed area) Ar0 of 1, 1, 1, 1, 1) is X
Data cannot be read correctly unless reading is performed in the order of 1, X1, and X2 (hereinafter referred to as an access procedure). That is (0, 1, 0, 0, 0, 0, 0, 0,
The data in the secret area Ar0 from (0) to (1,1,1,1,1,1,1,1,1,1) can be kept secret to those who do not know the access procedure. In addition, without performing the above access procedure, for example, the address (1, 1, 0,
(0,0,0,0,0,0) is input to the semiconductor memory device of this embodiment to read the stored data, A8 and A7 are not correctly transmitted to the address decoding circuit 13 and the address Since "L", that is, 0 is given to the decode circuit 13 from the address input prohibiting circuit 28 for the inputs corresponding to A8 and A7, the address (0, 0,
The same data as when 0, 0, 0, 0, 0, 0, 0) is input is read.

Since the above access procedure is defined by the circuit design on the semiconductor chip, the analysis is not easy, and if the package is sealed with a general opaque plastic package, it is possible to compare with the conventional semiconductor memory device. Since it cannot be distinguished, the existence of the address input prohibition circuit as described above cannot be known. Therefore, the stored data can be kept secret from a person who does not know the above access procedure, and copying can be prevented, so that there is an advantage that the interest of the creator of the stored data can be protected.

In this embodiment, if there is no certain condition, the input address signals A0 to A8 make it impossible to read the stored contents of the address in which at least one of A7 and A8 is H. In the case of a normal operation in which the device is incorporated into such a device and operates, the stored contents of the address where at least one of A7 and A8 is H are often output. in this case,
A means for canceling the address input prohibition of the address input prohibition circuit 28 needs to be incorporated in addition to the above configuration. As the canceling means, for example, the above-described operation for canceling the prohibition of address input, that is, the address access order (for example, X1, X1, X2 order) and the number of accesses, can be programmed in advance in a built-in microcomputer. Good.

[Second Embodiment] {Structure} FIG. 9 shows a semiconductor memory device according to a second embodiment of the present invention. The parts having the same functions as those in the first embodiment are designated by the same reference numerals. In the semiconductor memory device of this embodiment, as shown in FIG. 9, between the memory cell array 11 and the memory cell output select circuit 14, the predetermined memory cell column 12 necessary for releasing the signal input prohibition in the address input prohibition circuit 28. A writable memory cell column 45 for storing the number of selections is provided. The writable memory cell array 45 has the same number of memory cell elements as the memory cell arrays 12 in the memory cell array 11 arranged in a row, but each of the memory cells is writable. Different from column 12. The writable memory cell array 45 is a flash memory, an EEPROM or an EPR.
A writable non-volatile memory cell such as OM is used.

Further, in the first embodiment, the time-series signal transition of X1 and X2 in order to make it readable, that is, the reference of the number of times of selection of "H" of X1 and X2 is fixed. In the present embodiment, X1, for making the data readable,
Since the time-series signal transition of X2 is freely written in the writable memory cell column 45, it is necessary to call the reference number of times from the writable memory cell column 45 when the selection number is detected. Therefore, in the present embodiment, a selection number detection circuit 46 as shown in FIG. 10 is installed in place of the selection number detection circuit 27 shown in FIG. In FIG. 10, 51 is a negative input inverter circuit, 52 is a first AND circuit, 53 is a second AND circuit, 54 is an OR circuit, 55 is a third AND circuit, 56 is a first 8-bit counter, 5
7 is a second 8-bit counter, 58 and 59 are positive input exclusive OR circuits (EX.OR circuits), 61 and 62.
Is a positive input NOR circuit, 63 is a fourth AND circuit, 64
Is a fifth AND circuit, 65 is an IC, R2 is a resistor, and C2 is a capacitor.

An output enable signal (bar OE) is input to the input terminal of the negative input inverter circuit 51. The first
The AND circuit 52 has two input terminals, and one input terminal is connected to the output terminal of the negative input inverter circuit 51. The other input terminal is connected to X1. The second AND circuit 53 has two input terminals, and one input terminal is connected to the output terminal of the negative input inverter circuit 51. The other input terminal is X
Connected to 2. The OR circuit 54 has three input terminals, and an output enable signal (bar OE), X
1 and X2 are input. The first 8-bit counter 56 has a trigger input terminal T, a latch input terminal R, and eight output terminals, and the trigger input terminal T is connected to the output terminal of the first AND circuit 52, The latch input terminal R is connected to the output terminal of the OR circuit 54. The positive input exclusive OR circuit 58 is provided corresponding to the eight output terminals of the first 8-bit counter 56. Each positive input exclusive OR
The circuits 58 each have two input terminals, one input terminal being the output terminal of the first 8-bit counter 56, and the other input terminal being the writable memory cell array 4
5 are connected to each. One positive input NOR circuit 61 is provided for each of the four positive input exclusive OR circuits 58. The positive input NOR circuit 61 has four input terminals, and the output terminals of the respective positive input exclusive OR circuits 58 are connected to the positive input NOR circuit 61. The fourth AND circuit 63 has two input terminals, and each is connected to the output terminal of the positive input NOR circuit 61.
The third AND circuit 55 has two input terminals, one of which is an output terminal of the OR circuit 54.
The other input terminal is connected to the output terminal of the fourth AND circuit 63. The second 8-bit counter 57
Has a trigger input terminal T, a latch input terminal R and eight output terminals, the trigger input terminal T is connected to the output terminal of the second AND circuit 53, and the latch input terminal R is It is connected to the output terminal of the third AND circuit 55. The positive input exclusive OR circuit 5
9 are provided corresponding to the eight output terminals of the first 8-bit counter 56. Each of the positive input exclusive OR circuits 59 has two input terminals. One input terminal is the output terminal of the second 8-bit counter 57 and the other input terminal is the writable memory. Each is connected to the cell row 45. The positive input NOR circuit 6
One 2 is provided for each of the four positive input exclusive OR circuits 59. The positive input NOR circuit 62 has four input terminals, and the output terminals of the respective positive input exclusive OR circuits 59 are connected to the positive input NOR circuit 62. The fifth AND circuit 64 has two input terminals, and each is connected to the output terminal of the positive input NOR circuit 62. The IC 65 has a data input terminal D, an output terminal Q, a trigger input terminal T and a latch input terminal R.
The data input terminal D is connected to the power source V _DD , and the trigger input terminal T
Is connected to the output terminal of the fifth AND circuit 64, the latch input terminal R is connected to the connection point of the resistor R2 and the capacitor C2, and the output terminal Q is connected to the address input inhibition circuit 28. The resistor R2 is connected to the power supply V _DD . The capacitor C2 is grounded.

In this embodiment, a data writing means for writing arbitrary data in the writable memory cell column 45 is required. Therefore, instead of the memory cell output select circuit 14 and the input / output circuit 48 which are configured to have only the output function in the first embodiment, the memory cell input / output select circuit 47 and the input / output circuit having both the input and output functions. 48 are installed and these are used as a writing means. Data writing to the writable memory cell column 45 may be performed through the memory cell input / output select circuit 47 and the input / output circuit 48. The memory cell input / output select circuit 47 and the input / output circuit 48
May use a general microcomputer chip or microprocessor chip having a CPU. The rest of the configuration is similar to that of the first embodiment, so the explanation is omitted.

{Operation} In FIG. 10, the output X1 from the address decode circuit 13 and the output enable signal (bar OE) to the input / output circuit 48 select the memory cell column 12 coupled to X1. At this time, the selection count detection circuit 4
In the first 8-bit counter 56 of 6, the memory cell column 1
The number of times 2 has been read is counted, the stored data in the writable memory cell column 45 is compared with the above number, and the reset of the second 8-bit counter 57 is released only when these numbers match.

In the second 8-bit counter 57, the memory cell column 12 coupled to X2 is selected by the output X2 from the address decoding circuit 13 and the output enable signal (bar OE) from the input / output circuit 48, and the reading is performed. The number of breaks is counted, and the above-mentioned number is compared with the stored data of the writable memory cell column 45. When the numbers of times match, the output to the address input prohibition circuit 28 is set to "H".
Set to.

That is, a writable memory cell column 45
The memory cell column 12 to which X1 is coupled is read a number of times corresponding to the data stored in
The address input prohibition is released and A8 and A7 are set to "H" for the first time by reading the memory cell column 12 to which is connected by the number of times corresponding to the data stored in the writable memory cell column 45. It becomes possible to read out the memory cell column 12 (the secret area Ar0 in FIG. 8) designated when "".

Here, X1, for canceling the signal concealment,
In order to cancel the signal transition of X2, the data in the writable storage cell column 45 may be updated via the storage cell input / output select circuit 47 and the input / output circuit 48. In this way, the memory cell column 4 in which the procedure (access procedure) that enables reading of the secret area Ar0 is writable
Since it is determined by the data written in 5, various access procedures can be set. By doing so, the access procedure can be freely set by the end user, an intermediate dealer who stores the program, and the procedure can be kept secret to the manufacturer of the semiconductor memory device.

[Third Embodiment] FIG. 11 shows a semiconductor memory device according to a third embodiment of the present invention. The parts having the same functions as those in the first embodiment are designated by the same reference numerals. In the first embodiment, the address decoding circuit 1
Some of the input address signals A8, A of the three
Although the input of 7 is prohibited by the address input prohibition circuit 28, in the semiconductor memory device of the present embodiment, instead of this method, the output permission signal (bar OE) to the output circuit 15 is sent as shown in FIG. Is prohibited by the output permission signal input prohibition circuit 71. The output permission signal input prohibition circuit 71 is composed of a positive input inverter circuit 72 and a positive input OR circuit 73. The input terminal of the positive input inverter circuit 72 is connected to the output terminal of the selection number detection circuit 27. The positive input OR circuit 73 has two input terminals, one input terminal of which is the positive input inverter circuit 72.
Of the output permission signal (bar OE) from the outside is input to the other input terminal. The positive input OR
The output terminal of the circuit 73 is connected to the inverting input terminal of the logic circuit Bf of the output circuit 15 as shown in FIG. The logic circuit Bf of the output circuit 15 is similar to that of the first embodiment shown in FIG. Further, the other configurations, particularly the internal configuration of the selection number detection circuit 27, are the same as those in the first embodiment, and the description thereof will be omitted.

In the semiconductor memory device having the above structure, a predetermined signal transition (for example, X1, X1, X2 as in the first embodiment) is performed.
, The selection count detection circuit 27 outputs the “H” signal, which is inverted by the positive input inverter circuit 72 to become “L” I, and then becomes positive. It is input to one input terminal of the input OR circuit 73. At this time, when the output enable signal (bar OE) (= "L") is input, both of the two inputs to the positive input OR circuit 73 are "
Since it is L ", an" L "signal is output to the output circuit 15. At this time, as shown in FIG.
Since the "H" signal is input, when the signal from the memory cell output select circuit 14 is "H", the output becomes "H" and the data is read.

On the other hand, when the above-mentioned predetermined signal transition does not occur, as shown in FIG. 11, the selection count detection circuit 27 outputs "L".
A signal is output, inverted by the positive input inverter circuit 72 to become “H”, and then input to one input terminal of the positive input OR circuit 73. At this time, even if the output enable signal (bar OE) (= "L") is input to the other input terminal, since "H" is input to one input terminal, the positive input OR circuit 73 is "H". The signal is output to the output circuit 15. At this time, as shown in FIG. 12, the inverted "L" signal is input to Bf, so that the output becomes "L" even if the signal from the memory cell output select circuit 14 is "H".
That is, the bar OE is in a high impedance state (floating state), and the memory cell output select circuit 14
The signal from is canceled.

With this configuration, the readable area Ar1 as shown in the address map of FIG. 8 is eliminated, and the reading of the stored data can be prohibited in all areas unless a predetermined access procedure is followed. Therefore, compared to the first embodiment, there is an advantage that all data can be kept secret.

In the present embodiment as well, as in the first embodiment, if there is no certain condition, the input address signal A0
Depending on A8, at least one of A7 and A8 is H
However, in the case of a normal operation that is incorporated in a device such as a computer to operate, at least one of A7 and A8 also has a stored content of H. It is often output. In this case, means for canceling the address input prohibition of the address input prohibition circuit 28 needs to be incorporated in addition to the above configuration. As the releasing means, for example, the above-mentioned operation for releasing the prohibition of address input, that is, the address access sequence (for example, X1, X1, X2).
Order) and the number of times of access may be programmed in advance in a built-in microcomputer.

[Fourth Embodiment] FIG. 13 shows a semiconductor memory device according to a fourth embodiment of the present invention. The parts having the same functions as those in the first embodiment are designated by the same reference numerals. In the semiconductor memory device of this embodiment, the signal of the address input prohibition circuit 28 is provided between the selection count detection circuit 27 and the address input prohibition circuit 28 in the security circuit 25 regardless of the output signal from the selection count detection circuit 27. A selection number detection signal invalidating circuit 77 for canceling the input inhibition is provided. The selection number detection signal invalidating circuit 77 is a positive input OR circuit and has two input terminals, one input terminal is connected to the output terminal of the selection number detecting circuit 27, and the other input terminal is External prohibition command signal C
A is input. The output terminal of the selection number detection signal invalidating circuit 77 is connected to each input terminal of the two address input prohibiting circuits 28. The rest of the configuration is similar to that of the first embodiment, so the explanation is omitted.

In the above structure, the prohibition cancellation command signal CA
Is "H", the selection number detection signal invalid circuit 77 outputs "H" regardless of whether the selection number detection signal output from the selection number detection circuit 27 is "H" or "L". , Release the signal input inhibition of the address input inhibition circuit.
Then, the address input can be set to be correctly transmitted to the address decode circuit at any time, and the data at all addresses can be read. Therefore, there is an advantage that the semiconductor memory device manufacturer does not need to input a signal with a predetermined signal transition each time a device test is performed. The prohibition cancellation command signal CA is not known to anyone but the manufacturer unless it is disclosed as the specifications of the semiconductor memory device, and it is possible to prevent the general user from decoding the data.

Various methods can be considered as to how the prohibition cancellation command signal CA is given to the selection number detection signal invalidation circuit 77. For example, (1) A method of transmitting a prohibition cancellation command signal CA to be input to the selection number detection signal invalidation circuit 77 using, for example, a ternary input terminal as shown in FIG. When the power supply voltage V _CC = 5V, twice the power supply voltage V _CC from the input terminal, that is, 10V
By applying the above potentials, the connection point between the CMOS transistors T1 and T2 is set to "H" and the prohibition cancellation command signal CA is set to "H". By using the three input terminals in this way, it is possible to simultaneously allocate to other signal terminals such as a reset terminal, a CE terminal, or a surplus terminal. (2) After the semiconductor memory device is molded as a chip and completed as a product, a prohibition release command signal CA is given to a certain pin.
As a power supply potential. (3) A test signal detection circuit that allows a test signal indicating that a test is to be performed to be input from the outside into the chip and detects whether or not the test signal is input, and a detection result of the test signal detection circuit And a command signal transmission circuit for transmitting the prohibition cancellation command signal CA to the selection number detection signal invalidation circuit 77 based on the above. (4) A command signal generation circuit for generating the prohibition cancellation command signal CA is provided in the chip, and the command signal generation circuit is always "
A method of outputting an "H" signal, but outputting only "L" if the fuse (power supply) is turned off after the test is completed.

It goes without saying that, by any of the above methods (1) to (4), the manufacturer or the like can release the confidentiality of the data at any time while keeping the data confidential to the user.

[Fifth Embodiment] FIG. 15 shows a semiconductor memory device according to a fifth embodiment of the present invention. The parts having the same functions as those in the second embodiment are designated by the same reference numerals. The semiconductor memory device of this embodiment is similar to the second embodiment in that a writable memory cell column 45 is provided between the memory cell array 11 and the memory cell output select circuit 14, but the writable The memory cell array 45 is different from the second embodiment in that it is for storing which one of the plurality of memory cell arrays 12 is a predetermined memory cell array 12 whose number of selections is detected. . That is,
In the writable memory cell column 45, the memory cell input / output select circuit 47 and the input / output circuit 48 as the data writing means selects the target memory cell column 12 of the number of times of selection, which serves as a criterion for determining whether to prohibit reading. Address data is written. The writable memory cell column 45
Are the flash memory and EEPR as in the second embodiment.
A writable non-volatile memory cell such as OM or EPROM is used.

Further, in the present embodiment, unlike the second embodiment, the address of the target memory cell column 12 of the number of times of selection, which is a criterion for determining whether or not to prohibit reading, is changed. Accordingly, it is necessary to change the access points of X1 and X2 input to the selection number detection circuit 27. Therefore, in this embodiment, as shown in FIG. 15, the selector 8 is provided between the cell column selecting means 21 and the memory cell array 11.
1 is interposed. The selector is a general one having a transistor connected to each connection line between the cell column selecting means 21 and the memory cell array 11, and receives a gate input from a writable memory cell column 45 to select one of them. The signals of the pair of connection lines are output to the selection number detection circuit 27 as X1 and X2. The configurations of the memory cell array 11, the memory cell column 12, the address decode circuit 13, the selection number detection circuit 27, the address input prohibition circuit 28, the memory cell input / output select circuit 47 and the input / output circuit 48 are the same as those in the second embodiment. Therefore, the description is omitted.

According to this embodiment, as in the second embodiment,
A procedure for enabling reading of the secret area Ar0, that is, a memory cell column 12 for detecting a signal transition for canceling the secret
Is determined by the data written in the writable memory cell column 45, so that various access target memory cell columns 12 can be set. Then, the end user or an intermediate distributor who stores the program can freely set the access target storage cell column 12,
The procedure can be kept secret from the manufacturer of the semiconductor memory device.

[Sixth Embodiment] FIG. 16 shows a semiconductor memory device according to the sixth embodiment of the present invention. The parts having the same functions as those in the fifth embodiment are designated by the same reference numerals. The semiconductor memory device of this embodiment stores which of the plurality of memory cell columns 12 the predetermined memory cell column 12 of which the number of times the writable memory cell column 45 is selected is stored. This is similar to the fifth embodiment in that the writable memory cell column 45 is further selected from the predetermined memory cell column 12 necessary for releasing the signal input inhibition in the address input inhibition circuit 28. It differs from the fifth embodiment in that the number of times is also stored. That is, in the writable memory cell column 45, the number of selections serving as a criterion for determining whether or not the reading is prohibited by the memory cell input / output select circuit 47 and the input / output circuit 48 as the data writing means, and the target. Memory cell column 12
Both address data of are written. As the writable memory cell column 45, a writable non-volatile memory cell such as a flash memory, an EEPROM or an EPROM is used as in the second and fifth embodiments.

Further, in the present embodiment, as in the fifth embodiment, since the address of the target storage cell column 12 of the number of times of selection, which is a criterion for determining whether to prohibit reading, is changed, A selector 81 is interposed between the column selection means 21 and the memory cell array 11. The memory cell array 11, the memory cell column 12, the address decode circuit 13, the selection number detection circuit 27, the address input prohibition circuit 28, the memory cell input / output select circuit 47, the input / output circuit 48, and the selector 81 have the second configuration. The description is omitted because it is similar to the embodiment.

According to the present embodiment, as in the second embodiment, X1 and X2 that enable reading of the secret area Ar0.
It is possible to freely set the number of selections serving as the reference of, and similarly to the fifth embodiment, it is possible to freely set the memory cell row 12 that is the target for detecting the signal transition for descrambling, and the descrambling condition is further complicated. Can be made even more difficult to decipher.

[Modification] (1) In the second, fourth, fifth, and sixth embodiments, as in the first embodiment, selection of a predetermined cell row. When the number of times is constant, the valid input address signals A0 to A8 are input to the address decoding circuit 13. However, as in the third embodiment, the number of times of selecting a predetermined cell row is constant. In this case, the output permission signal input prohibition circuit may be configured to cancel the inhibition of the input of the output permission signal to the output circuit.

(2) In the second, fifth, and sixth embodiments, as in the fourth embodiment, a signal for permitting data read is externally input, It may be possible to easily release the read prohibition in a test or the like.

[0058]

According to the first aspect of the present invention, selection for detecting that a predetermined memory cell column is selected a preset number of times in a semiconductor memory device having an address decoding circuit, a memory cell column, and an output circuit. Since the number-of-times detection circuit and the read-out prohibition means for switching the prohibition and the release of the prohibition in accordance with the output from the selection number-of-times detection circuit are provided, it is possible to select a specific memory cell column a predetermined number of times. As long as no steps are taken, reading of stored data can be prohibited, and the data can be kept secret from users who do not know the circumstances. Therefore, it becomes difficult to decrypt or copy the data stored in the semiconductor memory device, and it is possible to protect a program or the like developed with great expense and labor.

According to the second aspect of the present invention, the number of selections is detected in the semiconductor memory device including the address decode circuit, the memory cell column, and the output circuit to detect that the predetermined memory cell column has been selected a preset number of times. Since a circuit and an address input prohibition circuit for switching the input of the input address signal to the address decode circuit and the prohibition of input according to the output from the selection number detection circuit are provided, a predetermined memory cell string is set a predetermined number of times. Unless a specific procedure such as selecting is performed, there is an effect that reading of stored data is prohibited and all data in a certain area corresponding to the case where a predetermined input address signal is input can be kept secret.

According to the third aspect of the present invention, the number of selections is detected in the semiconductor memory device including the address decode circuit, the memory cell column, and the output circuit to detect that the predetermined memory cell column has been selected a preset number of times. Since the circuit and the output permission signal input prohibition circuit for inputting and prohibiting the input of the output permission signal to the output circuit according to the output from the selection number detection circuit are provided, the output permission signal input prohibition circuit does not operate when the data is kept secret. Input of the specified output enable signal to the output circuit can be prohibited, and even when the output enable signal is sent, it remains in the same state as when it was not sent.The output circuit is not driven and reading is not performed. There is an effect that the data of can be kept secret.

According to claim 4 of the present invention, since the writable memory cell for storing the number of times of selection of the predetermined memory cell column necessary for canceling the signal input prohibition in the address input prohibition circuit is provided, the writable memory cell is writable. It is possible to freely write and store the condition necessary for canceling the signal input prohibition in the address input prohibition circuit, that is, the number of times of selection, which is a reference of a predetermined memory cell column, in such a memory cell. Therefore, the configurator can freely set the data reading conditions, making it difficult to decipher the reading conditions and ensuring the confidentiality of the data.

According to claim 5 of the present invention, since the writable memory cell for storing the address of the predetermined memory cell column whose selection count is detected by the selection count detection circuit is provided, the writable storage It is possible to freely write and store in the cell the address of the memory cell column that detects the predetermined number of times of selection necessary for canceling the signal input prohibition in the address input prohibition circuit. Therefore, the configurator can freely set the data reading conditions, making it difficult to decipher the reading conditions and ensuring the confidentiality of the data.

According to claim 6 of the present invention, since the data writing means for writing arbitrary data to the writable storage cell is provided, when writing the data to the writable storage cell, the data writing means writes the data. The effect is that you can.

According to claim 7 of the present invention, between the selection number detecting circuit and the read inhibiting means, the selection number detecting signal for releasing the read inhibition by the read inhibiting means regardless of the output signal from the selection number detecting circuit. Since the invalid circuit is provided, when it is desired to temporarily cancel the data confidentiality entirely at the time of inspection after manufacturing, a signal can be input to the selection count detection signal invalid circuit to cancel the read prohibition by the read prohibition means. . Therefore, there is an effect that the data confidentiality can be completely released regardless of the output signal from the selection number detection circuit.

According to claim 8 of the present invention, the signal input inhibition of the address input inhibition circuit is released between the selection number detection circuit and the address input inhibition circuit regardless of the output signal from the selection number detection circuit. Since it is equipped with a selection count detection signal invalid circuit, when you want to temporarily clear the data confidentiality at the time of inspection after manufacturing, input a signal to the selection count detection signal invalid circuit, and The signal input prohibition can be released. Therefore, there is an effect that the data confidentiality can be completely released regardless of the output signal from the selection number detection circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell column of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a logic circuit diagram showing an address decoding circuit of the semiconductor memory device of the first exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a memory cell output select circuit of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing an output circuit of the semiconductor memory device according to the first exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing details of an output circuit of the semiconductor memory device according to the first exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram showing a selection frequency detection circuit of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing an address map of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a block diagram showing an outline of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a selection count detection circuit of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a block diagram showing an outline of a semiconductor memory device of a third embodiment of the present invention.

FIG. 12 is a circuit diagram showing details of an output circuit of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 13 is a block diagram showing an outline of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a signal input circuit from the outside of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing an outline of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 16 is a block diagram showing an outline of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 17 is a block diagram showing an outline of a conventional semiconductor memory device.

[Explanation of symbols]

 11 memory cell array 12 memory cell column 13 address decode circuit 14 memory cell output select circuit 15 output circuit 27 selection frequency detection circuit 28 address input prohibition circuit 45 memory cell sequence 46 selection frequency detection circuit 47 memory cell input / output selection circuit 48 input / output circuit 71 output permission signal input prohibition circuit 77 selection number detection signal invalidation circuit 81 selector A0 to A8 input address signal Ar0 secret area Ar1 possible area CA prohibition cancel command signal OE output permission signal

Claims (8)

[Claims] 1. An address decoding circuit that decodes an input address signal, a memory cell column selected by a selection signal from the address decoding circuit, and an output of the selected memory cell column is detected to externally output data. An output circuit for outputting, a selection number detection circuit for detecting that a predetermined memory cell column of the memory cell column has been selected a preset number of times, and the selection number detection circuit is preset. Read out of at least a part of the memory cell columns until it is detected that the selected number of times has been selected, and when the selected number detection circuit detects that the selected number of times has been selected, the selected number of times is selected. A semiconductor memory device comprising: read prohibition means for canceling read prohibition according to an output from a detection circuit. 2. An address decoding circuit that decodes an input address signal, a memory cell column selected by a selection signal from the address decoding circuit, and an output of the selected memory cell column is detected to externally output data. An output circuit for outputting, a selection number detection circuit for detecting that a predetermined memory cell column of the memory cell column has been selected a preset number of times, and the selection number detection circuit is preset. Input of the predetermined input address signal to the address decoding circuit is prohibited until it is detected that the selected number of times has been selected, and the selection number detection circuit detects that the selection number of times has been selected a preset number of times. An address for releasing the prohibition of the input of the predetermined input address signal to the address decoding circuit according to the output from the selection number detection circuit The semiconductor memory device and a power inhibiting circuit. 3. An address decoding circuit that decodes an input address signal, a memory cell column selected by a selection signal from the address decoding circuit, and an output of the output enable signal to detect the output of the memory cell column. An output circuit for outputting data to the outside, a selection number detection circuit for detecting that a predetermined memory cell column of the memory cell column is selected a preset number of times, and the selection number detection circuit, When it is detected that the selection number detection circuit has been selected a preset number of times, the input of the output permission signal to the output circuit is prohibited until it is detected that the selection has been performed a preset number of times. And an output permission signal input inhibition circuit for releasing the inhibition of the input of the output permission signal to the output circuit according to the output from the selection number detection circuit. Storage device. 4. A writable memory cell is provided for storing the number of times of selecting the predetermined memory cell column necessary for canceling the signal input prohibition in the address input prohibition circuit. The semiconductor memory device according to claim 3. 5. A writable memory cell for storing an address of the predetermined memory cell column, the selection frequency of which is detected by the selection frequency detection circuit, is provided.
The semiconductor memory device according to claim 2 or 3. 6. The semiconductor memory device according to claim 4, further comprising a data writing unit for writing arbitrary data to said writable memory cell. 7. A selection number detection signal invalidating circuit for canceling the reading inhibition by the reading inhibition unit regardless of the output signal from the selection number detecting circuit is further provided between the selection number detection circuit and the reading inhibition unit. The semiconductor memory device according to claim 1, further comprising: 8. A selection number detection signal invalid circuit for canceling the signal input inhibition of the address input inhibition circuit regardless of the output signal from the selection number detection circuit between the selection number detection circuit and the address input inhibition circuit. The semiconductor memory device according to claim 2, further comprising: