JP3296184B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit with a mode switching function, and more specifically, with a password function.

[0002]

2. Description of the Related Art At present, various kinds of semiconductor integrated circuits such as a memory, an arithmetic circuit, and a composite circuit thereof are manufactured and used. However, the semiconductor integrated circuit has a protection function for prohibiting free reading and rewriting of internal data. There is nothing.

[0003]

As the functions of semiconductor integrated circuits have become more sophisticated, there have been cases where it is desired to prohibit free reading and rewriting of internal data. For example, if an integrated circuit having a ROM in which a program for circuit inspection is written and the circuit inspection function is not to be used by anyone except a specific person, an electrically rewritable EEPROM is available.
This is the case where the OM is an OM and the supplier writes data, and the normal user wants to prohibit free rewriting of the data.

The present invention has been made in view of the above circumstances, and has a built-in protection circuit for prohibiting reading or writing of at least a part of an internal circuit, and is capable of inputting a predetermined password without adding a special external terminal. It is an object of the present invention to provide a semiconductor integrated circuit capable of releasing the protection. Another object of the present invention is to provide a semiconductor integrated circuit capable of switching operation modes by inputting switching code data without adding a special external terminal.

[0005]

SUMMARY OF THE INVENTION The present invention has a plurality of input terminals and output terminals, and a control terminal for controlling activation of an internal circuit, and reads or writes at least a part of the internal circuit. A semiconductor integrated circuit having a built-in protection circuit, wherein the protection circuit is configured to receive a plurality of bits from an input terminal of a predetermined combination among the plurality of input terminals in response to an input over a plurality of bits.
Detecting means for detecting a match / mismatch of a plurality of bits, wherein
Data holding means for temporarily holding detection output data of the detection means for a plurality of inputs, and detecting that the detection output data held by the data holding means has a predetermined arrangement to release protection. Determination means for performing the determination.

More specifically, in the present invention , the determining means is a path setting means for detecting that the detected output data is in a predetermined arrangement, and the control input of the control terminal is at a first level. The gate means for outputting a protection release signal when the detection output of the path setting means is in a predetermined arrangement, and controlling the gate means by a control input of the control terminal and the protection release signal, control input is constituted by a locking means for holding the output state of the protect release signal to switch to a second level different from the first level.

The present invention further comprises a first operation mode and a second operation mode.
Semiconductor integrated circuit having an operation mode of
Detecting means for detecting that switching code data of a combination not used in the first operation mode has been input from an external input terminal commonly used in the operation mode and the second operation mode; Data holding means for holding the obtained detection output data, and mode determination for determining that the detection output data held in the data holding means has a predetermined arrangement and setting the second operation mode Means.

According to the present invention, there is provided a protect mode in which reading or writing of at least a part of the internal circuit is prohibited, and the protection can be released by inputting a predetermined password without adding an extraneous external terminal, and the specific data can be released. A semiconductor integrated circuit capable of preventing confidentiality and preventing data from being freely rewritten by a user can be obtained. Further, according to the present invention, the above-described protect mode and unprotect mode are more generally referred to as a first operation mode and a second operation mode, and the second operation mode is input by inputting switching code data which cannot be normally obtained in the first operation mode. The semiconductor integrated circuit provided with the password function can be obtained by making the arrangement of the switching code data secret by enabling the switching to the operation mode.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a logic operation semiconductor integrated circuit (LSI) 1 according to an embodiment of the present invention. The main internal circuit of this LSI 1 is a logical operation circuit 2
And at least a power supply terminal (VDD), a ground terminal (VSS), a control terminal (CTRL) for controlling activation of the logical operation circuit 2,
Clock terminal (CLK), data input terminal (IN1 to I
Nn) and data output terminals (OUT1 to OUTm).

[0010] In addition to the logical operation circuit 2 as an internal circuit, an R circuit in which a circuit inspection program for the logical operation circuit 2 is written.
OM3. The data in the ROM 3 is prohibited from being read in the normal operation, and therefore, a protection circuit 4 is built in. The protection circuit 4 can cancel the protection by inputting a specific password only when performing a circuit inspection.

FIG. 2 shows a specific example of the protection circuit 4.
The protection circuit 4 is configured without adding any special terminal other than the terminal originally required as the LSI 1 and is input from a predetermined combination of terminals selected from the plurality of input terminals IN1 to INn. A detection circuit 21 for detecting password data, a data holding circuit 22 for temporarily holding the detection output data sequentially obtained by the detection circuit 21, and a predetermined arrangement of the detection output data held in the data holding circuit 22; The determination circuit 23 (23a to 23a) that determines that the
c).

In the case of the figure, the password data detection circuit 21 detects the three-input “H” level of the IN1, IN2, and IN3 terminals.
It comprises a NAND gate G1 for detecting the match / mismatch of the bell . The data holding circuit 22 includes a shift register SR that sequentially transfers and holds detection outputs of password data input a plurality of times as described later. The shift clock of the shift register SR is NA
The CTRL input is connected to the inverter I1 by the ND gate G2.
Is generated by matching the inverted signal with the CLK input.

A determination circuit 23 for canceling protection is a path setting circuit 23 for detecting that the detection output data held in the shift register SR has become a predetermined array.
a, a gate circuit 23b that extracts a detection output of the path setting circuit 23a when the CTRL input is at the first level (“L” level) and outputs a protection release signal;
Gate circuit 23 by TRL input and protection release signal
b, and a lock circuit 23c that holds the protection release state until the CTRL input switches to the second level (“H” level).

The path setting circuit 23a includes a shift register S
Each stage of R is configured by a predetermined inverter arrangement so as to invert or transfer the data to the next gate circuit 23b without inversion. Specifically, in the case of the figure, two inverters I3 and I4 are arranged to form a path setting circuit 23a, and output data sequentially detected by the detection circuit 21 is "H", "L", "H", "L". Only when "
An output of all "H" indicating that the path has been established is sent to the gate circuit 23b.

The gate circuit 23b includes a path setting circuit 23a
NOR gate array G having each output as one input
4 to G7 and inverters I5 to invert these outputs.
I8 matches the output of inverters I5 to I8 /
It comprises a NAND gate G8 for detecting a mismatch and an inverter I9 for inverting its output. Unless the condition for canceling the protection is satisfied as described later, in a normal state, the gate circuit 23b outputs the protection signal PT
= "L" is output, and the ROM 3 is set in a data reading prohibited state.

When the condition for canceling the protection is satisfied,
The lock circuit 23c that holds the state for a predetermined period includes a NAND gate G3 that detects coincidence between the protect signal PT and the inverted signal of the CTRL input, and an inverter I2 that inverts the output thereof. The control terminals of the NOR gate arrays G4 to G7 of 23b are provided.

The operation of the protection circuit 4 configured as described above will be described with reference to FIG. As shown in FIG.
When RL = “L”, the LSI 1 is activated. In the normal operation of the LSI 1, the protection signal is PT = "L" and the ROM 3 is kept inactive. When the circuit inspection is required, the input terminal I is set in the state of CTRL = "L".
Using N1 to IN3, password data C1 to C4 are sequentially input as shown in FIG. 3, and a clock is simultaneously introduced from the CLK terminal.

In the case of this embodiment, the password data C1
~C4, for example, sea urchin'll be shown in Figure 4, C1, C3 is IN
1 to IN3 are all "L", C2 and C4 are IN1 to IN
3 is all "H". At this time, N
The outputs of the AND gate G1 are sequentially "H", "L",
"H" and "L", which are sequentially shifted by the shift register SR.
, The state of the output of the path setting circuit 23a is all "H", that is, the condition of the protection release is satisfied.
This state is detected by NAND gate G8, and PT
= "H" is output. However,
This embodiment using the NAND gate G1 for the detection circuit 21
In the case of, even if C1 and C3 are not all "L",
If the combination is other than “H”,
The condition holds. That is, the protection solution in the case of this embodiment
Strictly speaking, C1 and C3 are all “H” or less.
Outside data and C2 and C4 are all "H"
Holds if

When the condition for canceling the protection is satisfied, the PT
= “H” is fed back to the lock circuit 23c, and the lock circuit 23c outputs “H”.
The signal is input to G7, and while CTRL = “L”, the state of protection release is maintained. R in the unprotected state
OM3 becomes active, and in this state, for example, IN1 to IN
When the test pattern data is input from n, the program data is read from the ROM 3 and the test operation of the circuit according to the program is performed. When CTRL = “H”, the output of the lock circuit 23c becomes “L”, and the protection state returns to PT = “L”.

As described above, according to this embodiment, the ROM
Reference numeral 3 is normally inactive, activated by a password input, and becomes readable. Therefore, it is effective when the general user does not want to know the contents of the circuit inspection of the LSI 1.

The mode of protection may be different from the above embodiment. For example, the ROM 3 is normally activated together with the logical operation circuit 2 to control the operation of the logical operation circuit 2, and the data content of the ROM 3 can be directly read out to the output terminals OUT1 to OUTm and checked by a specific input. However, there are cases where the data content of the ROM 3 is desired to be kept confidential to general users. In such a case, the protection signal PT by the protection circuit 4 is a control signal for preventing or canceling the reading of the data of the ROM 3 to the logical operation circuit 2 without inhibiting the reading to the external output terminal. As a result, it is possible to directly read and check the data in the ROM 3 for the first time by inputting the same password as in the embodiment.
I is obtained.

FIG. 5 shows an LSI 1 according to another embodiment of the present invention.
1 shows a schematic configuration. The main part of the LSI 11 is an EEPROM circuit 12. As an external terminal,
At least a chip enable terminal (CEN), a write enable terminal (WEN), and an address input terminal (A1
An), a power supply terminal (VDD), a step-up potential terminal (VPP) for rewriting, a data output terminal (OUT1 to OUTm), and a ground terminal (VSS).

In addition to the EEPROM circuit 12, the LSI 11 has a built-in protection circuit 13 which normally disables data rewriting of the EEPROM circuit 12 and enables only data reading. This protection circuit 13
Has a circuit configuration similar to that of FIG. 2 of the previous embodiment, for example, and is configured to release protection by inputting a fixed password without adding a special external terminal. In this case, an appropriate combination selected from the A1 to An terminals can be used as the password input terminal, a WEN terminal can be used instead of the CTRL terminal, and an appropriate address terminal can be used instead of the CLK terminal.

With such a configuration, when WEN = "L", that is, in the write enable state, the protection can be released by the same password input and clock input as in the previous embodiment, and the data can be rewritten. While the protection circuit 13 is controlled by inputting a password, VPP
Unless a rewriting step-up potential is applied to the terminal, erroneous writing does not occur. After rewriting data, WE
By setting N = “H”, it returns to the protected state as in the previous embodiment. As described above, according to this embodiment, an EEPROM is obtained in which only a specific person who knows the password can rewrite data.

Although the embodiment of the integrated circuit having the protect mode has been described above, the present invention is not limited to this. For example, the first operation mode is set to the normal mode, and the second operation mode is set to the second mode.
The operation mode is a mode for checking the main circuit or reading specific data. By providing a mode switching circuit having the same configuration as the protection circuit of the above-described embodiment, the password function can be performed without adding an extra external terminal. Can be obtained.

[0026]

As described above, according to the present invention, there is provided a semiconductor integrated circuit having a built-in protection circuit for inhibiting reading or writing of at least a part of an internal circuit and capable of releasing the protection by inputting a certain password. Can be provided.

[Brief description of the drawings]

FIG. 1 shows a configuration of an LSI according to an embodiment of the present invention.

FIG. 2 shows a configuration of a protection circuit of the embodiment.

FIG. 3 is a timing chart for explaining the operation of the protection circuit.

FIG. 4 shows an example of password data of the protection circuit.

FIG. 5 shows a configuration of an LSI according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LSI, 2 ... Logical operation circuit, 3 ... ROM, 4 ... Protect circuit, 11 ... LSI, 12 ... EEPROM circuit,
13 Protect circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/14 G11C 16/06

Claims (3)

(57) [Claims] 1. A semiconductor having a plurality of input terminals and output terminals, and a control terminal for controlling activation of an internal circuit, and having a built-in protection circuit for inhibiting reading or writing of at least a part of the internal circuit. An integrated circuit, wherein the protection circuit is configured to input a plurality of bits from a plurality of input terminals of a predetermined combination among the plurality of input terminals a plurality of times.
Detecting means for detecting a match / mismatch of each of a plurality of bits, data holding means for temporarily holding detection output data of the detection means in response to the plurality of inputs , and detecting detection data held by the data holding means. A semiconductor integrated circuit comprising: a determination unit configured to detect that a predetermined arrangement has been achieved and release protection. 2. The method according to claim 1, wherein the determining unit detects that the detected output data has a predetermined arrangement, and the path setting unit determines that the control input of the control terminal is at a first level. The detection output of the means is in a predetermined array
A gate means for outputting a protection release signal in a case where the control input is switched to a second level different from the first level by controlling the gate means with the control input of the control terminal and the protection release signal. 2. The semiconductor integrated circuit according to claim 1, further comprising: lock means for holding an output state of the protection release signal. 3. The method according to claim 2, wherein the determining means includes a plurality of bits.
A first NAND gate for detecting “H”, wherein the data holding unit detects the first NAND gate;
A shift register that sequentially inputs and outputs data and serially transfers it
, And the said path setting means, for the input over said plurality of times
The detection output of the first NAND gate is predetermined.
"H", "L" when it is arranged that "L" anti the level
Arrange inverters so that they are all turned to “H” state
The gate means is provided for each data passing through the inverter array section.
NOR gates to which data are input,
Detect all “H” states of inverted data of each output of the gate row.
A second NAN for outputting the protection release signal
A D gate, wherein the lock means is configured to output the protection release signal and the control signal.
A signal match is detected and the output of the protection release signal is output.
"H" input to the NOR gate train to maintain the state.
Having a third NAND gate for
The semiconductor integrated circuit according to claim 2 .