GB2129586A - Improvements in or relating to memory systems - Google Patents

Abstract

A memory system comprises a main memory 2 and means, such as a selectable buffer 31, for preventing illicit reading of the memory 2. Auxiliary memories 3, 4 contain data indicative of permitted or illicit sequences of addresses to the main memory, which data are decoded in circuits 35, 36 for disabling the buffer 31 to prevent reading of the memory 2. The contents of the auxiliary memories and the circuitry of the system are not available to a user. The contents of the memory 2 thus cannot be read if the memory is addressed in an incorrect sequence. <IMAGE>

Description

SPECIFICATION Improvements in or relating to memory systems The present invention relates to memory systems, for instance for use in computers.

The proliferation of computers in commercial, industrial, domestic and other applications has led to a similar proliferation in the supply of data, for example programs, for these computers to handle. The generation of this data is often an extremely tedious and time-consuming exercise: consequently the development costs incurred by those involved in generating the data are very high.

Unfortunately, however, it is relatively easy for users of the data to make unauthorized copies of it, allowing subsequent distribution of the data to third parties, or use of the data on computers other than those for which the data was provided.

Unauthorized copying and other use of computer data in this way is a source of very considerable financial loss to those individuals and organizations involved in its preparation.

In the past, several methods have been employed to frustrate unauthorized copying or other use of data in a memory system. For example, in one such system intended to prevent a computer program or copy thereof from being executed on a computer other than that for which it was intended, each computer is provided with an identification code which can be read by program. Programs which are to be protected read this code at some point in their execution. If the identification code does not correspond with a similar code contained within the program, the program terminates.

One of the problems associated with this and many similar systems is that the program can be read by conventional means and analysed. It is a relatively simple matter, either manually or using a disassembler, to detect the part of the program which performs this test and to replace it with instructions which have no such effect, thus creating a trivially modified program which can be copied at will and which will execute on other computers.

Other systems which have been proposed or implemented suffer from various disadvantages, for example: they do not permit the use of interrupts; they do not allow recursive programs; they are inappropriate for computers with multibyte instructions; they do not allow for the storage of constants in the memory system; they do not allow for reentrant programs.

According to the invention, there is provided a memory system as defined in the appended claim 1.

Advantageous embodiments of the invention are defined in the other claims following claim 1.

It is thus possible to provide a memory system whereby copying or other unauthorized use of information in the memory system is rendered exceedingly difficult, time-consuming, and expensive.

According to one aspect of the invention, additional information is stored in the memory system to indicate normal sequences of accesses. During subsequent use of the memory, any departure from these predefined sequences of accesses causes the memory system to enter a "disabled" state.

According to another aspect of the invention, additional information is stored to indicate sequences of accesses to the memory system that should never occur. During subsequent use of the memory system, if such a sequence of accesses takes place, the memory system is caused to enter the "disabled" state.

It is possible to provide such a memory system contained in one integrated circuit device, which, for instance, is pin-compatible with existing, conventional memory systems.

Such a memory system can be used in conjunction with other such memory systems to provide a memory system with increased capacity.

Such a memory system may comprise two or more separate but communicating memory systems with protection against unauthorized use for the composite memory system.

It is possible to provide a memory system in which incorrect access sequences due to malfunction or other abnormal operation of the system are detected.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a first preferred embodiment of the present invention in the form of a read-only memory; Figure 2 illustrates an example of a typical computer program which may be stored in the memory of Fig. 1, together with auxiliary information relating to access sequences to the memory; and Figure 3 is a block diagram of a second preferred embodiment of the present invention in the form of a random-access memory which may be loaded from a separate, external memory system.

The memory system shown in Fig. 1 comprises a main memory 2 and an auxiliary memory divided into two parts A and B (reference nos. 3 and 4). The main and auxiliary memories have a common address bus 1 which constitutes the address input of the memory system. The main memory 2 has a data bus 5 connected to the input of an output buffer 31, whose output 32 forms the output of the memory system.

The output 6 of the auxiliary memory A is connected to a first access sequence verifica tion circuit 35, which comprises a 2-bit shift register 13 whose outputs 14 are connected to the inputs of an AND gate 16. The data input of the shift register 13 is connected to the output 6 of the auxiliary memory 1 and the clock input of the shift register is connected to a line 9 which is connected to the output of a delay element 33. The input 10 of the delay element 33 is connected to a chipselect input of the memory system. A clear input of the shift register 13 is connected to a reset line 12 from the output of a reset generator 37 whose input 11 is connected to the power supply line VCC of the memory system. The generator 37 supplies a signal to the line 12 upon the application of power to the memory system so as to initialize the system.

The auxiliary memory B has an end-key signal output 7 and a key data output 8, both of which are connected to a second access sequence verification circuit 36. The circuit 36 comprises a shift register 20 whose data input is connected to the output 8 of the auxiliary memory B, whose clock input is connected to the line 9, and whose clear input is connected to the line 12. The parallel outputs 19 of the shift register 20 are connected to the address input lines of a read only memory 21 whose output 22 is connected to a first input of an AND gate 23. The second input of the gate 23 is connected to the output 18 of a D-type flip-flop 17. The flip-flop 17 has a data input connected to the output 7 of the auxiliary memory B, a clock input connected to the line 9, and a clear input connected to the line 12.

The outputs 15 and 24 of the first and second verification circuits 35 and 36 are connected to respective inputs of an OR gate 25, whose output 26 is connected to the data input of a D-type flip-flop 27. The flip-flop 27 has a clock input connected to the line 9, a reset input connected to the line 12, and an inverted output connected to the set input of the flip-flop and to a first input 29 of an AND gate 30. The other input of the gate 30 is connected to the chip select line 10. The output 34 of the AND gate is connected to an enable input of the output buffer 31.

The memory system shown in Fig. 1 operates as follows. For the purposes of explanation, it will be assumed that the memory system is a read-only memory containing a program to be executed by a microprocessor or other computer. In particular, this program is stored in the main memory 2 in essentially the usual way and the program instructions in machine code are read out, word by word, on the data bus 5 in response to addresses supplied to the address input of the memory system and, via the address bus 1, to the memory 2. The memory 3, also in the form of a conventional read-only memory, contains "antikey" data, supplied to the output 6 in response to addresses on the address bus 1, for indicating memory access sequences which should never occur consecutively.In particular, when programming the auxiliary memory A, the author of the information will be aware of sequences of memory accesses which should never be followed. It is therefore possible to indicate in the auxiliary memory A a selection of sequences which, if followed, cause the memory system to be disabled.

In the case where the main memory 2 contains a computer program, these sequences of memory accesses could be associated with flow of control instructions. Fig. 2 illustrates a typical sequence of instructions to be performed by the central processing unit of a computer. Detailed explanation of the function of these instructions will not be given as this is not necessary for the purposes of describing the present invention. However, it should be noted that the instruction BSR causes a change in the flow of execution of the program, in particular by causing the computer to access the location named DEST at memory location 43. Thus, during excution of the program contained in the main memory 2, the sequence of addresses accessed by the computer will be 1, 2, 3, 4, 43, 44 ....

As shown in Fig. 2, the auxiliary memory A contains binary "0" at memory locations 1, 2, 3, 43, 44, 45, 46..., but contains binary "1" at addresses 4 and 5. When the program is executed, the output 6 of the auxiliary memory A will remain at logic level "0".

If an attempt is made to read the contents of the main memory 2, for instance by supplying all of the addresses of the memory to the address bus 1 consecutively and in order, then the address 5 would be supplied immediately after the address 4 with the result that two consecutive 1 's will be supplied to the output 6. These 1 's are clocked into the 2-bit shift register 13 by the delayed chip select signal on the line 9, and the two 1 's appearing at the inputs of the AND gate 16 cause a logic level 1 to be supplied via the OR gate 25 to the data input of the flip-flop 28. This signal is clocked into the flip-flop 28 by the delayed chip select signal, so that a logic level zero output is provided at the inverted output.

This logic level is supplied to the asynchronous set input 28, so that the flip-flop is latched in this condition. A logic level zero is thus applied to one input of the AND gate 30 whose output therefore remains at logic level zero so that the output buffer 31 is disabled and no further data is supplied from the memory 2 to the output 32 of the memory system. The memory system thus remains temporarily disabled until power is removed and restored.

The auxiliary memory B contains "key" data as indicated in the column marked AMB in Fig. 2, and "End-Key" data as indicated in the right-hand column in Fig. 2. The key-data is used to indicate memory access sequences which should always occur consecutively.

Thus, provided the computer program illustrated in Fig. 2 is followed when addressing the memory system, the output 8 of the auxiliary memory B will supply a sequence of logic levels 0, 1,0, 1,0, 1, 1, 1, which signals are clocked into the shift register 20, which has eight serially connected stages. The end-key data is simultaneously supplied to the output 7 of the auxiliary memory B and the logic level 1 corresponding to the last bit of the key-data is simultaneously clocked into the flip-flop 17.

The parallel outputs of the shift register 20 are used to address the read-only memory 21 and the address corresponding to the key is programmed to supply logic level "0" at the output 22, whereas all other addresses are programmed to supply logic level "1" at the output. Thus, when the key-data has been clocked in to the shift register 20, the flip-flop 12 supplies an enable signal to the AND gate 23, which thus supplies the logic level from the output of the memory 21 via the OR gate 25 to the data input of the flip-flop 28, where the data is latched by the delayed chip select signal. If the correct key has been entered in the shift register 20, the inverted output of the flip-flop will be at logic level "1" so that the chip select signal on the line 10 is passed through the AND gate 30 to enable the output buffer 31.However, if an incorrect key has been read into the shift register 20, then the flip-flop 28 is latched and the output buffer 31 disabled as described above.

In the case of a computer program containing instructions which cause a change in the flow of execution, resulting in the computer supplying non-consecutive addresses to the memory system, then the auxiliary memories A and B may be programmed with data of the type illustrated in Fig. 2 at one or more of the locations corresponding to a change of flow of execution. However, in the case of computer programs in which no such change in the flow of execution occurs, it is possible for a programmer to write the program in such a way that the execution jumps to non-consecutive locations in the memory system, so as to permit the memory system to operate as described above. The auxiliary memories may also be programmed as described above when the computer supplies non-consecutive addresses to the memory system in order to access data.

In order for the memory system to be protected against illicit reading, an unauthorized user should not have access to the auxiliary memories A and B, and preferably also to the detailed circuitry of the memory system. This may, for instance, be achieved by forming the memory system as a single integrated circuit, for instance monolithically on a single semiconductor chip. In this case, the auxiliary memories A and B may form part of conventional read-only memory components included with the main memory 2. The other parts of the circuitry can easily be integrated on the same chip without substantially affecting the cost of the memory.This has the advantage that "dismantling" of the memory system would be prohibitively uneconomic so that, unless an illicit user could obtain information concerning the memory system from another source, the chances of his being able to read the contents of the main memory 2 by attempting to go through all permutations of address sequences would be vanishingly small. Further, the memory system would benefit from the other advantages inherent in modern integrated circuit technology.

Fig. 3 shows a random access memory comprising a main memory 52 and a content -addressable memory 55, which corresponds to the auxiliary memories A and B of Fig. 1.

The address inputs and data inputs of the memories 52 and 55 are connected to common address and data buses, respectively, which are connected via a decryption device 56 to the address and data inputs 57 and 58 of the memory system. Inverted write enable inputs of the memories 52 and 55 are connected to a common line 54 connected to a read/write input of the memory system. A chip select input of the memory system is connected via a chip select line 59 to a delay element 60. The output data bus 63 of the main memory 52 is connected to the input of an output buffer 77, whose output 58 is connected to the read output of the memory system.For instance, the data input and output of the memory system may be provided with tri-state buffers so as to use a common data line for reading and writing, so as to make the memory system compatible with microprocessors and other computers employing this technique.

The content-addressable memory 55 contains data corresponding to selected decrypted addresses from the decrypting device 56. In particular, if a particular decrypted address corresponds to one of these selected addresses, a signal is provided on a "match" output M and data is presented at an "antikey" output AK, a "key data" output K, and an "end-key" output EK, corresponding to the outputs 6, 8 and 7, respectively, of the auxiliary memories A and B of Fig. 1.

The outputs AK and M of the memory 55 are supplied to a first verification circuit 97 whereas the outputs M, EK and K are supplied to a second verification circuit 98. The first verification circuit 97 contains a shift register 73 with parallel outputs 72 and an AND gate 70 corresponding to the shift register 13, outputs 14, and gate 16 in the verification circuit 35 of Fig. 1. Additionally, the verification circuit 97 has an AND gate 65 whose output 96 is connected to the data input of the shift register 72 and whose inputs 64 and 66 are connected to the outputs AK and M, respectively, of the memory 55. The gate 65 serves to permit the entry of data to the shift register 73 only upon the occurrence of a "match" signal on the output M of the memory 55.Otherwise the verification circuit 97 operates in the same way as the verification circuit 35 of Fig. 1 and will not be described further.

The verification circuit 98 comprises a Dtype flip-flop 75 having an output 88 connected to one input of an AND gate 87, an eight-stage shift register 92 whose parallel outputs 91 are connected to address inputs of a read-only memory 90, and an output 89 of the memory 90 connected to the second input of the gate 87. The operation of these components is essentially the same as that of the corresponding components of the verification circuit 37 in Fig. 1 and will not be described further. Additionally, the verification circuit 98 comprises AND gates 76 and 100 whose outputs 95 and 101, respectively, are connected to the data inputs of the shift register 92 and the flip-flop 75, respectively. A first input of each of the gates 76 and 100 is connected to the output M of the memory 55.

The second inputs of the gates 76 and 100 are connected to the outputs K and EK respectively of the memory 55. Thus, the gates 76 and 100 operate in the same way as the gate 65 to permit entry of data into the shift register 92 and into the flip-flop 75 only upon the occurrence of a "match" signal from the memory 55.

The memory system shown in Fig. 3 also includes a delay element 60 having an output line 69 and a reset generator 93 having an output line 74, all of which operate in the same way as the delay element 33 and reset generator 37 shown in Fig. 1.

The output buffer 77 has an enable input 80 connected via a fusible link 79 and a line 62 to the output of an AND gate 94. The inputs of the gate 94 are connected to the chip select line 59 and to the read/write line 54 of the memory system. A control input 81 for selectively fusing the link 79 is connected to the output of a D-type flip-flop 82 having a clock input connected to the line 69, a reset input connected to the line 74, and d data input connected to the output 85 of an OR gate 84. The gate 84 has inputs 71 and 86 connected to the outputs of the verification circuits 97 and 98, respectively.

In use, external addresses and data are supplied to the decryption device 56, for instance from the central processing unit of a computer or from a direct memory access unit reading data and/or a computer program from, for example, a magnetic disc. The decryption device 56 produces decrypted addresses and data according to an algorithm known to the programmer, and the addresses and data are supplied simultaneously to the main memory 52 and the content-addressable memory 55.

When the memory system is placed in the "write" mode by the presence of a signal of logic level "0" on the read/write input, the memories 52 and 55 are placed in the "write" mode and data may be stored therein. The data to be stored are read into the memory 52 and additional information, for instance of the type illustrated in Fig. 2 and stored in the auxiliary memory A and B of Fig. 1, are simultaneously supplied to the content-addressable memory 55. When a signal of logic level 1 is supplied to the read/write input of the memory system, the memories 52 and 55 operate in the "read" mode so that data corresponding to the decrypted addresses supplied to the memory system are provided on the bus 53 as input to the output buffer 77.

Simultaneously, antikey data, end-key data, and key data are supplied to the verification circuits 97 and 98 from the memory 55. The verification circuits 97 and 98 operate in the same way as the verification circuits 35 and 36, and the result of the verification is supplied via the OR gate 84 to the flip-flop 82. If the sequence of addresses supplied to the memory system is verified by the verification circuits, the fusible link 79 remains intact and the output buffer 77 is enabled by the AND gate 94 in response to the presence of a chip select signal and a read signal at the inputs of the memory system. However, if an incorrect sequence of addresses is supplied to the memory system, the output signal from the or each verification circuit is clocked into the flipflop 82 and the output signal therefrom causes the link 79 to be fused, thus permanently disabling the memory system.

The memory system of Fig. 3 may be integrated on a single chip in the same way as the memory system of Fig. 1 with the corresponding advantages. The use of a contentaddressable memory 55 permits, in certain circumstances, a reduction in the storage space required.

Various modifications may be made within the scope of the invention. For instance, a "start-of-key" signal may be used in place of the "end-key" signal to control verification of the key data from the auxiliary memory. Also, the data contained in the auxiliary memory may be generated automatically, for instance by means of a microprocessor or other computer. Further instead of disabling the data output of the memory system, the memory system may be arranged to modify the address supplied to the main memory so as to prevent illicit copying. Alternatively, the data from the main memory may be modified so as to prevent illicit copying.

Claims (28)

1. A memory system comprising a memory and means for supplying an error signal when a sequence of addresses supplied to the memory differs from a predetermined sequence.

2. A memory system as claimed in claim 1, including means for preventing reading of the memory in response to the error signal.

3. A memory system as claimed in claim 2, in which the supplying means comprises an auxiliary memory, containing or arranged to contain data for indicating the sequence of addresses supplied to the memory, and discriminating means for determining whether data read from the auxiliary memory is indicative of the predetermined sequence.

4. A memory system as claimed in claim 3, in which the address inputs of the memory and of the auxiliary memory are connected together.

5. A memory system as claimed in claim 3 or 4, in which the memory is associated with a computer and includes at least one cell which, in use, is not addressed by the computer after the computer has addressed the cell having the preceding address, the auxiliary memory containing, in a predetermined number of cells whose addresses follow or include and follow each cell corresponding to the said at least one cell of the memory, data of a first type and, in the other cells thereof, data of a second type, the discriminating means being arranged to actuate the preventing means upon detection of the predetermined number of data elements of the first type read from the first auxiliary memory.

6. A memory system as claimed in claim 5, in which the data of first and second types are binary digits of first and second type, respectively.

7. A memory system as claimed in claim 5 or 6, in which the discriminating means comprises a shift register, having a number of cells equal to the predetermined number and an input connected to the auxiliary memory and being arranged to receive a shift pulse for each address supplied to the memory, and decoding means for determining when all of the shift register cells contain data of the first type.

8. A memory system as claimed in claim 7, when dependent on claim 6, in which the first type of binary digit is a "1" and the decoding means is an AND gate whose inputs are connected to the cell outputs of the shift register.

9. A memory system as claimed in claim 8, in which the predetermined number is 2.

10. A memory system as claimed in any one of claims 3 to 9, in which the memory is associated with a computer and the auxiliary memory contains data which, when read in the order of instructions performed by the computer, forms a predetermined data sequence, the discriminating means being actuable when the predetermined data sequence is expected to actuate the preventing means if the data sequence differs from the predetermined data sequence.

11. A memory system as claimed in claim 10, in which the predetermined data sequence is a sequence of binary digits.

12. A memory system as claimed in claim 10 or 11-, in which the discriminating means comprises a shift register, having a number of cells equal to the length of the predetermined data sequence and an input connected to the auxiliary memory and being arranged to receive a shift pulse for each address supplied to the memory, and decoding means for determining when the shift register contains the predetermined data sequence

13. A memory system as claimed in claim 1 2, in which the decoding means comprises a read only memory whose address inputs are connected to the cell outputs of the shift register and which contains first data for disabling the preventing means at the address corresponding to the predetermined data sequence and second data for actuating the preventing means at all other addresses.

14. A memory system as claimed in any one of claims 10 to 13, in which the auxiliary memory contains further data, at the address of the last data of the predetermined data sequence, for actuating the discriminating means.

15. A memory system as claimed in claim 14, in which the further data is a binary digit.

16. A memory system as claimed in claim 15, in which there is provided a gate having a first input connected to the output of the discriminating means and a second input connected to a data latch whose input is connected to receive the further data from the auxiliary memory.

17. A memory system as claimed in any one of claims 3 to 16, in which the auxiliary memory is part of the memory.

18. A memory system as claimed in any one of claims 2 to 17, in which the preventing means is a selectively enablable buffer connected to the output of the memory.

19. A memory system as claimed in claim 18, in which the buffer has an enable input connected via a self-latching bistable circuit to the output of the actuating means.

20. A memory system as claimed in claim 1 8, in which the buffer has an enable input connected via a fusible link to receive enable signals, the output of the actuating means being arranged to fuse the link to actuate the preventing means.

21. A memory system as claimed in any one of the preceding claims, comprising a read only memory.

22. A memory system as claimed in any one of claims 1 to 20, comprising a random access or read/write memory.

23. A memory system as claimed in claim 22, in which address inputs and/or data inputs of the system are provided with decryption means for decrypting encrypted addresses and/or data.

24. A memory system as claimed in any one of the preceding claims, in the form of an integrated circuit.

25. A memory system as claimed in claim 24, integrated on a single semiconductor chip.

26. A memory system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

27. A computer including a memory system as claimed in any one of the preceding claims.

28. A computer as claimed in claim 27, in the form of a microcomputer.