JPH07245390A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a gate oxide film hardly deteriorate and to restrain deterioration of element characteristics by making positive charge hardly flow in a gate oxide film below a gate electrode during ion implantation for source/drain diffusion layer formation. CONSTITUTION:The method for manufacturing a semiconductor device includes a process for forming a resist film 5 on a substrate 1, a process for forming an opening part 5a by patterning the resist film 5, a process for forming an amorphous carbon film 6 all over, a process for introducing ion by ion implantation into the substrate 1 passing through the amorphous carbon film 6 inside the opening part 5a by using the patterned resist film 5 as a mask and a process for removing the amorphous carbon film 6 and the resist film 5 simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, it can be applied to a CMOS transistor or the like in which a PMOS transistor and an NMOS transistor are combined. The present invention relates to a method for manufacturing a semiconductor device, which makes it difficult for + charges to flow in a gate oxide film under a gate electrode when implanting, thereby making it difficult to cause deterioration of the gate oxide film and suppressing deterioration of element characteristics.

In recent years, in a MOS transistor manufacturing method, ion implantation for forming a source / drain diffusion layer is performed in a Si substrate using a gate electrode and a resist as a mask. Therefore, the gate electrode is directly irradiated at the time of ion implantation. In addition to the generated + charges, the + charges stored on the surface of the resist pattern flow. Therefore, the + charge is easily stored in the gate electrode, and the + charge stored in the gate electrode flows to the Si substrate side connected to the ground. At this time, since the + charges pass through the gate oxide film formed under the gate electrode, there is a problem that the gate oxide film is easily deteriorated and the device characteristics are easily deteriorated.

Therefore, when ion implantation for forming the source / drain diffusion layer is performed, it is possible to make it difficult for + charges to flow to the gate oxide film under the gate electrode and prevent deterioration of the gate oxide film. There is a demand for a semiconductor device manufacturing method capable of suppressing deterioration.

[0004]

2. Description of the Related Art FIG. 5 is a diagram showing a conventional method of manufacturing a semiconductor device. Conventionally, first, as shown in FIG.
After the SiO ₂ field oxide film 101 is formed on the Si substrate 100 by the LOCOS method, the Si substrate 100 is thermally oxidized by the thermal oxidation method or the like to form the SiO ₂ gate oxide film 102. Next, as shown in FIG. 5B, after depositing poly-Si on the entire surface by the CVD method or the like, the poly-Si is etched by the RIE method or the like to form the gate electrode 103, and the source / drain diffusion layer is formed by the photolithography technique. A resist pattern 104 for formation is formed, and thereafter, ion implantation for forming a source / drain diffusion layer is performed in the Si substrate 100 using the gate electrode 103 and the resist pattern 104 as a mask, and an annealing treatment is performed to form the source / drain diffusion layer 105. To form. Then, the PSG interlayer insulating film 106 is formed on the entire surface by the CVD method or the like, the interlayer insulating film 106 is etched by the RIE method or the like to form a contact hole 107, and then the contact hole 107 is formed by the sputtering method or the RIE method. By forming the Al wiring layer 108 so as to make contact with the source / drain diffusion layer 105, a semiconductor device as shown in FIG. 5C can be obtained.

In the conventional method for manufacturing a semiconductor device reported in Japanese Patent Laid-Open No. 4-196120, a conductive thin film made of aluminum, a refractory metal, and a barrier metal is formed so as to cover the resist opening, and this conductive film is formed. Ion implantation is performed on the Si substrate through the thin film.

[0006]

As described above, as shown in FIG.
In the conventional method for manufacturing a semiconductor device shown in FIG.
03 and the resist pattern 104 are used as masks to perform ion implantation for forming the source / drain diffusion layers in the Si substrate 100, and the resist pattern 1 is applied to the gate electrode 103 in addition to the + charge generated by direct irradiation during ion implantation.
04 Since the + electric charge accumulated on the surface flows in, the + electric charge is easily accumulated in the gate electrode 103.
Si substrate 100 in which the + electric charge stored in is connected to the ground
Flowing to the side. At this time, since the + charges are formed under the gate electrode 103 and pass through the gate oxide film 102, there is a problem that the gate oxide film 102 is easily deteriorated and the device characteristics are easily deteriorated.

Next, in the conventional method of manufacturing a semiconductor device reported in the above-mentioned Japanese Patent Laid-Open No. 4-196120, the problem of FIG. 5 described above can be solved. There is a problem that it is difficult to simultaneously remove the conductive thin film made of a refractory metal and a barrier metal. Therefore, according to the present invention, when performing ion implantation for forming the source / drain diffusion layer, it is possible to make it difficult for + charges to flow to the gate oxide film under the gate electrode and prevent deterioration of the gate oxide film. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can suppress the deterioration of the semiconductor device, and easily remove the conductive thin film together with the resist after the ion implantation.

[0008]

The invention according to claim 1 is
A step of forming a resist film on a substrate, a step of patterning the resist film to form an opening, a step of forming an amorphous carbon film on the entire surface, and then a step of patterning the resist film. As a mask, and a step of introducing ions into the substrate by passing through the amorphous carbon film in the opening by ion implantation, and then removing the amorphous carbon film and the resist film at the same time. It is characterized by that.

According to a second aspect of the present invention, a step of sequentially forming a resist film and an amorphous carbon film on a substrate, and then a step of patterning the amorphous carbon film and the resist film to form an opening Then, using the patterned amorphous carbon film and resist film as a mask,
The method is characterized by including a step of introducing ions into the substrate in the opening by ion implantation, and then a step of simultaneously removing the amorphous carbon film and the resist film.

According to a third aspect of the present invention, a step of sequentially forming an amorphous carbon film and a resist film on a substrate, a step of patterning the resist film to form an opening, and then a patterning process are performed. A step of introducing ions into the substrate by passing ions through the amorphous carbon film in the opening by ion implantation using the resist film as a mask;
Next, a step of simultaneously removing the resist film and the amorphous carbon film is included.

[0011]

According to the first aspect of the invention, as shown in FIG. 1 of Example 1 described later, the amorphous carbon film 6 is provided with the opening 5.
Since the ion implantation for forming the source / drain diffusion layer is performed in a state where it is formed on the entire surface so as to contact the Si substrate 1 in a, the charges generated on the surface of the amorphous carbon film 6 during the ion implantation are transferred to the opening 5a. Through the amorphous carbon film 6 in contact with the Si substrate 1 therein, the Si substrate 1 connected to the ground can escape to be discharged. For this reason, it is possible to make it difficult for + charges to flow to the gate oxide film 3 under the gate electrode 4 and to prevent the deterioration of the gate oxide film 3, and thus to suppress deterioration of device characteristics. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

In the second aspect of the present invention, as shown in FIG. 2 of the second embodiment described later, ion implantation for forming the source / drain diffusion layer is performed with the amorphous carbon film 6 formed on the resist film 5. Therefore, the charges generated on the surface of the amorphous carbon film 6 during the ion implantation can be discharged through the amorphous carbon film 6 to the Si substrate 1 or the like connected to the ground via the clamp that fixes the wafer edge. Therefore, it is difficult for the positive electrode to flow into the gate oxide film 3 below the gate electrode 4 and the gate oxide film 3
Since deterioration can be made less likely to occur, deterioration of element characteristics can be suppressed. The clamp for fixing the wafer edge during ion implantation can electrically connect the substrate 1 and the amorphous carbon film 6. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

According to the third aspect of the present invention, as shown in FIG. 3 of the third embodiment described later, the amorphous carbon film 6 is made of Si.
Since the ion implantation for forming the source / drain diffusion layers is performed in a state where it is formed on the entire surface so as to be in contact with the substrate 1, the charges generated on the surface of the resist film 5 and the amorphous carbon film 6 during the ion implantation are applied to the Si substrate 1. Through the contacted amorphous carbon film 6, the Si substrate 1 connected to the ground can be discharged and discharged. For this reason, it is possible to make it difficult for the + electrode to flow into the gate oxide film 3 below the gate electrode 4 and to prevent the deterioration of the gate oxide film 3, and thus to suppress the deterioration of the device characteristics. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

In the present invention, as shown in FIG. 4 of Example 4 described later, ion implantation for forming source / drain diffusion layers is performed with an amorphous carbon film 6 formed on the entire surface so as to contact the Si substrate 1. Therefore, the charges generated on the surfaces of the resist film 5 and the amorphous carbon film 6 at the time of ion implantation can be discharged to the Si substrate 1 connected to the ground through the amorphous carbon film 6 in contact with the Si substrate 1 for discharging. For this reason, it is possible to make it difficult for the + electrode to flow into the gate oxide film 3 below the gate electrode 4 and to prevent deterioration of the gate oxide film 3.
It is possible to suppress deterioration of element characteristics. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention. The illustrated example is applied to a method of manufacturing a MOS transistor. In this embodiment, first, as shown in FIG. 1A, Si is formed by the LOCOS method.
After the SiO ₂ field oxide film 2 having a film thickness of about 3000 Å is formed on the substrate 1, the Si substrate 1 is thermally oxidized by a thermal oxidation method or the like to form the SiO ₂ gate oxide film 3 having a film thickness of about 100 Å. Next, after depositing a poly-Si film with a thickness of about 3000 Å on the entire surface by a CVD method or the like, a poly S film is formed by an RIE method or the like.
i is etched to form the gate electrode 4, and then a resist is applied to the entire surface to form a resist film 5 having a film thickness of about 1.2 μm.

Next, as shown in FIG. 1B, the resist film 5 is patterned by a photolithography technique to form an opening 5a. At this time, the opening 5a forms not only an opening for forming the source / drain diffusion layer but also an opening for letting out + charges. Then, amorphous carbon is deposited on the entire surface by a CVD method or the like to form a film thickness 4
An amorphous carbon film 6 having a thickness of about 00Å is formed. At this time, the amorphous carbon film 6 is not only formed in the opening 5a for forming the source / drain diffusion layer, but also
It is also formed in the opening for releasing the + charge. Then, using the patterned resist film 5 and gate electrode 4 as a mask, ions such as As ⁺ are passed through the amorphous carbon film 6 in the opening 5a by ion implantation to form Si.
After being introduced into the substrate 1, annealing is performed at 850 ° C. for about 30 minutes to form the source / drain diffusion layer 7.

Then, the amorphous carbon film 6 and the resist film 5 are removed by wet treatment with hydrofluoric acid or persulfuric acid or dry treatment with O ₃ plasma sublimation, and a PSG interlayer insulating film 8 is formed on the entire surface by a CVD method or the like, and RIE is performed. After forming the contact hole 9 by etching the interlayer insulating film 8 and the gate oxide film 3 by a sputtering method or the like, the sputtering method or the like and R
The Al wiring layer 10 is formed so as to contact the source / drain diffusion layer 7 through the contact hole 9 by the IE method or the like.
By forming the above, a semiconductor device as shown in FIG. 1C can be obtained.

As described above, in this embodiment, the amorphous carbon film 6 is formed on the entire surface so as to be in contact with the Si substrate 1 in the opening 5a for allowing the + charge to escape. Since the ion implantation is performed, the + charges generated on the surface of the amorphous carbon film 6 during the ion implantation are transferred to the Si substrate 1 connected to the ground through the amorphous carbon film 6 in contact with the Si substrate 1 in the opening 5a. Can be discharged and discharged. For this reason, it is possible to make it difficult for + charges to flow to the gate oxide film 3 under the gate electrode 4 and to prevent the deterioration of the gate oxide film 3, and thus to suppress deterioration of device characteristics. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

(Second Embodiment) FIG. 2 shows a second embodiment according to the present invention.
FIG. 6 is a diagram showing a method for manufacturing the semiconductor device of FIG. MO shown
This is a case where the method is applied to a method for manufacturing an S transistor. In this embodiment, first, as shown in FIG.
After the SiO ₂ field oxide film 2 having a film thickness of about 3000 Å is formed on the Si substrate 1 by the method of
The substrate 1 is thermally oxidized to form a SiO ₂ gate oxide film 3 having a film thickness of about 100 Å. Then, after depositing poly-Si to a thickness of about 3000 Å on the entire surface by the CVD method or the like, the poly-Si is etched by the RIE method or the like to form the gate electrode 4. After that, a resist is applied to the entire surface to form a resist film 5 having a film thickness of about 5, and then amorphous carbon is deposited on the resist film 5 by a CVD method or the like to form an amorphous carbon film 6 having a film thickness of about 400 Å.

Next, as shown in FIG. 2B, the opening 1 is formed by patterning the amorphous carbon film 6 and the resist film 5 by the photolithography technique and the RIE method.
1 is formed. Next, the patterned resist film 5
And using the gate electrode 4 as a mask, As is implanted by ion implantation.
After introducing ions such as ⁺ into the Si substrate 1 in the opening 11, annealing is performed at 850 ° C. for about 30 minutes to form the source / drain diffusion layer 7. In addition, at the time of ion implantation,
The wafer edge is fixed by a clamp that electrically connects the substrate 1 and the amorphous carbon film 6.

Then, the amorphous carbon film 6 and the resist film 5 are removed by wet treatment with hydrofluoric acid or persulfuric acid or dry treatment with O ₃ plasma sublimation, and a PSG interlayer insulating film 8 is formed on the entire surface by a CVD method or the like, and RIE is performed. After forming the contact hole 9 by etching the interlayer insulating film 8 and the gate oxide film 3 by a sputtering method or the like, the sputtering method or the like and R
The Al wiring layer 10 is formed so as to contact the source / drain diffusion layer 7 through the contact hole 9 by the IE method or the like.
By forming the above, a semiconductor device as shown in FIG. 2C can be obtained.

As described above, in this embodiment, since the ion implantation for forming the source / drain diffusion layer is performed with the amorphous carbon film 6 formed on the resist film 5, the surface of the amorphous carbon film 6 is subjected to the ion implantation. It is possible to discharge the electric charges generated in the above to the Si substrate 1 and the like connected to the ground through the clamp through the amorphous carbon film 6 and the like. For this reason, it is possible to make it difficult for + charges to flow to the gate oxide film 3 under the gate electrode 4 and to prevent the deterioration of the gate oxide film 3, and thus to suppress deterioration of device characteristics. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

(Third Embodiment) FIG. 3 shows a third embodiment according to the present invention.
FIG. 6 is a diagram showing a method for manufacturing the semiconductor device of FIG. MO shown
This is a case where the method is applied to a method for manufacturing an S transistor. In this embodiment, first, as shown in FIG.
After the SiO ₂ field oxide film 2 having a film thickness of about 3000 Å is formed on the Si substrate 1 by the method of
The substrate 1 is thermally oxidized to form a SiO ₂ gate oxide film 3 having a film thickness of about 100 Å. Then, after depositing poly-Si to a thickness of about 3000 Å on the entire surface by the CVD method or the like, the poly-Si is etched by the RIE method or the like to form the gate electrode 4. After that, amorphous carbon is deposited on the entire surface by a CVD method or the like to form an amorphous carbon film 6, and then a resist is applied on the amorphous carbon film 6 to form a resist film 5 having a film thickness of about 1.2 μmÅ. At this time, the amorphous carbon film 6 is brought into contact with the Si substrate 1 in a region other than the region for forming the source / drain diffusion layer.

Next, as shown in FIG. 3B, the resist film 5 is patterned by a photolithography technique to form openings 5a for forming source / drain diffusion layers. Next, using the resist film 5 and the gate electrode 4 as a mask, ions such as As ⁺ are introduced by ion implantation into the Si substrate 1 through the amorphous carbon film 6 in the opening 5a, and then at 850 ° C. for about 30 minutes. The source / drain diffusion layer 7 is formed by annealing.

Then, the patterned resist film 5 and the amorphous carbon film 6 are removed by wet treatment with hydrofluoric acid or persulfuric acid or dry treatment with O ₃ plasma sublimation, and a PSG interlayer insulating film 8 is formed on the entire surface by a CVD method or the like. After the interlayer insulating film 8 and the gate oxide film 3 are etched by the RIE method or the like to form the contact hole 9,
After the contact hole 9 is formed by etching the interlayer insulating film 8 and the gate oxide film 3 by the sputtering method and the RIE method, the source / drain diffusion layer 7 is formed through the contact hole 9 by the sputtering method and the RIE method. By forming the Al wiring layer 10 so as to make contact,
A semiconductor device as shown in (c) can be obtained.

As described above, in this embodiment, the ion implantation for forming the source / drain diffusion layers is performed with the amorphous carbon film 6 formed on the entire surface so as to contact the Si substrate 1. Resist film 5
Also, the + charges generated on the surface of the amorphous carbon film 6 can be discharged to the Si substrate 1 or the like connected to the ground through the amorphous carbon film 6 that is in contact with the Si substrate 1 and discharged. Therefore, it is difficult for positive charges to flow to the gate oxide film 3 below the gate electrode 4 and the gate oxide film 3 is prevented.
Since deterioration can be made less likely to occur, deterioration of element characteristics can be suppressed. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment according to the present invention.
FIG. 6 is a diagram showing a method for manufacturing the semiconductor device of FIG. MO shown
This is a case where the method is applied to a method for manufacturing an S transistor. In this embodiment, first, as shown in FIG.
After the SiO ₂ field oxide film 2 having a film thickness of about 3000 Å is formed on the Si substrate 1 by the method of
The substrate 1 is thermally oxidized to form a SiO ₂ gate oxide film 3 having a film thickness of about 100 Å. Next, after depositing poly-Si on the entire surface by the CVD method or the like, the poly-Si is etched by the RIE method or the like to form the gate electrode 4. Then CVD
Amorphous carbon is deposited on the entire surface by a method or the like to form an amorphous carbon film 6, and then a resist is applied on the amorphous carbon film 6 to form a resist film 5 having a film thickness of about 1.2 μmÅ. At this time, the amorphous carbon film 6 is also contacted with the Si substrate 1 in a region other than the source / drain diffusion layer forming region.

Next, as shown in FIG. 4B, the resist film 5 and the amorphous carbon film 6 are patterned by the photolithography technique and the RIE method to form the source / source.
An opening 21 for forming the drain diffusion layer is formed. Then, using the resist film 5 and the gate electrode 4 as a mask, ions such as As ⁺ are introduced into the Si substrate 1 in the opening 21 by ion implantation, and then annealed at 850 ° C. for about 30 minutes to perform source / drain diffusion. Form the layer 7.

Then, the patterned resist film 5 and the amorphous carbon film 6 are removed by wet treatment with hydrofluoric acid or persulfuric acid or dry treatment with O ₃ plasma sublimation, and a PSG interlayer insulating film 8 is formed on the entire surface by a CVD method or the like. After the interlayer insulating film 8 and the gate oxide film 3 are etched by the RIE method or the like to form the contact hole 9,
By forming the Al wiring layer 10 so as to be in contact with the source / drain diffusion layer 7 through the contact hole 9 by the sputtering method or the RIE method, the semiconductor device as shown in FIG. 4C can be obtained. it can.

As described above, in this embodiment, the ion implantation for forming the source / drain diffusion layer is performed with the amorphous carbon film 6 formed on the entire surface so as to contact the Si substrate 1 in order to release the + charges. Therefore, the resist film 5 and the amorphous carbon film 6 are formed at the time of ion implantation.
The charge generated on the surface is connected to the Si substrate 1 through the amorphous carbon film 6 and is connected to the ground through Si.
It can be discharged to the substrate 1 or the like and discharged. For this reason,
Since it is possible to make it difficult for + charges to flow to the gate oxide film 3 below the gate electrode 4 and prevent the gate oxide film 3 from being deteriorated, it is possible to suppress deterioration of the device characteristics. Moreover, the amorphous carbon film 6 can be easily removed together with the resist film 5 after the ion implantation.

Although the first to fourth embodiments have been described as applied to the method of manufacturing a MOS transistor, the present invention is not limited to this and is also applied to a method of manufacturing a CMOS transistor, for example. be able to.

[0032]

According to the present invention, when the ion implantation for forming the source / drain diffusion layers is performed, it is difficult for + charges to flow to the gate oxide film under the gate electrode, thereby making it difficult to cause deterioration of the gate oxide film. Therefore, it is possible to suppress deterioration of device characteristics, and it is possible to easily remove the conductive thin film together with the resist after the ion implantation.

[Brief description of drawings]

FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 1 substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 resist film 5a, 11, 21 opening 6 amorphous carbon film 7 source / drain diffusion layer 8 interlayer insulating film 9 contact hole 10 wiring layer

Claims (3)

[Claims] 1. A step of forming a resist film (5) on a substrate (1), then a step of patterning the resist film (5) to form an opening (5a), and then a non-coated surface. A step of forming a crystalline carbon film (6), and then using the patterned resist film (5) as a mask, ions are ion-implanted to pass through the amorphous carbon film (6) in the opening (5a). A method of manufacturing a semiconductor device, comprising: a step of introducing the amorphous carbon film (6) and the resist film (5) into the substrate (1); and a step of simultaneously removing the amorphous carbon film (6) and the resist film (5). 2. A step of laminating a resist film (5) and an amorphous carbon film (6) on a substrate (1), and then patterning the amorphous carbon film (6) and the resist film (5). To form the opening (11), and then using the patterned amorphous carbon film (6) and resist film (5) as a mask, ions are implanted by ion implantation into the substrate in the opening (11). (1) A method of manufacturing a semiconductor device, comprising: a step of introducing the amorphous carbon film (6) and a step of simultaneously removing the resist film (5). 3. A step of sequentially forming an amorphous carbon film (6) and a resist film (5) on a substrate (1), and then patterning the resist film (5) to form an opening (5a). In the step of forming, and then using the patterned resist film (5) as a mask, ions are injected by ion implantation to pass through the amorphous carbon film (6) in the opening (5a) and then in the substrate (1). And a step of simultaneously removing the resist film (5) and the amorphous carbon film (6), the method of manufacturing a semiconductor device.