CN102437027A - Application of amorphous carbon layer to serving as sacrificial layer during ion implantation - Google Patents
Application of amorphous carbon layer to serving as sacrificial layer during ion implantation Download PDFInfo
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- CN102437027A CN102437027A CN2011103661820A CN201110366182A CN102437027A CN 102437027 A CN102437027 A CN 102437027A CN 2011103661820 A CN2011103661820 A CN 2011103661820A CN 201110366182 A CN201110366182 A CN 201110366182A CN 102437027 A CN102437027 A CN 102437027A
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Abstract
The invention relates to application of an amorphous carbon layer to serving as a sacrificial layer during ion implantation. The application comprises the following steps of: providing a silicon wafer, wherein the silicon wafer comprises shallow trench isolations and a liner oxide film positioned between the shallow trench isolations on the surface of the silicon wafer; removing the liner oxide film on the surface of the silicon wafer; depositing the amorphous carbon layer on the surface of the structure; coating photoresist on the amorphous carbon layer, and carrying out graphic ion implantation to form an ion implantation region; and removing the photoresist by using a dry method and stripping the amorphous carbon layer. Due to the processes, the ion implantation region is subjected to multilayer ion implantation by repeating the graphic ion implantation. According to the invention, by adopting the amorphous carbon layer as the sacrificial layer during ion implantation, the amorphous carbon layer regrows in each graphic ion implantation project, and the thickness stability of the amorphous carbon layer used as the sacrificial layer in the silicon wafer during graphic ion implantation is controlled better, therefore the stability of a device is improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of amorphous carbon layer injects the application of sacrifice layer as ion.
Background technology
Semiconductor development at present presents the diversification direction, and System on Chip/SoC (SOC) is a big main flow wherein.This means has multiple operating voltage on same chip, want the grid oxygen of integrated multiple thickness in this type of designing requirement chip production process.In order to reduce shallow trench isolation, just must reduce shallow trench isolation on the technology from the wet etching step before gate oxidation from (STI) marginal trough (divot) as far as possible.Therefore at 0.13 micron below the process node, generally keep liner oxide film (pad oxide) that shallow trench isolation leaves sacrificial oxide layer (scarify oxide) as follow-up ion implantation technology.
Along with day by day dwindling of device size, the degree of depth of injection also equal proportion reduces, and the liner oxidation film thickness change that stays is day by day obvious to injecting influence, has increased the susceptibility of device fluctuation.It is liner oxide film that the photoresist lift off of follow-up repeatedly injection technology also can consume certain thickness silicon dioxide simultaneously, and the amount that consumes is uncontrollable.
Also the someone puts forward to utilize anti-reflecting layer (BARC) conduct in the photoresist to inject sacrifice layer now, but anti-reflecting layer is a kind of relative labile organic material, for the injection of high-energy or high dose, has instable shortcoming equally.
Summary of the invention
The purpose of this invention is to provide the application that a kind of amorphous carbon layer injects sacrifice layer as ion, silicon chip improves the stability of device as the thickness stability of sacrifice layer when graphically injecting with better control, helps the product of scale of mass production high request.
Technical solution of the present invention is the application of a kind of amorphous carbon layer as ion injection sacrifice layer, it is characterized in that, may further comprise the steps:
One silicon chip is provided, and said silicon chip comprises that shallow trench isolation leaves and the liner oxide film of the silicon chip surface between shallow trench isolation leaves;
Remove the liner oxide film of silicon chip surface;
At said structure surface deposition first amorphous carbon layer, the sacrifice layer that said first amorphous carbon layer injects as follow-up ion;
On first amorphous carbon layer, apply first photoresist, photoetching forms first window, through first window silicon chip is carried out ion and injects, and forms first ion implanted region;
Dry method is removed first photoresist and is peeled off first amorphous carbon layer;
At said structure surface deposition second amorphous carbon layer, the sacrifice layer that said second amorphous carbon layer injects as follow-up ion;
On second amorphous carbon layer, apply second photoresist, photoetching forms second window, through second window silicon chip is carried out ion and injects, and forms second ion implanted region, and said first ion implanted region and second ion implanted region are not overlapping;
Dry method is removed second photoresist and is peeled off the second setting carbon-coating;
The above-mentioned technology of repeated using is carried out the injection of multilayer ion to first ion implanted region and second ion implanted region.
As preferably: the thickness of said amorphous carbon layer is the 50-300 dust.
Compared with prior art; Sacrifice layer when the present invention adopts amorphous carbon layer to inject as ion; The characteristic of utilizing the high stability of amorphous carbon layer when ion injects and going photoresist to be prone to peel off in dry method, at each graphical engineering amorphous carbon layer that all regrows that injects, silicon chip is as the thickness stability of sacrifice layer when better having controlled graphical the injection; Thereby improve the stability of device, help the product of scale of mass production high request.
Description of drawings
Fig. 1 is amorphous carbon layer of the present invention injects sacrifice layer as ion a applicating flow chart.
Fig. 2 is the profile of each processing step in the application flow of the present invention.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 shows amorphous carbon layer of the present invention injects sacrifice layer as ion applicating flow chart.
See also shown in Figure 1ly, in the present embodiment, comprise the steps:
In step 101, shown in Fig. 2 a, a silicon chip 200 is provided, said silicon chip 200 comprises that shallow trench isolation leaves 201 and in the liner oxide film 202 on silicon chip 200 surfaces of shallow trench isolation between 201;
In step 102, remove the liner oxide film 202 on silicon chip 200 surfaces;
In step 103; At said structure surface deposition first amorphous carbon layer 203; The sacrifice layer that said first amorphous carbon layer 203 injects as follow-up ion; Obtain structure shown in Fig. 2 b, said first amorphous carbon layer 203 can adopt the APF film (Advanced Pattening Film) of Applied Materials, and the thickness of said first amorphous carbon layer 203 is the 50-300 dust;
In step 104, shown in Fig. 2 c, on amorphous carbon layer 203, apply first photoresist 204, photoetching forms the first window 204a, through the first window 204a silicon chip 200 is carried out ion and injects, and forms the first ion implanted region A;
In step 105, shown in Fig. 2 d, dry method is removed first photoresist 204 and is peeled off first amorphous carbon layer 203;
In step 106; At said structure surface deposition second amorphous carbon layer 205; The sacrifice layer that said second amorphous carbon layer 205 injects as follow-up ion; Obtain structure shown in Fig. 2 e, said second amorphous carbon layer 205 can adopt the APF film (Advanced Pattening Film) of Applied Materials, and the thickness of said second amorphous carbon layer 205 is the 50-300 dust;
In step 107; Shown in Fig. 2 f; On second amorphous carbon layer 205, apply second photoresist 206, photoetching forms the second window 206a, through the second window 206a silicon chip 200 is carried out ion and injects; Form the second ion implanted region B, the said first ion implanted region A and the second ion implanted region B are not overlapping;
In step 108, shown in Fig. 2 g, dry method is removed second photoresist 206 and is peeled off second amorphous carbon layer 205;
In step 109, the above-mentioned technology of repeated using is carried out the injection of multilayer ion to the first ion implanted region A and the second ion implanted region B.
Sacrifice layer when the present invention adopts amorphous carbon layer to inject as ion; Utilize the high stability of amorphous carbon layer when ion injects and remove the characteristic that photoresist is prone to peel off in dry method; At each graphical engineering amorphous carbon layer that all regrows that injects; Silicon chip is as the thickness stability of sacrifice layer when better having controlled graphical inject, thereby improves the stability of device, helps the product of scale of mass production high request.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (2)
1. an amorphous carbon layer is characterized in that as the application that ion injects sacrifice layer, may further comprise the steps:
One silicon chip is provided, and said silicon chip comprises that shallow trench isolation leaves and the liner oxide film of the silicon chip surface between shallow trench isolation leaves;
Remove the liner oxide film of silicon chip surface;
At said structure surface deposition first amorphous carbon layer, the sacrifice layer that said first amorphous carbon layer injects as follow-up ion;
On first amorphous carbon layer, apply first photoresist, photoetching forms first window, through first window silicon chip is carried out ion and injects, and forms first ion implanted region;
Dry method is removed first photoresist and is peeled off first amorphous carbon layer;
At said structure surface deposition second amorphous carbon layer, the sacrifice layer that said second amorphous carbon layer injects as follow-up ion;
On second amorphous carbon layer, apply second photoresist, photoetching forms second window, through second window silicon chip is carried out ion and injects, and forms second ion implanted region, and said first ion implanted region and second ion implanted region are not overlapping;
Dry method is removed second photoresist and is peeled off the second setting carbon-coating;
The above-mentioned technology of repeated using is carried out the injection of multilayer ion to first ion implanted region and second ion implanted region.
2. the application that amorphous carbon layer according to claim 1 injects sacrifice layer as ion, it is characterized in that: the thickness of said first amorphous carbon layer and second amorphous carbon layer is the 50-300 dust.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103661820A CN102437027A (en) | 2011-11-17 | 2011-11-17 | Application of amorphous carbon layer to serving as sacrificial layer during ion implantation |
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| CN2011103661820A CN102437027A (en) | 2011-11-17 | 2011-11-17 | Application of amorphous carbon layer to serving as sacrificial layer during ion implantation |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07245390A (en) * | 1994-03-04 | 1995-09-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR100725711B1 (en) * | 2005-12-28 | 2007-06-07 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device with wet ashing process |
| CN1992227A (en) * | 2005-12-28 | 2007-07-04 | 海力士半导体有限公司 | Method of fabricating semiconductor device with dual gate structure |
| US20090081858A1 (en) * | 2007-09-26 | 2009-03-26 | Shu Qin | Sputtering-Less Ultra-Low Energy Ion Implantation |
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2011
- 2011-11-17 CN CN2011103661820A patent/CN102437027A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07245390A (en) * | 1994-03-04 | 1995-09-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR100725711B1 (en) * | 2005-12-28 | 2007-06-07 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device with wet ashing process |
| CN1992227A (en) * | 2005-12-28 | 2007-07-04 | 海力士半导体有限公司 | Method of fabricating semiconductor device with dual gate structure |
| US20090081858A1 (en) * | 2007-09-26 | 2009-03-26 | Shu Qin | Sputtering-Less Ultra-Low Energy Ion Implantation |
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Application publication date: 20120502 |