JP2002246486A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of two dissimilar kinds of MOS transistor circuits of a gate insulation film, while reducing the number of processes. SOLUTION: In the manufacturing method of a first MOSTr circuit and a second MOSTr circuit, a first gate insulation film is formed in first and second MOSTr circuit formation regions, ion implantation is carried out, by forming a first resist pattern with an opening in an N or PMOSTr formation region of a second MOSTr circuit formation region, a resist film is formed over the entire semiconductor substrate with the first resist pattern, ion implantation is carried out, by processing it to a second resist pattern with an opening in a P or NMOSTr formation region of the second MOSTr circuit formation region, the first and second resist patterns are processed into a pattern having an opening in an N and PMOS formation region of the second MOSTr circuit formation region, a first gate oxide film in the second MOSTr circuit formation region is removed, and a second gate insulation film is formed in the second MOSTr circuit forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device in which various types of MOS transistor circuits are integrated, or in which a nonvolatile semiconductor memory cell array having a floating gate is further integrated.

[0002]

2. Description of the Related Art In recent years,
Along with the nonvolatile semiconductor memory cell array, a logic circuit is mounted on the same chip, and the development and production of a semiconductor device with high added value have been promoted. In this type of semiconductor device, as a peripheral circuit of a memory cell array, a MOS transistor circuit (hereinafter, referred to as a high withstand voltage driving region) constituting a driving circuit for handling a high voltage required for driving a memory cell is provided. A MOS transistor circuit (hereinafter, referred to as a low-withstand-voltage drive region) that constitutes a logic circuit or the like that operates is used. These two types of MOS transistor circuits have different gate insulating film thicknesses and also have different gate structures with the nonvolatile memory cell.
The manufacturing process of the semiconductor device becomes complicated.

[0003] For example, the manufacturing process is briefly described as follows. First, well formation and channel control ion implantation are performed in the high breakdown voltage circuit formation region and the low breakdown voltage circuit formation region of the semiconductor substrate, respectively. Next, a tunnel insulating film is formed in the nonvolatile memory cell formation region, and a floating gate electrode material film is deposited thereon. Further, a slit process for performing separation in the row direction in the memory cell array is performed. An insulating film on the gate electrode is deposited on the obtained semiconductor substrate. Subsequently, etching is performed so that these stacked films are left in the nonvolatile memory cell formation region. After that, a first gate insulating film is formed in the high breakdown voltage circuit formation region. At this time, the first gate insulating film is formed by thermal oxidation to be slightly thinner than required for high breakdown voltage driving. Then, the first gate insulating film is removed by etching in the low withstand voltage circuit formation region, and a thin second gate insulating film is formed again in the low and high withstand voltage circuit formation regions. After that, by performing heat treatment on these gate insulating films, the second gate insulating film is added to the first gate insulating film in the high breakdown voltage circuit formation region, and the first gate insulating film has a desired thickness. Will be formed. continue,
On the obtained substrate, a gate electrode material is deposited, and a control gate in a nonvolatile memory cell forming region and a gate electrode in a high and low withstand voltage circuit forming region are respectively patterned. After that, source / drain regions are formed.

The above-described method for manufacturing a semiconductor device has the following problems. Focusing on a low withstand voltage circuit requiring high speed operation, at least two or more times of forming first and second gate insulating films in a high and low withstand voltage circuit formation region after performing well formation and channel control ion implantation. A thermal oxidation step and a first gate insulating film removing step are performed. Also,
In the nonvolatile memory cell formation region, a high-temperature heat treatment for forming a tunnel insulating film and an insulating film on the gate between the floating gate and the control gate is performed. These steps make it extremely difficult to control the impurity profile of the channel region in the MOS transistor, fail to obtain desired device characteristics, or cause a short channel effect.

In Japanese Patent Application Laid-Open No. H11-284152, desired characteristics are exhibited by two types of MOS transistor circuits having different gate insulating film thicknesses together with these nonvolatile memory cell arrays. A manufacturing method for obtaining device characteristics is disclosed.
In this manufacturing method, first, as shown in FIG. 16, in a state where a sacrificial oxide film 22 is formed on a silicon substrate 21, well formation and channel control are performed in the PMOS and NMOS transistor formation regions of the high breakdown voltage circuit formation region, respectively. Implantation for N-type well 23 and P-type well 2
4 is formed. Next, using a resist pattern (not shown) having a desired shape, the sacrificial oxide film 22 in the memory cell formation region is removed by etching.

Thereafter, as shown in FIG. 17, a tunnel insulating film 26 and a polysilicon film 27 serving as a floating gate electrode material are sequentially deposited in a memory cell forming region to perform isolation in a row direction in the memory cell forming region. Perform slit processing. Further, an insulating film on the gate electrode is
An NO film 28 is deposited. Next, as shown in FIG. 18, these laminated films are left only in the memory cell forming region using a resist pattern 29 having a desired shape, and are etched so that the surface of the silicon substrate 21 is exposed in the high and low withstand voltage circuit forming regions. I do.

Subsequently, as shown in FIG. 19, a first gate insulating film 30 (thickness 13 n) for a high withstand voltage circuit is formed by thermal oxidation.
m). At this time, the first gate insulating film 30
Is formed slightly thinner than the film thickness required for high breakdown voltage driving. Next, as shown in FIGS. 20 and 21, ion implantation is performed using the resist patterns 31 and 32 in order to selectively perform well formation and channel control in the low breakdown voltage circuit formation region. Thereafter, as shown in FIG. 22, the first gate insulating film 30 in the low breakdown voltage circuit forming region is etched away using the resist pattern 33 having a desired shape.

Next, as shown in FIG. 23, a second gate insulating film (8 nm thick) 36 is formed in the low breakdown voltage circuit forming region by high-temperature thermal oxidation. At this time, in the high breakdown voltage circuit formation region, the second gate insulating film 36 is laminated on the first gate insulating film 30, and the gate insulating film 40 is formed. Note that the N-type well 34 and the P-type well 35 in the low breakdown voltage region are formed by the thermal oxidation at this time.
After that, as shown in FIG. 24, a polysilicon film 37 is deposited on the obtained substrate 1 as a gate electrode material.
As shown in FIG. 5, by patterning the polysilicon film 37, the control gate 37 in the memory cell formation region is formed.
a, the gate electrode 37b in the high and low withstand voltage circuit formation region,
37c are formed by patterning, and source / drain regions 38 and 39 are further formed.

In the nonvolatile memory, the element characteristics of the memory cell array region, particularly the insulation characteristics of the insulating film between the floating gate and the control gate, for example, the ONO film are important.
In general, it is known that if many lithography steps are performed on an ONO film, the insulation reliability of the ONO film deteriorates. However, in the above method, focusing on the memory cell array, a step of forming an ONO film on the floating gate and then patterning the ONO film and the polysilicon film, and a step of implanting ions into the PMOS and NMOS transistor regions of the low breakdown voltage circuit formation region, respectively It is necessary to perform a total of four photolithography steps of etching the gate insulating film in the low breakdown voltage circuit formation region. Therefore, the insulating property of the ONO film is deteriorated due to these photolithography steps, and the production yield is reduced.

Further, since a photoresist patterning step for removing the thick gate insulating film formed in the low withstand voltage circuit formation region is required, the number of steps is increased, the manufacturing cost is increased, and the TAT ( Turn Ar
sound time) is delayed. The present invention has been made in view of the above problems, and provides a method of manufacturing a semiconductor device capable of exhibiting desired characteristics in two types of MOS transistor circuits having different gate insulating film thicknesses while reducing the number of steps. It is intended to be.

[0011]

According to the present invention, there is provided a first MOS transistor circuit and a second MOS transistor circuit having a gate insulating film having a thickness different from that of the gate insulating film in the first MOS transistor circuit. A method of manufacturing a semiconductor device having the same on the same semiconductor substrate, comprising:
The first and second MOS transistor circuit formation regions
Forming a gate insulating film, and (b) a second MOS
Forming a first resist pattern having an opening in the NMOS or PMOS transistor formation region of the transistor circuit formation region, and ion-implanting the first resist pattern using the first resist pattern as a mask; Forming a resist film on the entire surface of the semiconductor substrate having the second resist pattern, and processing the resist film into a second resist pattern having an opening in the PMOS or NMOS transistor formation region of the second MOS transistor circuit formation region; (D) ion-implanting using the resist pattern of (1) as a mask; and (d) forming the first and second resist patterns in N
Processing a resist pattern having openings in the MOS and PMOS formation regions, and removing the first gate oxide film in the second MOS transistor circuit formation region using the obtained resist pattern as a mask; and (e) at least The second MOS transistor circuit formation region has the second
Forming a gate insulating film.

Further, according to the present invention, the first MOS transistor circuit and the second MOS transistor circuit having a gate insulating film having a thickness different from that of the gate insulating film in the first MOS transistor circuit are formed on the same semiconductor substrate. A method for manufacturing a semiconductor device provided above, comprising: (a) forming a first gate insulating film in first and second MOS transistor circuit formation regions; and (b ′) forming a second MOS transistor circuit. Forming a first resist pattern having an opening in an NMOS or PMOS transistor forming region of the region, ion-implanting the first resist pattern as a mask, and further using the first resist pattern as a mask to form an NMOS or PMOS transistor; Removing the first gate insulating film in the transistor formation region; and (c ′) removing the first resist pattern. A resist film is formed on the entire surface of the semiconductor substrate having the pattern, and the resist film is processed into a second resist pattern having an opening in the PMOS or NMOS transistor formation region of the second MOS transistor circuit formation region. Ion-implanting using the second resist pattern as a mask, removing the first gate insulating film in the PMOS or NMOS transistor formation region using the second resist pattern as a mask, (e)
At least in the second MOS transistor circuit formation region,
Forming a second gate insulating film.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a so-called logic circuit in which at least a first MOS transistor circuit and a second MOS transistor circuit are mounted. In addition, the semiconductor device manufactured by this method may optionally be
A so-called logic-embedded nonvolatile memory in which a nonvolatile memory cell array and the like are further embedded may be provided.
In the method of manufacturing a semiconductor device according to the present invention, in the step (a), first, a first gate insulating film is formed in first and second MOS transistor circuit formation regions on a semiconductor substrate.

The semiconductor substrate used in the present invention is not particularly limited as long as it is generally used for semiconductor devices. For example, elemental semiconductors such as silicon and germanium, GaAs, InGaAs, ZnS
Various substrates such as a substrate made of a compound semiconductor such as e, an SOI substrate, and a multilayer SOI substrate can be used. Among them, a silicon substrate is preferable. On this semiconductor substrate,
Elements such as LOCOS film, trench oxide film, STI film, etc., transistors, capacitors, resistors, etc., elements such as circuits, interlayer insulating films, wiring layers, etc. are combined to form a single or multi-layer structure. Is also good.

As the first gate insulating film formed in the first and second MOS transistor circuit forming regions, for example, a silicon oxide film (thermal oxide film, low-temperature oxide film: LTO film, etc., high-temperature oxide film: HTO) Film), silicon nitride film, Ta ₂
A single-layer film or a laminated film such as a high-dielectric film such as O ₅ is exemplified. Above all, a silicon oxide film is preferable. The first gate insulating film is formed by a thermal oxidation method, a normal pressure CVD method, a low pressure CVD method,
It can be formed by selecting from various methods such as a plasma CVD method, a sputtering method, and an anodic oxidation method. The thickness can be appropriately set in consideration of its function, the thickness of a second gate insulating film described later, and the like, and includes, for example, about 5 to 50 nm.

In the step (b), a first resist pattern having an opening in an NMOS (or PMOS) transistor formation region in a second MOS transistor circuit formation region is formed, and ion implantation is performed using the first resist pattern as a mask. inject. As a resist for forming a resist pattern, any of a negative type, a positive type, and the like generally used in the field may be used, but a positive type resist is preferable. The resist pattern can be formed into a desired shape by a known method, for example, photolithography and etching technology.

The ion implantation is performed to form a p-well (or n-well) in the second MOS transistor and to control the channel. Ion species, acceleration voltage, in ion implantation for well formation and / or channel control,
The dose and the like can be appropriately selected by a method known in the art. In the case of ion implantation for these purposes, if it is necessary to make the ion species, acceleration voltage, dose, and the like different, ion implantation may be performed a plurality of times, and a mask corresponding to each of them may be used. Forming
Utilization may be used to perform ion implantation a plurality of times. This allows
At least one p-well can be formed in the formation region of the NMOS (or PMOS) transistor, and the impurity concentration of the channel region can be controlled to obtain a desired threshold voltage.

In the step (b '), following the step (b), the first gate insulating film in the NMOS (or PMOS) transistor forming region is removed using the first resist pattern as a mask. . Various methods can be appropriately selected for removing the first gate insulating film depending on the film quality of the gate insulating film, for example, wet etching using hydrofluoric acid, hot phosphoric acid, nitric acid, sulfuric acid, or the like, and RIE.
Dry etching, CMP (chemical mechanical polishing)
And various methods. Of these, wet etching is preferred.

In the step (c), first, a resist film is further formed on the entire surface of the semiconductor substrate having the first resist pattern while the first resist pattern remains, and this resist film is formed on the second substrate. A second resist pattern having an opening in a PMOS (or NMOS) transistor formation region in a MOS transistor circuit formation region is processed. The second resist pattern can be formed in the same manner as the first resist pattern.

Next, ion implantation is performed using the obtained second resist pattern as a mask. The ion implantation here can be performed by the same purpose and method as those performed in the NMOS transistor formation region. In the step (c ′), following the step (c), the PMO is further performed using the second resist pattern as a mask.
The first gate insulating film in the S (or NMOS) transistor formation region is removed. The removal of the first gate insulating film can be performed in the same manner as described above.

In the step (d), the first and second resist patterns are processed into resist patterns having openings in the NMOS and PMOS formation regions of the second MOS transistor circuit formation region, and the obtained resist pattern is processed. The first gate oxide film in the second MOS transistor circuit formation region is removed using the mask as a mask. The processing of the resist pattern can be performed in the same manner as described above. In the second MOS transistor circuit formation region, only the first or second resist pattern is partially formed.
Alternatively, it has a laminated pattern of the first and second resist patterns, but it is preferable to select photolithography conditions and the like that can form a desired pattern by one exposure and development. The removal of the first gate insulating film can be performed in the same manner as described above.

In the step (e), at least the second M
A second gate insulating film is formed in an OS transistor circuit formation region. Here, the second gate insulating film can be formed substantially using the thickness, material, and the like exemplified for the first gate insulating film. The second gate insulating film is
It may be formed only in the second MOS transistor circuit formation region, or may be formed in the first and second MOS transistor circuit formation regions. In this case, in the first MOS transistor circuit formation region, a laminated film in which the second gate insulating film is formed on the already formed first gate insulating film is formed. A membrane can be obtained. Note that in order to make such a laminated structure film function well as a gate insulating film, heat treatment is preferably performed. This heat treatment may use other steps, for example, heat treatment for impurity diffusion, thermal oxidation, or the like. The conditions of the heat treatment include the first and second gate insulating films to be used, the film thickness,
It can be appropriately set according to the performance / characteristics of the MOS transistor to be obtained.

The steps (a) to (e) are suitably performed in this order, but these steps may be changed, and other steps may be advanced before each step is completed. As a result, steps (a) to (e) may be realized as a result. In addition, before, during, and after each step, other ion implantation, formation of electrodes, formation of sidewall spacers, heat treatment, formation of insulating films, formation of contact holes, formation of wiring, etc.
The steps performed in a normal semiconductor process may be arbitrarily performed. For example, when manufacturing a semiconductor device in which a nonvolatile memory cell array is mounted in addition to the first MOS transistor circuit and the second MOS transistor circuit as a semiconductor device, first, before the step (a), Preferably, in the step (i), an element isolation film is formed on the semiconductor substrate, and a memory cell array formation region, a first MOS transistor circuit formation region, and a second MOS transistor circuit formation region are defined. In this case, the element isolation film can be formed by a known method, for example, various methods such as a LOCOS method, a trench isolation method, and an STI method.

After the step (i), a sacrificial oxide film is formed on the entire surface of the semiconductor substrate.
NMO in first MOS transistor circuit formation region
Preferably, ions are implanted into the S and PMOS transistor formation regions, and then the sacrificial oxide film is removed. Examples of the sacrificial oxide film include a silicon oxide film. The film thickness is not particularly limited, and for example, a film thickness capable of protecting the surface of a semiconductor substrate in a semiconductor process. Specifically, about 2 to 50 nm is appropriate. The sacrificial oxide film is formed by, for example, a thermal oxidation method, a normal pressure CVD method,
It can be formed by selecting from various methods such as a low pressure CVD method, a plasma CVD method, and a sputtering method.

The ion implantation performed through the sacrificial oxide film into the formation region of the first MOS transistor circuit is usually performed by the first ion implantation.
By using a mask having an opening in an arbitrary region of the MOS transistor circuit formation region, for example, a PMOS formation region and an NMOS formation region by a photolithography process and utilizing the same, ion implantation can be performed only in a desired region. it can. The ion implantation is mainly performed for well formation and / or channel control.
If it is necessary to make the ion species, acceleration voltage, dose, and the like different, ion implantation may be performed a plurality of times, and masks corresponding to them may be formed,
Utilization may be used to perform ion implantation a plurality of times. This allows
In the region where the NMOS transistor is formed, at least one
One P-well, at least one N-well can be formed in a region for forming a PMOS transistor, and at least one P-well and N-well can be formed in a region for forming a CMOS transistor. For this purpose, the impurity concentration of the channel region can be controlled.

Various methods can be appropriately selected for removing the sacrificial oxide film depending on the film quality and the like. For example, wet etching using hydrofluoric acid, hot phosphoric acid, nitric acid, sulfuric acid, or the like,
Various methods such as a dry etching such as an IE method, a CMP (chemical mechanical polishing) method, and the like can be given. Next, in step (ii), a tunnel oxide film, a conductive film, and an insulating film are formed in this order at least in the memory cell array formation region. Specifically, first, as a step (ii-1), a tunnel oxide film, a conductive film, and an insulating film are formed in this order on the entire surface of the semiconductor substrate.

The tunnel insulating film can be formed by using the same material, forming method and the like as the first and second gate insulating films. The film thickness is, for example, about 2 to 20 nm.
As the conductive film, a material for forming a floating gate can be generally used. For example, silicon such as polysilicon, monosilicon, and amorphous silicon; metals such as platinum, aluminum, copper, and nickel; tantalum, titanium,
Refractory metals such as cobalt and tungsten; and single-layer films or laminated films of silicide with these refractory metals. Above all, a single-layer film of polysilicon, a film made of silicide with a high melting point metal, and a film made of polycide are preferable. When using polysilicon, it is preferable to set a predetermined resistance value by doping with an N-type or P-type impurity when or after forming the polysilicon film. Gate electrode material is sputtering, CVD, vacuum deposition, EB
Film thickness from 50 to 300
It can be formed with a thickness of about nm.

The insulating film is, for example, a silicon oxide film (thermal oxide film, low-temperature oxide film: LTO film, etc.)
HTO film), silicon nitride film, SOG film, PSG film, B
A single-layer film or a laminated film such as an SG film, a BPSG film, a PZT, a PLZT, a ferroelectric film or an anti-ferroelectric film can be given.
Among them, a three-layer structure film of a silicon oxide film / silicon nitride film / silicon oxide film is preferable. The insulating film can be formed by various methods such as a sputtering method, a CVD method, an evaporation method, an EB method, a spin coating method, an MOCVD method, and a sol-gel method. The film thickness can be set according to the function, for example, about 5 to 50 nm.

Next, as a step (ii-2), a resist pattern having openings in the first and second MOS transistor circuit formation regions is formed, and the first and second MOS transistors are formed using this resist pattern as a mask. The substrate surface in the transistor circuit formation region is exposed. That is, all of the tunnel oxide film, the conductive film, and the insulating film formed in the previous step on the first and second MOS transistor circuit formation regions are removed. The removal of these films can be performed by appropriately combining those under appropriate conditions from among the above-described wet etching, dry etching, CMP, and the like. Further, the resist pattern used to expose the substrate surface is preferably stripped by a method known in the art, but the process may proceed to the next step without stripping.

In the present invention, the first and second MOS
The transistor circuit may be of any type as long as the circuit includes transistors having different thicknesses of the gate insulating film. For example, it is appropriate that the first MOS transistor circuit is a so-called high withstand voltage drive circuit and the second MOS transistor circuit is a so-called low withstand voltage drive circuit. Here, the low withstand voltage driving circuit is a circuit having a relatively low operating voltage, such as a signal processing circuit and a memory circuit.
The high withstand voltage drive circuit means a circuit having a higher operating voltage than the low withstand voltage drive circuit. Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

First Embodiment FIGS. 1 to 11 are cross-sectional views showing a manufacturing process of an embodiment in which a method of manufacturing a semiconductor device according to the present invention is applied to a nonvolatile memory with embedded logic. Here, (a), (b) and (c) of each drawing
Shows a memory cell array formation region in the same process, a high breakdown voltage circuit formation region as a first MOS transistor circuit formation region, and a low breakdown voltage circuit formation region as a second MOS transistor circuit formation region. In the case of this embodiment, both the high withstand voltage drive circuit and the low withstand voltage drive circuit
It consists of a MOS circuit.

First, as shown in FIG.
A sacrificial oxide film 2 having a thickness of 10 n is formed on a silicon substrate 1 to be formed.
m. After that, the N-type c
Resist pattern having an opening in the well formation region (not shown)
Is formed, and phosphorus is accelerated to about 1 at an accelerating voltage of about 150 keV.
× 10¹³ions / cm^TwoIon implantation in the order of
You. Subsequently, the P-type well formation region of the high breakdown voltage circuit formation region
Form resist pattern (not shown) with openings in
And boron at an acceleration voltage of about 100 keV to 1 × 10 ¹³i
ons / cm^TwoIon implantation in the order of afterwards,
The resist pattern is removed, and a temperature of about 1200 ° C.
After performing thermal diffusion treatment for about an hour, the N-type well 3 and the P-type
A well 4 is formed.

Next, a resist pattern (not shown) having an opening is formed in the NMOS transistor formation region of the high breakdown voltage circuit formation region, and a proper amount of boron ions are implanted at an acceleration voltage of about 60 keV. Next, a resist pattern (not shown) having an opening in the PMOS transistor formation region is formed. Phosphorus ions are added at an acceleration voltage of about 300 keV to suppress a short channel effect, and boron ions are added to control a threshold value. Is implanted at an acceleration voltage of about 20 keV.

Subsequently, a resist pattern (not shown) having an opening in the memory cell array formation region is formed, and the sacrificial oxide film 2 in the memory cell array formation region is removed by wet etching. Thereafter, as shown in FIG. 2, a tunnel insulating film 6 having a thickness of about 10 nm is formed in the memory cell formation region by thermal oxidation at about 1000 ° C. Further, an n-type polysilicon film 7 serving as a floating gate electrode material is deposited on the entire surface of the obtained silicon substrate 1. Slit processing is performed on the polysilicon film 7 to separate in the row direction in the memory cell formation region. An ONO film 8 is formed thereon as an insulating film on the floating gate. The ONO film 8 is, for example, a silicon oxide film (6
nm), and a silicon nitride film (10 n
m), and a silicon oxide film having a thickness of about 4 nm is converted into a silicon oxide film having a thickness of about 6 nm by a combustion oxidation method to form a silicon oxide film 6 nm / silicon nitride film 6 nm / silicon oxide film 6 nm. It can be formed as a structure.

Thereafter, as shown in FIG. 3, a resist pattern 9 is formed to cover the memory cell array formation region, and the ONO film 8 and the polysilicon film 7 in the high breakdown voltage and low breakdown voltage drive regions are sequentially removed by etching, and further sacrificed. The oxide film 2 is also removed by wet etching to expose the substrate surface in the high breakdown voltage and low breakdown voltage circuit formation regions. Next, as shown in FIG. 4, a first gate insulating film 10 having a thickness of about 13 nm, which becomes a part of the gate insulating film for the high withstand voltage circuit, is formed in the high withstand voltage and low withstand voltage circuit formation regions by thermal oxidation. . At this time, oxidation is added to the ONO film 8 in the memory cell array formation region, but the oxidation rate of the nitride film is suppressed to a negligible level. At this stage, the first gate insulating film 10 is in a state where the thickness is slightly less than a specified thickness, and is added in a gate oxidation step of a low-withstand-voltage circuit formation region described later.

Next, as shown in FIG. 5, a resist pattern 11 having an opening only in the NMOS transistor formation region in the low breakdown voltage circuit formation region is formed, and boron ions are applied to form a well at an acceleration voltage of 300 keV and 150 kV.
eV and 80 keV sequentially switched to 1 × 10 ¹³ / cm ²
Ion implantation at a dose of Subsequently, for channel control, boron ions were accelerated to 20 keV and 1 × 1.
Ion implantation is performed at a dose of 0 ¹³ / cm ² . Then, FIG.
As shown in (2), another resist pattern 12 is formed on the resist pattern 11 with the resist pattern 11 remaining. As a result, the N
In the MOS transistor region, a resist pattern 12 exists as a single layer, and in other regions, a laminated structure of the resist pattern 11 and the resist pattern 12 exists.
Note that the resist patterns 11 and 12 are formed of a positive photoresist having a property of being soluble in a developing solution by one exposure.

Subsequently, using a glass mask (not shown) with a chrome shield plate having an opening only in the PMOS transistor region of the low breakdown voltage circuit forming region, the lower resist pattern 11 and the silicon substrate 1 are formed only in that region. By applying sufficient exposure light to the interface and performing an alkali developing process, the resist pattern 12 is processed into a resist pattern 12 having an opening only in the PMOS transistor region in the low breakdown voltage circuit forming region, as shown in FIG. Using this resist pattern 12, for forming a well, phosphorus ions are accelerated at 800 keV, 500 KeV, and 300 keV.
The ion implantation is performed at a dose of 1 × 10 ¹³ / cm ² by sequentially switching to keV. Subsequently, for channel control, phosphorus ions are implanted at 100 keV at a dose of 1 × 10 ¹³ / cm ² to perform threshold control.

Then, the resist pattern only on the low withstand voltage circuit forming region is removed, and the resist pattern 12 is left on the other regions, and the first gate insulating film of the PMOS transistor region in the low withstand voltage circuit forming region is removed. The film 10 is removed by wet etching. For wet etching, use hydrofluoric acid (HF): ammonium fluoride (N
H ₄ F) is using a mixture of ratio of 1:30 for about 360 seconds. The etching amount is about 15 nm, and the thickness of the already formed first gate insulating film 10 is 13 n.
However, the first gate insulating film 10 is completely removed. Thereafter, as post-processing, resist stripping by sulfuric acid-hydrogen peroxide treatment for about 10 minutes and running water treatment are performed.

Thereafter, heat treatment is performed to form a P-type well 14 and an N-type well 15 in the low breakdown voltage circuit forming region, as shown in FIG. Substrate cleaning by RCA cleaning, which sequentially removes organic substances with sulfuric acid and hydrogen peroxide, removes particles with ammonia and hydrogen peroxide, removes metal impurities with hydrochloric acid and hydrogen peroxide, removes a natural oxide film with dilute hydrofluoric acid, and finally cleans with ultrapure water, A second gate insulating film 16 having a thickness of about 8 nm is formed in the low breakdown voltage circuit formation region by high-temperature thermal oxidation. In this high-temperature thermal oxidation, the thickness of the first gate insulating film 10 already formed in the high breakdown voltage circuit formation region increases,
A gate insulating film 20 having a thickness of about nm is formed. This is a gate insulating film thickness necessary to secure a withstand voltage of about 10 V required for the memory cell drive circuit.

Next, as shown in FIG. 10, a polysilicon film 17 is deposited as a gate electrode material. Subsequently, as shown in FIG. 11, a polysilicon film 17 is patterned in the memory cell formation region to form a control gate 17a, and a polysilicon film is self-aligned with the floating gate 7a in a self-aligned manner, as shown in FIG. Is formed. In the high and low breakdown voltage circuit formation regions, the polysilicon film 17 is patterned to form gate electrodes 17b and 17c having desired gate lengths, respectively,
An n ⁺ diffusion layer and ap ⁺ diffusion layer which become the drain regions 18 and 19 are sequentially formed.

Thereafter, an interlayer insulating film is deposited, and if necessary, metal wirings are provided in multiple layers to complete a logic-embedded nonvolatile memory. According to this embodiment, since another resist pattern is formed and the n-well is formed without removing the resist pattern for forming the p-well in the low breakdown voltage circuit formation region, photolithography accompanying ion implantation is performed. The process can be simplified.

Further, the photolithography process on the surface of the ONO film is performed by using ON and
Removing the O film to form a gate insulating film;
This is only a total of two times including the subsequent step of forming the NMOS transistor and the PMOS transistor in the low breakdown voltage circuit formation region. Therefore, it is possible to minimize deterioration of the reliability of the memory cell array. Second Embodiment First, as in the first embodiment (FIGS. 1 to 4), a tunnel insulating film 6, a polysilicon film 7, an ONO film 8, which is an insulating film on a floating gate, and a high breakdown voltage circuit are formed in a memory cell forming region. An N-type well 3 and a P-type well 4 are formed in a formation region, and a first gate insulating film 10 is formed in a high breakdown voltage and low breakdown voltage circuit formation region.

Next, as shown in FIG. 12, a resist pattern 11 having an opening only in the NMOS transistor formation region of the low breakdown voltage circuit formation region is formed, and the embodiment is formed for well formation and channel control. Like 1,
Ions are implanted. Subsequently, with the resist pattern 11 remaining, the first gate oxide film 10 in the NMOS transistor formation region in the low breakdown voltage circuit formation region is removed by wet etching. This wet etching is performed in the same manner as in the first embodiment. Next, as shown in FIG. 13, another resist pattern 12 is formed on the resist pattern 11 with the resist pattern 11 remaining. Thereby, the NMOS in the low breakdown voltage circuit forming region
In the transistor region, the resist pattern 12 has a single layer, and in other regions, a laminated structure of the resist pattern 11 and the resist pattern 12 exists. In addition,
The resist patterns 11 and 12 are formed of a positive photoresist as in the first embodiment.

Subsequently, as in the first embodiment, as shown in FIG. 14, the resist pattern 12 is processed into a resist pattern 12 having an opening only in the PMOS transistor region in the low breakdown voltage circuit forming region. Using this resist pattern 12, as in the first embodiment, ions are implanted for well formation and channel control. Then, the resist pattern only on the low withstand voltage circuit forming region is removed, and in other regions, the resist pattern 12 is removed.
Is left, the first gate insulating film 10 in the PMOS transistor region in the low breakdown voltage circuit forming region is removed by wet etching. The wet etching is performed in the same manner as in Embodiment 1. As a result, the first gate insulating film 10 on the entire surface of the low breakdown voltage circuit formation region is removed.

Thereafter, heat treatment is performed in the same manner as in the first embodiment, and as shown in FIG. 15, as in the first embodiment, the P-type well 14, the N-type well 15,
A second gate insulating film 16 is formed. Subsequently, a logic-embedded nonvolatile memory is completed according to a normal process.
According to this embodiment, by using one resist pattern as a mask, well formation in the low breakdown voltage circuit formation region and ion implantation for channel control are performed, and at the same time, the gate oxide film in the low breakdown voltage circuit formation region is removed. A resist pattern forming step for newly removing a thick gate oxide film formed in a low breakdown voltage circuit forming region as in the related art is not required, and the TAT can be shortened and the process cost can be reduced.

[0046]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a first MOS transistor circuit and a second MOS transistor circuit on the same semiconductor substrate.
A second resist pattern as a mask used for ion implantation of the NMOS or PMOS transistor formation region on the first resist pattern used for ion implantation of the P or NMOS transistor formation region of the MOS transistor circuit formation region of FIG. By using it, a process for forming a resist pattern can be simplified.

Further, according to the present invention, the first resist pattern used for ion implantation of the P or NMOS transistor formation region of the second MOS transistor circuit formation region is also used as a mask for removing the first gate insulating film. In addition, since the second resist pattern used for the ion implantation of the NMOS or PMOS transistor formation region is also used as a mask for removing the first gate insulating film, the thick gate formed in the low breakdown voltage driving region as in the related art is used. A photoresist patterning step for newly removing the insulating film is not required, and accordingly, the number of photo steps can be reduced, and the TAT and the process cost can be reduced. In addition to the above effects, with the reduction in the number of photo steps, deterioration of the insulation reliability of the insulating film on the gate can be minimized, and a high-performance logic-embedded nonvolatile memory can be manufactured.

In particular, in the case of a semiconductor device in which a memory cell array is mixed, the first and second resistive patterns used for ion implantation in the P and NMOS transistor formation regions in the second MOS transistor circuit formation region are not removed.
By stacking and using the resist pattern used to remove the gate insulating film, the process for forming the resist pattern can be simplified, and the insulating film on the floating gate forming the memory cell array can be formed. Since the number of times of resist application is reduced, deterioration of the insulation reliability of the insulating film on the gate can be minimized with the reduction in the number of photo processes, and a high-performance logic embedded non-volatile memory can be manufactured. Become.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional process diagram for carrying out a method of manufacturing a semiconductor device according to the present invention (first embodiment).

FIG. 2 is a schematic process sectional view for carrying out the method of manufacturing a semiconductor device according to the present invention (first embodiment);

FIG. 3 is a schematic process cross-sectional view for carrying out the semiconductor device manufacturing method of the present invention (Embodiment 1);

FIG. 4 is a schematic cross-sectional process diagram for carrying out the semiconductor device manufacturing method of the present invention (Embodiment 1).

FIG. 5 is a schematic process cross-sectional view for carrying out the semiconductor device manufacturing method of the present invention (Embodiment 1);

FIG. 6 is a schematic process sectional view for carrying out the method of manufacturing the semiconductor device of the present invention (Embodiment 1);

FIG. 7 is a schematic cross-sectional process diagram for carrying out the semiconductor device manufacturing method of the present invention (first embodiment).

FIG. 8 is a schematic process sectional view for carrying out the method of manufacturing the semiconductor device of the present invention (Embodiment 1);

FIG. 9 is a schematic process sectional view for carrying out the method for manufacturing a semiconductor device of the present invention (Embodiment 1);

FIG. 10 is a schematic process sectional view for carrying out the method for manufacturing a semiconductor device of the present invention (Embodiment 1);

FIG. 11 is a schematic process sectional view for carrying out the method of manufacturing the semiconductor device of the present invention (Embodiment 1);

FIG. 12 is a schematic process sectional view for carrying out the method for manufacturing a semiconductor device of the present invention (Embodiment 2);

FIG. 13 is a schematic process sectional view for carrying out the method of manufacturing a semiconductor device of the present invention (Embodiment 2);

FIG. 14 is a schematic process cross-sectional view for carrying out the semiconductor device manufacturing method of the present invention (Embodiment 2);

FIG. 15 is a schematic process cross-sectional view for carrying out the semiconductor device manufacturing method of the present invention (Embodiment 2);

FIG. 16 is a schematic cross-sectional view of a step in a conventional method for manufacturing a semiconductor device.

FIG. 17 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 18 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 19 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 20 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 21 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 22 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 23 is a schematic cross-sectional view of a step in a conventional method for manufacturing a semiconductor device.

FIG. 24 is a schematic cross-sectional view of a step in a conventional method for manufacturing a semiconductor device.

FIG. 25 is a schematic cross-sectional view of a step in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate (semiconductor substrate) 2 sacrificial oxide film 3, 15 n-type well 4, 14 p-type well 5 element isolation film 6 tunnel insulating film 7 polysilicon film (floating gate material film) 7 a floating gate 8 ONO film 9, 11 , 12 resist pattern 10 first gate insulating film 16 second gate insulating film 17 polysilicon film (gate electrode material film) 17a control gate 17b, 17c gate electrode 18, 19 source / drain region 20 gate insulating film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/417 H01L 29/78 371 29/788 29/792 F term (Reference) 4M104 BB01 BB02 BB04 BB05 BB06 BB14 BB17 BB18 BB21 BB22 BB25 BB27 BB28 BB40 CC05 DD34 DD35 DD37 DD43 FF14 GG09 GG10 GG14 GG16 5F048 AA05 AA09 AB01 AC03 BA01 BB05 BB06 BB16 BB18 BE02 BE03 BE04 5F083 EP02 EP23 PR05 JA36 PR35 JA36 PR55 ZA04 ZA05 ZA06 ZA07 ZA08 ZA12 5F101 BA07 BA29 BA36 BB05 BD02 BD10 BD24 BD27 BD36 BD37 BH09 BH21

Claims (7)

[Claims] A first MOS transistor circuit; a first MOS transistor circuit;
A method of manufacturing a semiconductor device having a second MOS transistor circuit having a gate insulating film having a different thickness from a gate insulating film in the MOS transistor circuit of (1) on the same semiconductor substrate, wherein (a) first and second Forming a first gate insulating film in a MOS transistor circuit formation region; and (b) forming an NMO in a second MOS transistor circuit formation region.
Forming a first resist pattern having an opening in the S or PMOS transistor formation region, and ion-implanting using the first resist pattern as a mask; and (c) an entire surface on the semiconductor substrate having the first resist pattern. A resist film is formed on the substrate, and the resist film is formed on the PMOS or NMO of the second MOS transistor circuit formation region.
Processing a second resist pattern having an opening in the S transistor formation region, and ion-implanting using the obtained second resist pattern as a mask; and (d) forming the first and second resist patterns by: NMOS and PMO of the second MOS transistor circuit formation region
Processed into a resist pattern having an opening in the S formation area,
Removing the first gate oxide film in the second MOS transistor circuit formation region using the obtained resist pattern as a mask; and (e) forming a second gate insulating film in at least the second MOS transistor circuit formation region. Forming a film. 2. A first MOS transistor circuit, comprising:
A method of manufacturing a semiconductor device having a second MOS transistor circuit having a gate insulating film having a different thickness from a gate insulating film in the MOS transistor circuit of (1) on the same semiconductor substrate, wherein (a) first and second Forming a first gate insulating film in a MOS transistor circuit formation region; and (b ′) forming an NM in a second MOS transistor circuit formation region.
Forming a first resist pattern having an opening in an OS or PMOS transistor formation region, ion-implanting using the first resist pattern as a mask;
Removing the first gate insulating film in the NMOS or PMOS transistor formation region using the resist pattern as a mask; and (c ′) forming a resist film on the entire surface of the semiconductor substrate having the first resist pattern; The resist film is applied to the second
PMOS or NM in the MOS transistor circuit formation region of
A second resist pattern having an opening in an OS transistor formation region is processed, ions are implanted using the obtained second resist pattern as a mask, and a PMOS or NMOS transistor is formed using the second resist pattern as a mask. Manufacturing a semiconductor device, comprising: removing a first gate insulating film in a region; and (e) forming a second gate insulating film in at least a second MOS transistor circuit formation region. Method. 3. A first MOS transistor circuit and a second MOS transistor circuit.
A method of manufacturing a semiconductor device having a memory cell array in addition to the MOS transistor circuit of (i), further comprising: (i) forming an element isolation film on a semiconductor substrate, forming a memory cell array formation region, and forming a first MOS transistor circuit. 3. A step of defining a region and a second MOS transistor circuit formation region, and (ii) a step of forming a tunnel oxide film, a conductive film and an insulating film in this order at least in a memory cell array formation region. 13. The method for manufacturing a semiconductor device according to item 5. 4. A process (ii) comprising: (ii-1) forming a tunnel oxide film, a conductive film and an insulating film in this order on the entire surface of the semiconductor substrate; and (ii-2) first and second MOSs. Forming a resist pattern having an opening in the transistor circuit formation region, and exposing the substrate surfaces of the first and second MOS transistor circuit formation regions using the resist pattern as a mask. A method for manufacturing a semiconductor device. 5. After the step (i) and before the step (ii), a sacrificial oxide film is formed on the semiconductor substrate, and the NMOS and PMOS transistors in the first MOS transistor circuit formation region are passed through the sacrificial oxide film. 4. The method according to claim 3, wherein the sacrificial oxide film is removed by performing ion implantation on the formation region.
Or the method of manufacturing a semiconductor device according to 4. 6. A second MOS transistor circuit comprising:
The method of manufacturing a semiconductor device according to claim 1, wherein the MOS transistor is a MOS transistor driven at a higher breakdown voltage than the MOS transistor circuit described in claim 1. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the removal of the first gate insulating film is performed by wet etching.