JPH07244993A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain the high speed of writing and erasing operations. CONSTITUTION:This device is provided with a count means 154 for counting the number of the executings of verifying operations and a control means 151 for raising a voltage impressed to memory cells for writings and erasings based on the counted result. Thus, the high speed of writing and erasing operations can be attained by making memory cells reach desired states more quickly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and further to a write / erase technique in the same, and to a technique effective when applied to, for example, a flash memory.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 2-289997 discloses a batch erasing type EEPROM (electrically erasable and programmable read only memory). This collective erasing type EEPROM can be understood in the same meaning as the flash memory in this specification. The flash memory can rewrite information by electrical erasing / writing, and like the EPROM (electrically programmable read only memory), its memory cell can be composed of one transistor. , A function of electrically erasing all of the memory cells or a block of memory cells collectively. Therefore, the flash memory can rewrite the stored information in the state where it is mounted in the system, and the batch erasing function can shorten the rewriting time, and further contributes to the reduction of the chip occupying area. To do.

[0003]

A memory cell of a flash memory has a two-layer structure of a floating gate and a control gate, and is a one-transistor type cell which is almost the same as an EPROM. Writing is performed by applying a high voltage to the control gate and drain and injecting hot electrons generated in the vicinity of the drain junction into the floating gate, as in the EPROM. Also,
Erasing is realized by applying a high voltage to the source, grounding the control gate to 0V, and drawing out electrons in the floating gate to the source by a tunnel phenomenon. If this electron extraction is excessive, a so-called over-erasure (duplication) state is set. The injection of hot electrons into such a cell takes time, and since the target memory cell state is not reached easily, the write operation and verify operation are repeated many times, and the write time of the memory is Will be regulated by the writing time of. Further, when there are overwritten cells, it takes time to extract electrons, and the erase operation and the verify operation are repeated many times. Therefore, the erase time of the memory is the erase time for the bit. Will be regulated by.

An object of the present invention is to speed up writing and erasing operations.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, as the first means, a counting means for counting the number of executions of the verify operation, and a control for increasing the voltage applied to the memory cell for writing or erasing based on the counting result. And means.

As a second means, a counting means for counting the number of executions of the programming or erasing operation, and based on the counting result, for increasing the voltage applied to the memory cell for programming or erasing. A control means is provided.

As a third means, a counting means for counting the number of executions of the verify operation, and the pulse width of the pulse voltage applied to the memory cell for writing or erasing based on the counting result is widened. And a control means for this.

As a fourth means, a counting means for counting the number of times of executing the writing or erasing operation, and a pulse width of a pulse voltage applied to the memory cell for writing or erasing based on the counting result. And a control means for expanding.

[0011]

According to the above means, the control means increases the voltage for writing or erasing or widens the pulse width of the pulse voltage on the basis of the counting result of the counting means, thereby controlling the memory cell. , Reach the desired state sooner. This achieves high speed writing and erasing operations in the semiconductor memory device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a flash memory which is an embodiment of the present invention.

Although not particularly limited, the flash memory shown in FIG. 1 is formed by a known semiconductor integrated circuit on one semiconductor substrate such as single crystal silicon.

In FIG. 1, 10 is a plurality of memory cells M.
S is a memory cell array in which S is arranged in a matrix, and this memory cell array 10 is capable of rewriting information by electrical erasing / writing, and one memory cell is formed by one transistor like an EPROM. Composed. Further, it has a function of electrically erasing a plurality of memory cells MS collectively. In the memory cells MS arranged in a matrix in the X and Y directions, the control gates (selection gates of the memory cells) of the storage transistors arranged in the same row are respectively associated with the corresponding word line W.
The drain regions (memory cell input / output nodes) of the storage transistors connected to 0 to W3 and arranged in the same column are
It is connected to the corresponding data lines D11 to D14. The source regions of the memory transistors forming the memory cell are coupled to the corresponding source lines S11 to S14. The plurality of data lines D11 to D14 and the source lines S11 to D14 correspond to the corresponding column selection switches 16 to.
Via 23, they are coupled to the common data line D and the common source line S, respectively. Column selection switch 16-2
The operation of No. 3 is controlled by column control signals D0 to D3 from the address decoder 11 which will be described later. That is, one of the column control signals D0 to D3 is selectively set to the high level, so that one set of the data line and the source line among the data lines D11 to D14 and the source lines S11 to S14 is selectively made common. It is adapted to be connected to the data line D and the common source line S.

Reference numeral 11 is an input address signal A0-A3.
The address decoder 11 is a row decoder for selecting the word lines W0 to W3, and column selection switches 16 to 23.
It includes a column decoder for switch control. As will be described later, the address signals A0 and A1 are handled as row addresses and are decoded to generate a word line selection signal. Also, address signals A2 and A
3 is treated as a column address, and by decoding it, the selection signals (D0 to D3) of the column selection switches 16 to 23 are generated.

Reference numeral 12 is a data write / erase circuit. This data write / erase circuit 12 has a common data line D,
Via the common source line S, the plurality of memory cells MS
Writing data to and erasing written data. A write / erase execution instruction signal WES and a write / erase selection signal W / E * are input to the data write / erase circuit 12. Write / erase selection signal W / E
When * is high level, the write operation is selected, and when write / erase selection signal W / E * is low level, the erase operation is selected. In addition, write and erase operations
This is made possible by applying a predetermined voltage to the memory cell MS, and the application timing of such a voltage is controlled by the write / erase execution command signal WES.

Reference numeral 13 is a data read circuit, and the data read circuit 13 includes a sense amplifier for taking in the output data of the memory cell via the common data line D and the common source line S and amplifying it. The data read by the data read circuit 13 is DR,
The data is transmitted to the data comparison circuit 14 and can be output to the outside through a buffer circuit or the like.

The data comparison circuit 14 compares the data DW to be written in the memory cell array 10 with the read data DR in order to check whether the data has been written correctly in the data writing to the memory cell array 10. . Here, the read data DR is the data written in the memory cell immediately before the read, and if written correctly, the write data DW and the read data DR match. The comparison result of the data comparison circuit 14 is transmitted to the control circuit 15.

The control circuit 15 includes the data comparison circuit 14 described above.
The operation of the address decoder 11, the data write / erase circuit 12, and the data read circuit 13 is controlled based on the comparison result of 1. The write command signal WRS * (* indicates low active or signal inversion), the clock CLK, and the read command signal RDS * are input from the outside of the memory of this embodiment, and such various control signals are input. Based on, the operation control of each part is performed.

FIG. 2 shows the structure of the memory cell MS.

The stack type flash memory cell has a two-layer structure of a floating gate and a control gate, and is a one-transistor type cell which is almost the same as an EPROM. Writing is performed by applying a high voltage to the control gate and drain and injecting hot electrons generated in the vicinity of the drain junction into the floating gate, as in the EPROM. For erasing, as shown in FIG. 3, while applying a high voltage to the source,
Control gate to 0V (usually low level power supply Vs
(equivalent to s) and grounded, and by tunneling, electrons in the floating gate are extracted to the source. When electrons are drawn from the floating gate,
The threshold Vth seen from the control gate becomes low.

FIG. 4 shows a structural example of the address decoder 11.

As shown in FIG. 4, the address decoder 11 for decoding the fetched address signal includes
A row address decoder 11A for decoding A0 and A1 of the address signals A0 to A3 and A2 and A3
Column address decoder 11B for decoding

The row address decoder 11A is constructed as follows.

Inverters 31, 3 for obtaining complementary levels by inverting addresses A0, A1 respectively.
2 is provided, and two-input AND circuits 33, 34, 35, 36 for obtaining those AND logics are provided. The outputs of the AND circuits 33 to 36 are coupled to the word lines via the n-channel MOS transistors 41 to 44, respectively. n-channel MOS transistor 41
˜44 are turned on when the read command signal RDS is asserted to the high level. Although not shown, the AND circuits 33 to 36 are supplied with the high-level power supply Vdd as their operating power supply. Therefore, the high level at the time of driving the word line at the time of reading is equal to the power supply voltage Vdd.

An n-channel type MOS transistor 45 whose operation is controlled by the write depth signal WDP,
An n-channel type MOS transistor 46 whose operation is controlled by the write / erase selection signal W / E * is provided, and the write depth signal WDP and the write / erase selection signal W / E are provided.
When * is high level, the high voltage Vpp is taken in. Write / erase execution instruction signal WES,
AND circuits 37 to 40 for obtaining AND logic with the logic outputs of the AND circuits 33 to 36 are provided, and n channel type MOS is provided by the logic outputs of the AND circuits 37 to 40.
The operations of the transistors 49 to 52 are controlled. That is, in the state where the write / erase execution command signal WES is asserted to the high level, one of the AND circuits 37 to 40 is set to the high level output according to the AND logic according to the address, and the n channel corresponding thereto is output. The high voltage Vpp is supplied to the word line by turning on the MOS transistors 49 to 52. Further, an n-channel type MOS transistor 48 coupled to the low level power supply Vss and a write / erase selection signal W /
An inverter 47 is provided for inverting E * and transmitting it to the gate electrode of the n-channel MOS transistor 48, and the n-channel MOS transistors 46 and 48 are complementary to each other in response to the write / erase selection signal W / E *. It is designed to be activated.

Further, the column address decoder 11B
Is composed of inverters 53 and 54 for obtaining complementary levels by inverting addresses A2 and A3, and 2-input NAND circuits 55 to 58 for obtaining AND logics thereof. The logical output is column selection switches 16 to 2 as column selection signals.
3 is transmitted.

FIG. 5 shows main functional blocks of the control circuit 15.

As shown in FIG. 5, the control circuit 15 is
Includes, but not particularly limited to, voltage control means 151, write / erase control means 152, verify control means 153, and counting means 154.

The writing / control means 152 writes / writes
Erase execution command signal WES, write / erase selection signal W / E
The operation of the data write / erase circuit 12 is controlled by *. The verify control means 153 controls the verify operation for checking the memory cell state. This verify operation includes write verify for checking the write state of the memory cell immediately after the data write operation to the memory cell, and write verify for checking the erase state of the memory cell immediately after the erase operation. Erase verify is included.

The counting means 154 cumulatively adds the number of times of execution of the verify operation from the control information of the verify control means 153, and transmits the counting result CAL to the voltage control means 151.

The voltage control means 151 is the counting means 15 described above.
The operation of the voltage selection circuit 62 is controlled based on the counting result CAL of 4. In other words, the voltage control unit 151 raises the level of the high voltage applied to the memory cell in the write operation or the erase operation performed after that, when the number of executions of the verify operation reaches a predetermined number. This level increase is not particularly limited, but can be made possible by selecting the voltage output terminal. For example, as shown in FIG. 5, when the high voltage Vpp and the second high voltage Vpp 'which is set slightly higher than the high voltage Vpp are output by the voltage generation circuit 61 incorporated in the flash memory of this embodiment. , A selection switch circuit 62 for selecting the voltage output terminal is provided in the subsequent stage. This selection switch circuit 6
2 is a high voltage Vp output from the voltage generation circuit 61
Alternatively, p and Vpp 'are selected. This selected output is output to the memory cell MS via the word lines W0 to W3 and the source line S.
Can be applied to. Although not particularly limited, Vpp is 1
When set to 0 volts, Vpp 'is 10.5-11
It is regarded as a bolt.

Now, let us consider a case where there are over-erased cells or over-written cells in the memory cell array 10. Although not particularly limited, writing and erasing are performed by a general-purpose PROM writer.

When there is an overerased cell, it takes time to inject hot electrons into the memory cell, so that the number of times the write operation and the verify operation are executed will inevitably increase. Therefore, in the present embodiment, although not particularly limited, when the number of executions of the write operation and the verify operation reaches 10, the existence of an overerased cell is suspected and the voltage control means 15 shown in FIG.
Controls the operation of the selection switch circuit 62 to switch to the second high voltage Vpp 'which is set higher than the previously selected high voltage Vpp. That is,
If the number of times the verify operation is executed reaches 10,
Since the second high voltage Vpp ′ is selected in the subsequent write operation, this second high voltage Vpp ′ is applied to any of the word lines W0 to W3 via the n-channel MOS transistors 45 and 46. Is applied (see FIG. 4). In this way, by using the second high voltage Vpp ′ set higher than the high voltage Vpp used at the time of normal writing, the memory cell continues to use the high voltage Vpp more than when it is used. The desired state is reached quickly.

Erasing is realized by applying a high voltage to the source, grounding the control gate to 0 V, and drawing out electrons in the floating gate to the source by a tunnel phenomenon. If it exists, the number of times the erase operation and the verify operation of the cell are executed will increase. Therefore, in the present embodiment, although not particularly limited, when the number of executions of the erase operation and the verify operation reaches 10, it is suspected that there is an overwritten cell, and as in the case described above, FIG. The voltage control means 15 shown in FIG. 6 controls the operation of the selection switch circuit 62 to replace the high voltage Vpp selected until then with the second high voltage Vpp set higher than that.
Switch to ´. When the second high voltage Vpp ′ is applied to the source, the memory cell continues to have the high voltage Vpp
The desired state is reached sooner than when using pp.

According to the above embodiment, the following operational effects can be obtained.

In writing, when the number of times the verify operation is executed reaches 10, the operation of the selection switch circuit 62 is controlled by the voltage control means 15 to replace the high voltage Vpp selected until then. Since it is switched to the second high voltage Vpp ′ set higher than that,
The memory cell reaches the desired state sooner than if it continues to use the high voltage Vpp. Also, in erasing,
If the number of times the verify operation is executed reaches 10,
The operation of the selection switch circuit 62 is controlled by the voltage control means 15, and instead of the high voltage Vpp selected until then, the second high voltage Vpp set higher than that is set.
Since it is switched to ', the memory cell reaches the desired state sooner than if it continues to use the high voltage Vpp. In this way, the high voltage level for programming or erasing is increased based on the number of times the verify operation is performed, so that the speed of the programming or erasing operation can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the counting means 154
Although the number of verifications is calculated by the above, the number of executions of the write operation or the erase operation may be counted.

In the above embodiment, the high voltage Vpp is
The second high voltage Vpp 'set higher than that is switched to, but the level of this high voltage is kept constant,
Even if the application time of the high voltage is lengthened, the same effect as in the above embodiment can be obtained. That is, since the high voltage is applied in a pulse form in the write or erase operation, the pulse width of this pulse high voltage is controlled according to the counting result of the counting means. For example, the verification count is 10
When reaching the number of times, by increasing the pulse width of the pulse high voltage used for writing or erasing,
The high voltage application time in the subsequent write or erase operation is lengthened. Even if the high voltage application time is lengthened in this way, the same effect as increasing the level of the high voltage as in the case of the above-described embodiment can be obtained.

Furthermore, in the above embodiment, the high voltage Vpp, Vpp 'is generated inside the chip, but the high voltage may be supplied from the outside of the chip.

In the above description, the case where the invention made by the present inventor is mainly applied to the flash memory which is the field of application which is the background of the invention has been described, but the present invention is not limited to this, and for example, EPRO.
The present invention can be applied to the case where the M, the EEPROM, and further such a memory are built in a data processing device such as a microcomputer.

The present invention can be applied under the condition that at least the write and erase operations are repeated.

[0044]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the voltage for writing or erasing is increased or the pulse width of the pulse voltage is widened based on the counting result of the counting means, the memory cell reaches the desired state earlier. It is possible to speed up writing and erasing operations in the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a flash memory that is an embodiment of the present invention.

FIG. 2 is a basic configuration explanatory diagram of a memory cell included in the flash memory.

FIG. 3 is an operation explanatory diagram of a memory cell included in the flash memory.

FIG. 4 is a configuration circuit diagram of a main part of the flash memory.

FIG. 5 is a configuration block diagram of a main part in the flash memory.

[Explanation of symbols]

 10 memory cell array 11 address decoder 12 data write / erase circuit 13 data read circuit 14 data comparison circuit 15 control circuit 61 voltage generation circuit 62 selection switch circuit 151 voltage control circuit 152 write / erase control means 153 verify control means 154 counting means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiichi Yoshida 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (4)

[Claims] 1. A write / erase control means for controlling a write or erase operation by applying a voltage to a memory cell, and a verify control means for controlling a verify operation for checking the state of the memory cell. In a semiconductor memory device in which the write or erase operation and the verify operation are repeated until a desired memory cell state is reached, counting means for counting the number of executions of the verify operation, and a counting means based on the counting result. hand,
A semiconductor memory device comprising: a control unit for increasing a voltage applied to the memory cell for writing or erasing. 2. A write / erase control means for controlling a write or erase operation by applying a voltage to the memory cell, and a verify control means for controlling a verify operation for checking the state of the memory cell. In a semiconductor memory device in which the write or erase operation and the verify operation are repeated until a desired memory cell state is reached, counting means for counting the number of executions of the write or erase operation, and the counting result. And a control means for increasing the voltage applied to the memory cell for writing or erasing. 3. A write / erase control means for controlling a write or erase operation by applying a pulsed voltage to the memory cell, and a verify control means for controlling a verify operation for checking the state of the memory cell. And a counting unit for counting the number of executions of the verify operation in a semiconductor memory device in which the write or erase operation and the verify operation are repeated until a desired memory cell state is reached, and the counting result. And a control means for widening the pulse width of the pulsed voltage applied to the memory cell for writing or erasing. 4. A write / erase control means for controlling a write or erase operation by applying a pulsed voltage to the memory cell, and a verify control means for controlling a verify operation for checking the state of the memory cell. And a counting means for counting the number of executions of the write or erase operation in a semiconductor memory device in which the write or erase operation and the verify operation are repeated until a desired memory cell state is reached. A semiconductor memory device comprising: a control unit for expanding a pulse width of a pulsed voltage applied to the memory cell for writing or erasing based on a counting result.