JPH07244115A - Tester for semiconductor - Google Patents

Abstract

PURPOSE:To commonly use a testing board even if a part number of a semiconductor chip is altered, a package number is the same, and only a disposition pattern of a power terminal according to a power source voltage is altered in the case of inspecting the chip in which circuits having different operating voltages are placed in mixture. CONSTITUTION:A semiconductor chip in which circuits having different operating voltages are placed in mixture is inspected in the state contained in a package. Power source voltages responsive to the voltages of the chip are output from power output terminals A1, A2 of power source voltage supply means 2. Connecting terminals T1, T2, T3 are installed on a testing board 4 corresponding to a disposition pattern of a power terminal B provided at the package according to a power source voltage at each operating voltage of the chip. First connecting terminal groups T1, T2 are individually connected to the terminals A1, A2 of the means 2. The second group T3 is so connected as to be switched to any of the terminals A1, A2 of the means 2 via switching means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip testing apparatus used for inspecting and measuring the electrical characteristics of semiconductor integrated circuits such as ICs and LSIs in which circuits having different operating voltages are mixedly mounted on one chip. is there.

In recent years, in the market, the voltage of equipment has been lowered for the purpose of reducing power consumption and the like, and the operating voltage of ICs, LSIs and the like used in each circuit constituting the equipment has also been lowered. However, at present, all the circuits in the equipment are not unified so that they all operate at low voltage, and a circuit driven at low voltage and a circuit driven at conventional voltage (high voltage) are mixed. It is the current situation. Therefore, a circuit operating at a low voltage and a circuit operating at a high voltage are mixedly mounted on a semiconductor chip such as an IC or an LSI used in such a circuit, and the semiconductor chip is designed to operate with multiple power supplies. .

Usually, semiconductor chips are shipped in the state of being housed in a package, but various inspections such as electric characteristics are performed before the shipment. In order to inspect a semiconductor chip that operates with multiple power supplies, it is necessary to supply a plurality of power supply voltages (for example, two types of low voltage and high voltage) according to the operating voltage, and a test that can supply multiple power supply voltages. The device is in use.

[0004]

2. Description of the Related Art For example, when a semiconductor chip is provided with a circuit which operates with different power supply voltages of 3V and 5V, a power supply for 3V is provided in a large number of terminals (for example, leads) provided in a package that accommodates the semiconductor chip. The terminal (lead) and the 5V power supply terminal (lead) are the I / O for the power supply of the semiconductor chip.
Corresponding to the O ports, they are provided in a predetermined arrangement pattern. The semiconductor chip is inspected by using a test device 33 including a universal test board (hereinafter simply referred to as a test board) 31 and a tester power unit 32, which are shown in a circuit diagram in FIG. During inspection, semiconductor chip 34
The package 35 that accommodates is set on the test board 31. On the test board 31, at a position where the package 35 is set, a large number of connection terminals individually corresponding to all terminals (leads and the like) provided on the package 35 are installed,
Of these connection terminals, the 3V connection terminal e1 and the 5V connection terminal e2 are installed at positions corresponding to the 3V power supply terminal and the 5V power supply terminal of the package 35. That is, the 3V connection terminal e1 and the 5V connection terminal e2 are installed in the same layout pattern as the power supply terminals of the package 35, and when the package 35 is set, the power supply terminals and the connection terminals are for the same voltage. Are connected. Normally, the layout pattern of the power supply terminals is set to a predetermined layout pattern for each package part number so that the same test board 31 can be shared by the semiconductor chips 34 housed in the package 35 having the same part number.

The test board 31 outputs a power supply voltage (3 V and 5 V) corresponding to the operating voltage of the semiconductor chip 34 and is connected to a tester power unit 32 for measuring various electrical characteristics of the semiconductor chip 34. Then, two power supply voltages are supplied from the tester power unit 32 to the package 35 set on the test board 31 through the electrical contact between each connection terminal and each power supply terminal to the semiconductor chip 34 housed in the package 35, The tester power unit 32 measures various electrical characteristics of the semiconductor chip 34. Here, the wiring from each input / output terminal of the tester power unit 32 to each connection terminal provided on the test board 31 is almost in order to prevent generation of noise and voltage drop at the time of inspection and to obtain highly accurate measurement data. It was provided at the shortest distance, and each connection terminal was fixed at a predetermined position on the test board.

[0006]

Therefore, the package 3
Even if the package part numbers are the same due to the difference in the part numbers of the semiconductor chips 34 housed in 5, the power supply terminals (leads, etc.)
When the arrangement pattern for each power supply voltage is different, the test board 31 cannot be shared. for that reason,
The test board had to be produced each time, and the production time and the production cost for producing the dedicated test board became a burden.

For example, in Japanese Laid-Open Patent Publication No. 63-269074, as shown in FIG. 11, power supplies A1, A2, B1 ...
By arranging the relays Y1 to Y12 at the intersections of the matrix of the wiring connecting the terminals X1, X2, X3 ... Of the object to be measured, and operating the relays Y1 to Y12 every time the test changes to form a circuit for the next test. We are trying to simplify the inspection. Applying this method to the test board 31, the tester power unit 32
One of the solutions to the above problems is to provide a wiring in a matrix between the output terminals for each power source and the connection terminals for power source e1 and e2 of the test board 31 and dispose a relay at the intersection of this wiring matrix. Conceivable. According to this method, even if the arrangement pattern of the power supply terminals of the package 35 is changed due to the difference in the semiconductor chips 34 to be inspected, the power supply voltage to the power supply connection terminals e1 and e2 can be changed only by operating the relay. Therefore, the same test board 31 can be shared. However, in consideration of the actual device operation, as the number of switches such as relays arranged at the intersections of the matrix increases, the contact resistance and inductance of the relays increase, resulting in a new problem of being extremely vulnerable to noise. Particularly, in the shipping test, since the IC is often tested at the operation speed of the actual machine level, the influence of noise cannot be ignored when the number of switches such as relays increases.

The present invention has been made in view of the above problems, and an object thereof is to inspect a semiconductor chip in which circuits having different operating voltages are mixedly mounted. It is an object of the present invention to provide a semiconductor chip test apparatus capable of sharing the same test board even when only the arrangement pattern for each power supply voltage is changed.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. As shown in FIG. 1, the power supply voltage corresponding to the operating voltage is applied to the semiconductor chip 1 in which the circuits having different operating voltages are mounted together, and the power supply output terminals A1 and A2 of the power supply voltage supply means 2 are provided.
Is output from. On the test board 4 on which the semiconductor chip 1 is set, connection terminals T1, which can be electrically connected in a layout pattern corresponding to a plurality of power supply terminals B provided in the package 3 for supplying a power supply voltage to the semiconductor chip 1. T
2, T3 are provided. Connection terminals T1, T2, T3
Of the operating voltages of the semiconductor chip 1, the first connection terminal groups T1 and T2 that are electrically connected to a predetermined power supply voltage are:
Each of the power supply output terminals A1 and A2 of the power supply voltage supply means 2 that outputs a power supply voltage corresponding to the operating voltage is connected to each preset power supply voltage. Further, the second connection terminal group T3 that can be selectively conducted to at least two operating voltages of the semiconductor chip 1 has at least two preset connecting terminals of the power supply voltage supplying means 2 via the switching means 5. It is switchably connected to one of the two power output terminals A1 and A2.

[0010]

Therefore, each power supply terminal B of the package 3 set on the test board 4 is electrically connected to each connection terminal T1, T2, T3 provided in a corresponding layout pattern. To the first connection terminal group T1, T2 of the connection terminals T1, T2, T3, a predetermined power supply voltage corresponding to the operating voltage of the semiconductor chip 1 is output from each power supply output terminal of the power supply voltage supply means 2. Further, in the second connection terminal group T3, one of at least two power supply output terminals A1 and A2 preset among the power supply output terminals A1 and A2 of the power supply voltage supply means 2 according to the switching of the switching means 5. The power supply voltage from is output. That is, the second connection terminal group T
3 is switched by the switching operation of the switching means 5 between a state in which at least two power source output terminals A1 and A2 are set in advance, which is in conduction with the power source output terminal A1, and a state in which it is in conduction with the power source output terminal A2. Therefore, by switching the switching means 5, it becomes possible to share this test board among package types that differ only in the power supply voltage value supplied to the power supply terminal B connected to the second connection terminal group T3.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. As shown in FIG.
Is composed of a test board (hereinafter referred to as an FT board) 7, an electrode board 8 and a tester power unit 9 which are arranged to face each other with a predetermined interval. As shown in FIG. 2, the substrate 10 that constitutes the FT board 7 is a disk-shaped multilayer wiring substrate, and the substrate 10 has a 4
A book mounting table 11 is arranged so as to draw four sides of a square. The package 13 that houses the semiconductor chip 12 is
A large number of leads 14 provided on the side surfaces thereof are set on the FT board 7 in a state where their ends are in contact with the upper surface of the mounting table 11. Further, four sockets 15 are installed outside the mounting table 11 so as to surround the mounting table 11.
By operating 5 to move it from the open position (shown in FIG. 2) to the fixed position (shown in FIG. 5), the package 13 is pressed against the socket 15 and the tips (lower ends) of the leads 14 are placed on the upper surface of the mounting table 11. FT board 7 in contact with
It is supposed to be set on top.

As shown in FIG. 3, each mounting table 11 is constructed by arranging the same number of connecting terminals 16 as the number of leads 14 provided on the side surface of the package 13 so as to correspond to each lead 14. When the package 13 is set on the FT board 7, each lead 14 is connected to the socket 1
The connection terminal 16 whose tip corresponds to the pressing force from 5
Each lead 14 and each connection terminal 1 by being pressed against
6 and 6 are surely conducted.

On the semiconductor chip 12 of this embodiment, a circuit having an operating voltage of 3 V (volt) and a circuit having an operating voltage of 5 V (volt) are mixedly mounted. As shown in FIG. 3, of the leads 14 of the package 13 that accommodates the semiconductor chip 12, two near each end and one near the center of each side surface of the package 13.
The book serves as the power supply lead 14a, and the package 13
In total, 12 power supply leads 14a are provided. The 12 power supply leads 14a are set for 5V and 3V, respectively, depending on the connection relationship with the circuit formed on the semiconductor chip 12 in the package 13. Each power supply lead 14a is in contact with the power supply connection terminals t1, t2, t3 among the connection terminals 16 forming the mounting table 11 when the package 13 is set on the FT board 7. The arrangement pattern of the power supply connection terminals t1, t2, t3 is determined to be the same in the package 13 having the same product number and the same package shape and the same number of leads.

Each connection terminal 16 constituting the mounting table 11 is
As shown in FIG. 4, it is connected to a terminal 17 formed on the back surface side of the FT board 7 via a multilayer wiring 10a formed inside the substrate 10. Multilayer wiring 10a between each terminal 17
Each of the power supply connection terminals t1, t2, and t3 that are connected to each other is connected to each other via wirings 18a, 18b, and 18c. That is, all the terminals 17 connected to the power supply connection terminal t1 are connected to each other via the wiring 18a, and all the terminals 17 connected to the power supply connection terminal t2 are connected to each other via the wiring 18b. All of the terminals 17 connected to the connection terminal t3 are connected to each other via the wiring 18c. Further, two electrode terminals 19a and 19b are provided on the back surface of the FT board 7, the electrode terminal 19a is electrically connected to each power supply connection terminal t1, and the electrode terminal 19b is connected to each power supply connection terminal t2.

A relay 21 is arranged on the rear surface of the FT board 7, and the relay 21 has a wiring 18 via the electrode terminals 19a and 19b and a terminal 17 connected to a power supply connection terminal t3.
It is connected to a, 18b, and 18c. Then, the relay 21 is switched and connected to one of the wirings 18a and 18b with respect to the wiring 18c. In FIG. 4, only the wiring from the power supply connection terminals t1, t2, t3 to each terminal 17 and the electrode terminals 19a, 19b is shown, but F
On the back surface of the T-board 7, power supply connection terminals t1, t2, t3
Other electrode terminals for signal input / output (not shown) connected to the respective connection terminals 16 other than the above through multilayer wiring and wiring cords are provided.

As shown in FIG. 5, each electrode terminal 19 is provided on the upper surface of the electrode board 8 arranged below the FT board 7.
Probes 20a and 20b are provided at positions corresponding to a and 19b so as to vertically project upward from the electrode board 8. Each probe 20a, 20b is connected to two power supply output terminals a1, a2 provided in the tester power unit 9, respectively, and when the tester power unit 9 is operating, a predetermined power supply voltage VS1, from each power supply output terminal a1, a2.
VS2 is supplied with power.

A circuit diagram of the power supply system of the test apparatus 6 is shown in FIG.
Shown in. The power supply connection terminals t1 to t3 of the FT board 7 are arranged in a layout pattern as shown in FIG. That is, the power supply connection terminal t1 is the package 13 in FIG.
The power supply connection terminals t3 are arranged corresponding to both end positions on the left and right side surfaces of the package 13, and the power supply connection terminals t3 are arranged corresponding to both end positions on the upper and lower side surfaces of the package 13 in FIG. The power supply connection terminals t2 are connected between the power supply connection terminals t1 and the power supply connection terminals t.
It is arranged corresponding to the center position of each side surface of the package 13 sandwiched between the three.

Each power supply connection terminal t1 is connected to the power supply output terminal a1 of the tester power unit 9, and a voltage VD1 (= VS1) is supplied when the tester power unit 9 operates. Each power supply connection terminal t2 is connected to the power supply output terminal a2 of the tester power unit 9, and the voltage VD2 (= VS2) is supplied when the tester power unit 9 operates. Each power supply connection terminal t3 is connected to each power supply output terminal a1, a2 via the relay 21, and is connected to either one of the power supply output terminal a1 and the power supply output terminal a2 by the switching function of the relay 21. Therefore, the voltage VD3 is supplied when the tester power unit 9 operates. That is, when the relay 21 is in the first switching position shown by the solid line in FIG. 6, the output voltage VS1 is supplied to the power supply connection terminal t3, and the relay 21 is in the second switching position shown by the chain line in FIG. Sometimes the output voltage VS is applied to the power supply connection terminal t3.
2 is supplied.

Further, as shown in FIG. 5, the tester power unit 9 includes a microcomputer MC that executes a predetermined program based on the input data from the input device 9a. The electrode board 8 has a retracted position where the probes 20a and 20b and the electrode terminals 19a and 19b are separated from each other, and an operating position (a state in FIG. 5) where the probes 20a and 20b and the electrode terminals 19a and 19b are brought into contact with each other for conduction. The space between them can be moved and arranged while being parallel to the FT board 7 under the drive control of the microcomputer MC.

The output voltage values VS1 output from the power supply output terminals a1 and a2 based on the input data (for example, product number) of the semiconductor chip 12 input from the input device 9a.
The setting of VS2 and the switching of the relay 21 are automatically performed by the microcomputer MC. Further, the microcomputer MC executes various inspection items programmed in advance.

In the package 13 applied to the FT board 7 of this embodiment, all the power supply leads 14a corresponding to the power supply connection terminal t1 correspond to the power supply connection terminal t2 for the voltage VS1 (for example, 5V). The condition is that all the power supply leads 14a are set for the voltage VS2 (for example, 3V). Then, the power supply lead 14a corresponding to the power supply connection terminal t3 is set for the voltage VS1 (for example, 5V) in FIG. 7A or for the voltage VS2 (for example, 3V).
The package 13 designed according to the concept shown in FIG. 7B set to (for use) is applied to the FT board 7.

Each probe (not shown) for signal input / output provided on the electrode board 8 is connected to an input / output signal terminal (not shown) provided in the tester power unit 9. Further, the wiring from each power supply output terminal a1, a2 to each power supply connection terminal t1 to t3 via each probe 20a, 20b and electrode terminal 19a, 19b is provided so as to pass through a substantially shortest distance, and the wiring is performed. The voltage drop across it is almost negligible.

Next, the operation of the test apparatus 6 constructed as described above will be described. The semiconductor chip 12 is shipped in a state of being housed in a package 13 and sealed. For example, when various tests are performed by the test apparatus 6 before the shipment,
First, the package 13 in which the semiconductor chip 12 is housed is F
Set on T board 7. That is, the package 13 is mounted on the mounting table 11 so that the tips of the leads 14 contact the corresponding connection terminals 16, and in this state the socket 15 is moved from the open position to the fixed position to dispose the package 13. Set on FT board 7. In this set state, all the leads 14 are individually in electrical contact with the respective connection terminals 16 constituting the mounting table 11, and the twelve power supply terminals 14a are respectively corresponding power supply connection terminals t1, t.
2 and t3 are in electrical contact. Then, when the operation of the tester power unit 9 is started, the electrode board 8 in the retracted position is moved to the operating position, and the probes 20a and 20b are brought into contact with the electrode terminals 19a and 19b to be electrically connected.

For example, when inspecting a package 13 designed based on the concept shown in FIG. 7A,
Input data such as the product number of the semiconductor chip 12 housed in the package 13 shown in FIG. 7A is input from the input device 9a provided in the tester power unit 9. as a result,
Based on this input data, the microcomputer MC outputs the output voltage values VS1 and VS from the power supply output terminals a1 and a2.
2 is set to 5V and 3V respectively, and relay 2
1 is placed in the first switching position. When power supply voltages of 5V and 3V are output from the power supply output terminals a1 and a2 of the tester power unit 9, 5V is output to the power supply connection terminals t1 and t3, and 3V is output to the power supply connection terminal t2. It As a result, each power supply lead 14a of the package 13 set on the FT board 7 has the structure shown in FIG.
The power supply voltage as shown in (a) is supplied, and the package 13 designed based on such a concept can be inspected.

Next, when inspecting the package 13 designed based on the concept shown in FIG. 7B, the input device 9a provided in the tester power unit 9 to the package 13 shown in FIG. The input data such as the product number of the semiconductor chip 12 housed in is input. As a result, the microcomputer MC outputs the output voltage values VS1 and VS2 from the power supply output terminals a1 and a2 based on the input data.
Are set to 5V and 3V respectively, and the relay 21
Are arranged in a second switching position. When power supply voltages of 5V and 3V are output from the power supply output terminals a1 and a2 of the tester power unit 9, 5V is supplied to the power supply connection terminal t1 and 3 is supplied to the power supply connection terminals t2 and t3.
V is output. As a result, each power supply lead 14a of the package 13 set on the FT board 7 has the structure shown in FIG.
The power supply voltage as shown in (b) is supplied, and the package 13 designed according to such a concept can be inspected.

Further, by changing the settings of the power supply voltages VS1 and VS2 output from the power supply output terminals a1 and a2 to set the power supply voltage VS1 to 3V and the power supply voltage VS2 to 5V, respectively, as shown in FIG. ) And (b), it is possible to carry out the inspection of the package 13 designed by the concept. For example, when inspecting the package 13 designed by the concept shown in FIG. 8A, the output voltages VS1 and VS2 from the power supply output terminals a1 and a2 are set to 3V and 5V by the microcomputer MC based on the input data. At the same time, the relay 21 is placed in the first switching position. Also, FIG.
Package 1 designed by the concept shown in (b)
3 is inspected, the output voltages VS1 and VS2 from the power supply output terminals a1 and a2 are set to 3V and 5V by the microcomputer MC based on the input data, and the relay 21 is arranged at the second switching position. It Then, the power supply lead 14 of each package 13 designed by the concept shown in FIGS. 8A and 8B.
A predetermined power supply voltage according to the concept is supplied to a.

As described above, in the FT board 7 of this embodiment, the power supply connection terminal t3 is connected to either of the power supply output terminals a1 and a2 by switching the relay 21 by the microcomputer MC. Therefore, by switching the relay 21 between the first switching position and the second switching position, the relay 21 is designed with different concepts shown in FIGS. 7A and 7B depending on the circuit of the semiconductor chip 12 to be housed. The FT board 7 can be shared for the inspection of the two types of packages 13. Therefore, it is not necessary to manufacture the FT board 7 for each package 13 designed according to a different concept, and the material cost, the manufacturing cost, and the manufacturing time of the FT board 7 can be reduced to about half as much as the FT board 7 can be shared. You can

Further, in the present embodiment, the four power supply connection terminals t3 are connected to the power supply output terminals a1 and a1 via the relay 21.
Since a configuration in which 5V and 3V are supplied from a2, one relay 21 is used to provide a plurality of (four) power supply connection terminals t3.
It is possible to change the power supply voltage. Therefore, unlike the inspection device disclosed in Japanese Patent Laid-Open No. 63-269074 described in the prior art, a large number of relays are not used, so that contact resistance and inductance of the relays do not increase. As a result, the cause of erroneous measurement such as voltage drop and noise generation can be eliminated as much as possible. In particular, even when the semiconductor chip 12 is inspected at an actual machine-level operation speed, it is possible to perform the inspection with high accuracy without generating noise that may cause erroneous measurement, by only passing through one relay 21.

Further, in the tester power unit 9 of this embodiment, the setting of the power supply voltages VS1 and VS2 output from the power supply output terminals a1 and a2 can be changed. for that reason,
Inspection of the package 13 designed by two different concepts as shown in FIGS. 8A and 8B by setting the power supply voltages VS1 and VS2 to 3V and 5V, respectively, and switching the relay 21. Can be carried out.

Further, since the wiring distances from the power source output terminals a1 and a2 of the tester power unit 9 to the power source connecting terminals t1 to t3 are set to be almost the shortest distance, noise and voltage drop are eliminated as much as possible, and the accuracy is improved. It is possible to obtain good measurement data. As a result, by inspecting the semiconductor chip 12 with the test device 6, defective products can be reliably excluded. Further, the power supply voltage supplied from the power supply output terminals a1 and a2 of the tester power unit 9 to the power supply connection terminal t3 is switched by the relay 21. Therefore, the microcomputer M is based on the input data.
It becomes possible to drive-control the relay 21 by C.
As a result, the switching of the power supply voltage to the power supply connection terminal t3 can be automatically set based on the input data.

The present invention is not limited to the above embodiments, but can be modified as follows, for example, without departing from the spirit of the invention. (1) As shown in FIG. 9, the test device 6 has two relays 2
3, 24 are provided, and the relay 23 connects the power supply connection terminal t.
3 may be connected to either of the power supply output terminals a1 and a2, and the relay 24 may connect the power supply connection terminal t4 to either of the power supply output terminals a1 and a2. According to this configuration, the FT board 7 can be commonly used for inspection of packages designed with four different concepts by only switching the relays 23 and 24. Also in this case, since the power supply voltages to the plurality of power supply connection terminals t3 and t4 are changed by the relays 23 and 24, respectively, the number of relays 23 and 24 is smaller than the number of power supply connection terminals t3 and t4. Finished, relay 2
No adverse effects such as voltage drop and noise generation due to 3, 24 are exerted.

(2) The switching means is not limited to the relay as long as it has a switching function. For example, the switching circuit may be composed of semiconductor elements such as transistors. Like a relay, a transistor can be driven and controlled by a microcomputer or the like, and since switching does not involve mechanical operation, failure is unlikely to occur and the life of the switching unit can be extended.

(3) The layout pattern of the power supply connection terminals t1 to t3 is not limited to the above embodiment, and may be set appropriately according to the layout pattern of the power supply leads 14a of the package 13 set on the FT board 7. You can

(4) The operating voltage of the semiconductor chip is 3 V and 5
The present invention is not limited to V, and the present invention may be applied to inspection of semiconductor chips that operate at other operating voltages. (5) The operating voltage of the semiconductor chip is not limited to two power sources such as 3V and 5V. The present invention may be applied to the inspection of semiconductor chips having three power sources or multiple power sources.

(6) The number of power supply connection terminals t1 to t3 is not limited to twelve in total, and can be set appropriately according to the number of power supply leads 14a of the package to be inspected. (7) The terminal shape of the package 13 is not limited to the above embodiment. For example, a pin grid array (PGA), a dual in-line package (DIP), a QFJ, or the like may be used, or the terminals may be bumps. Further, the present invention may be applied to TAB inspection.

The technical idea other than the scope of the claims understood from the embodiment will be described below together with its effect. (1) The semiconductor chip test apparatus according to any one of claims 1 to 4, wherein the power supply voltage supply means is capable of changing the setting of the power supply voltage value output from the power supply output terminal.

According to this structure, the output voltage value from each power supply output terminal of the power supply voltage supply means set according to the operating voltage of the semiconductor chip is reset so that the voltage values are replaced with each other, and this test is performed. The device can be commonly used for inspection of semiconductor chips housed in a package having power supply terminals having different arrangement patterns.

(2) The semiconductor chip test apparatus according to any one of claims 1 to 3 or the technical idea (1), wherein the switching means comprises a semiconductor element. According to this structure, since the switching means is made of a semiconductor element, it can be electrically controlled and is not accompanied by a mechanical switching operation, so that a failure is unlikely to occur and the life can be extended.

[0039]

As described in detail above, according to the first and second aspects of the invention, in the inspection of the semiconductor chip in which the circuits having different operating voltages are mounted together, the switching means supplies the connection terminals to the test board. Since the power supply voltage that can be changed can be changed, the test board can be shared even if the semiconductor chip part number changes and only the arrangement pattern of the power supply terminals for each power supply voltage is changed in the same package part number. Produce an effect.

Further, according to the invention described in claim 3, since each output terminal of the power supply voltage supply means and each connection terminal are connected by a short wiring in which a voltage drop between them is almost negligible, The measurement accuracy of the test device can be improved.

Further, according to the invention described in claim 4, since the switch means is a relay, there is an excellent effect that electrical control becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a partial schematic perspective view of a test apparatus according to an embodiment.

FIG. 3 is a partial schematic perspective view of the test apparatus showing a state in which a package is set.

FIG. 4 is a schematic bottom view of a test board.

FIG. 5 is a schematic side view of a test apparatus.

FIG. 6 is a circuit diagram of a test apparatus.

FIG. 7 is a plan view showing an arrangement pattern of power supply leads.

FIG. 8 is a plan view showing an arrangement pattern of power supply leads.

FIG. 9 is a circuit diagram of a test device of another example.

FIG. 10 is a circuit diagram of a conventional test device.

FIG. 11 is a circuit diagram of a conventional test device.

[Explanation of symbols]

 1 semiconductor chip 2 power supply voltage supply means 3 package 4 test board 5 switching means 21, 23, 24 relay A1, A2 power supply output terminal B power supply terminal T1, T2, T3 connection terminal and connection terminal group T1 first connection terminal group and First connection terminal group T2 First connection terminal group and second connection terminal group T3 Second connection terminal group and third connection terminal group

Claims (4)

[Claims] 1. A power supply voltage supply means (2) for supplying a power supply voltage to a semiconductor chip (1) on which circuits operating at different operation voltages are mounted together and having power supply output terminals (A1, A2) for each operation voltage. And a connection terminal (T1, T2, T3) provided in a layout pattern corresponding to the power supply terminal (B) provided for each operating voltage in the package (3) accommodating the semiconductor chip (1). A board (4), wherein the package (3) is the test board (4)
Set to the power supply terminal (B) and the connection terminal (T
1, T2, T3) are electrically connected to each other, the power supply terminal (B) and the connection terminals (T1, T2, T3)
3) A semiconductor chip test apparatus for supplying a power supply voltage according to its operating voltage from the power supply voltage supply means (2) to the semiconductor chip (1) through connection with the connection terminals (T1, T2, T3) is a first connection terminal group (T1, T2) that is electrically connected to any one of the operating voltages of the semiconductor chip (1) and at least two of the operating voltages of the semiconductor chip (1). It is divided into one operating voltage and a second connection terminal group (T3) which can be selectively conducted, and each power output terminal (A1, A2) of the power voltage supply means (2) and a first connection terminal group (T1). , T2) for each preset power supply voltage, and the second connection terminal group (T3) is connected to each power supply output terminal (A1, A1) of the power supply voltage supply means (2) via the switching means (5). At least two preset in A2) Power output terminals (A1, A2)
A semiconductor chip testing device that is switchably connected to any of the above. 2. A plurality of power supply terminals (B) provided for each operating voltage in a package (3) accommodating a semiconductor chip (1) on which a circuit operating at a first power supply voltage and a circuit operating at a second power supply voltage are mixedly mounted. ), The connection terminals (T1, T2, T3) provided on the test board (4) in an arrangement pattern corresponding to
First connection terminal group (T1) electrically connected to the first power supply voltage
And a second connection terminal group (T
2) and a third connection terminal group (T3) capable of conducting both the first power supply voltage and the second power supply voltage, and the semiconductor chip (1) is provided with a power supply voltage according to its operating voltage. Each power supply output terminal (A of the power supply voltage supply means (2) to be supplied
1, A2) and the connection terminal group (T1, T2, T3) are connected to the first power supply output terminal (A1) that outputs the first power supply voltage and the first connection terminal group (T1). , The second power supply output terminal (A2) from which the second power supply voltage is output and the second connection terminal group (T2) are respectively connected,
The third connecting terminal group (T3) is connected to the first via the switching means (5).
Power output terminal (A1) and second power output terminal (A2)
A semiconductor chip testing device that is switchably connected to either 3. The output terminals of the power supply voltage supply means (2) and the connection terminals (T1, T2, T3) are connected by short wirings such that the voltage drop between them is almost negligible. The semiconductor chip test apparatus according to claim 1 or 2. 4. The switching means (5) is a relay (21, 2).
3. The semiconductor chip testing apparatus according to claim 1, which comprises