JPH07235656A - Ccd solid-state image sensor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide the CCD solid-state image sensor having the structure, which can simplify and unify the manufacturing process, and the manufacturing method thereof. CONSTITUTION:A channel layer 11 is laminated on a substrate 10. Many transfer electrodes G0, G1, G2... are aligned and formed along the transfer direction of electric charge. Barrier parts B1, B2... are periodicailly formed at the surface part of the channel layer 11 beneath the transfer electrodes. A potential well, wherein electric charge is accumulated, is formed in the channel layer region between barrier parts. To each transfer electrode, the clock signal in any phase of clock signals in a plurality of phases for driving the charge transfer is supplied. The signal charge accumulated in the potential well is separated from the signal charge accumulated in the other potential well and transferred.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CC for picking up an optical image.
The present invention relates to a D solid-state imaging device and a manufacturing method thereof, and more particularly, to a CCD solid-state imaging device which performs charge transfer based on clock signals having three or more phases and a manufacturing method thereof.

[0002]

2. Description of the Related Art A CCD solid-state image pickup device (hereinafter also simply referred to as a CCD) is widely used as an image pickup device for picking up an image of light. From the viewpoint of the structure, such a CCD includes an interline transfer method (IT method) and a frame interline transfer method (FIT method) having an interline function, and a frame transfer method (FT method) having no interline function. And full frame transfer method (F
FT method).

Consumer video equipment such as VTRs with built-in cameras and electronic still cameras are equipped with IT having an interline function.
Type and FIT type CCDs are generally used.
Also, in a special measurement field such as capturing an image of an extremely weak light, for example, in a special measurement field such as condensing light arriving from a star at an extremely long distance and analyzing the image,
The FT method and the FFT method which do not have the interline function are more effective. FT method and FFT method C
This is because the aperture ratio of the CD can be improved by providing the charge transfer path group with the charge transfer function and the photoelectric conversion function.

In any of the above methods, in the charge transfer performed for reading out the signal charge generated in response to the light incident during the image pickup period, the electrodes arranged periodically in the charge transfer direction on the charge transfer path. A plurality of phases of clock voltage signals are supplied to the group to separate the signal charges of each pixel and transfer the charges.

FIG. 13 is a block diagram of a light receiving portion of a conventional CCD having no interline function. This CCD has 3
This is a device for performing charge transfer by phase clock drive, and three clock signals of each phase are arranged in the charge transfer direction and are connected by wiring to each electrode of each set of one electrode group. As shown in FIG. 9, since the electrode sets are arranged periodically,
In order to ensure electrical isolation between the individual electrodes, the electrodes in one set have different shapes and are formed by different manufacturing processes.

[0006]

Since the conventional CCD is constructed as described above, in the case of a CCD using a clock signal of n (n ≧ 2) phase, the area surface for one pixel of the channel layer is formed. Since n number of electrodes to which voltages can be applied independently in the charge transfer direction are sequentially arranged and the clock signal of each phase is individually supplied to each electrode, when n is an even number, the electrode forming step is performed. However, if n is an odd number, it is necessary to form the electrode three times or more in the electrode forming step.

The present invention has been made in view of the above points, and a CCD solid-state image pickup device having a structure capable of simplifying the manufacturing process and improving unification thereof, and such a C
A method for manufacturing a CD solid-state imaging device is provided.

[0008]

A CCD solid-state image pickup device of the present invention is a CCD solid-state image pickup device having a charge transfer path group having photoelectric conversion and charge transfer functions, wherein the charge transfer path group is (a). A channel layer for transferring signal charges; (b) an insulating layer formed on one surface of the channel layer; (c)
A first electrode group and a second electrode group formed of a plurality of electrodes of a first type and a second type alternately formed in a surface region of the insulating layer along the charge transfer direction; and (d) a second electrode group. A barrier portion formed in the channel layer below a predetermined number of two or more electrodes of the second type along the charge transfer direction. Then, at the time of imaging, a voltage forming a potential well group corresponding to a pixel generated in a channel layer region where the barrier portion is not formed is applied to all the electrodes of the first transfer electrode group and the second transfer electrode group. At the time of being applied and transferring charges, clock signals having three or more phases are applied to the first electrode group and the second electrode group, and the signal charges accumulated in the potential well are accumulated in other potential wells. Is separated from the charge transfer.

The predetermined number is 2, the number of clock phases is 3, and the charge transfer between the first electrode and the first electrode of the second electrode group formed above the barrier layer is performed. In the charge transfer direction side of the second electrode and the first electric wiring for applying the clock signal of the first phase of the three-phase clock signal to the second electrode of the first electrode group which is adjacent in the direction side. Adjacent second
To the third electrode of the third electrode group, the second electrical wiring for applying the second-phase clock signal of the three-phase clock signal and the first electrode group adjacent to the third electrode in the charge transfer direction side. The fourth electrode may be provided with a third electric wiring for applying a clock signal of a third phase of the three-phase clock signal.

Further, the voltage value applied to all the electrodes of the first transfer electrode group and the second transfer electrode group at the time of imaging is equal to or less than the pinning voltage value, and the clock signal is higher than the pinning voltage and the pinning voltage. The voltage value and the voltage value may be alternately generated.

A method of manufacturing a CCD solid-state image pickup device according to the present invention is a method of manufacturing a CCD solid-state image pickup device having a charge transfer path group having photoelectric conversion and charge transfer functions. The method includes: (a) forming a channel layer for transferring signal charges on the surface of a first conductivity type semiconductor substrate; (b) forming an insulating layer on one surface of the channel layer; and (c) ) A plurality of first types on the first region group of the first and second region groups, which are composed of a plurality of first and second regions that are alternately present in the surface region of the insulating layer along the charge transfer direction. Forming a first electrode group consisting of the electrodes of (1), and (d) forming a barrier portion of the first conductivity type in the channel layer below the second region every predetermined number of 2 or more with respect to the second region. The step of forming and (e) the first electrode group are electrically separated, A step of forming a second electrode group composed of a plurality of second type electrodes on the second region group, and (f) during imaging, the electrodes of all the first transfer electrode groups and the second transfer electrode group. Is supplied with a voltage for forming a potential well group corresponding to a pixel generated in the channel layer region where the barrier portion is not formed, and at the time of charge transfer, the signal charge accumulated in one potential well is transferred to the signal charge accumulated in another potential well. And a step of providing electrical wiring for supplying a clock signal having a number of phases of three or more for separate charge transfer to the first electrode group and the second electrode group.

Here, the above-mentioned predetermined number of 2 or more is 2, the number of phases of the clock is 3, and further, in the step of providing the electrical wiring, the second electrode group of the second electrode group formed above the barrier layer is used. 1
To the second electrode of the first electrode group which is adjacent to the first electrode on the charge transfer direction side of the first electrode, a first electric wiring for applying the clock signal of the first phase of the three-phase clock signal is provided. First to give
And the second electric wiring for applying the clock signal of the second phase of the three-phase clock signal to the third electrode of the second electrode group adjacent to the second electrode in the charge transfer direction side of the second electrode. And a second sub-step of applying a clock signal of a third phase of the three-phase clock signal to the fourth electrode of the first electrode group adjacent to the third electrode in the charge transfer direction side. And a third sub-step of applying the electric wiring of No. 3.

[0013]

In the CCD solid state image pickup device of the present invention, when light is received during the image pickup period, signal charges are accumulated in the potential well portion having the barrier portion in the channel layer as the side wall. After the end of the imaging period, when transitioning to the charge transfer period, n (n ≧ n
3; The same applies hereafter) A clock signal of a phase driving method is supplied, and a potential value corresponding to the voltage value applied to each electrode is periodically generated in the region of the channel layer below each electrode,
The signal charges are sequentially transferred to the charge transfer method to realize the transfer of the signal charges.

In the method for manufacturing a CCD solid-state image pickup device of the present invention, first, a channel layer is formed on the surface of a semiconductor substrate, and an insulating layer is formed on the surface of the channel layer. Next, in the case where the region on the surface of the insulating layer is divided into a plurality of regions in the charge transfer direction, the first electrode group is set to the selected first region group for every other divided region in the charge transfer direction. Form. Next, in the area of the surface of the insulating layer, when the individual divided areas of the second area group excluding the first area are sequentially counted in the charge transfer direction, second areas for every integer number of n / 2 or more A barrier portion is formed in the channel layer below the divided region of the group in a self-aligned manner. Subsequently, a second electrode group is formed on the second region, and wiring connection for supplying the n-phase clock to the first electrode group and the second electrode group is performed. Thus, the charge transfer path, which is a characteristic part of the CCD solid-state imaging device of the present invention, is manufactured.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. First, an example of a CCD that is preferably applied in implementing the present invention will be described with reference to FIGS. 1 and 2. In this embodiment, a CC that performs vertical charge transfer by three-phase clock drive
It is D. Figure 1 shows FT without interline function
FIG. 3 is a configuration diagram of a CCD of a method, each of which has a plurality of rows of charge transfer path groups each having both a photoelectric conversion function and a charge transfer function, and a light receiving section 3 which is further continuous to the end portions of these charge transfer path groups. A storage unit 4 having a charge transfer path group formed and having its surface shielded, and a signal charge transferred from the storage unit 4 connected to the end of the charge transfer path group of the storage unit 4 and having its surface shielded from light. A horizontal charge transfer path 7 for horizontally transferring the group in the horizontal direction x in accordance with the horizontal two-phase clocks S1 and S2, and a signal charge for each pixel provided at the end of the horizontal charge transfer path 7 and converted to a pixel signal of voltage and output. The output section 8 is provided.

On the other hand, FIG. 2 shows a CCD of the FFT system which does not have an interline function and a storage section, and a horizontal charge transfer path 6 is directly connected to the end of the charge transfer path group of the light receiving section 3. 1 is different from the FT CCD shown in FIG.

FIG. 3 is a sectional view showing the structure of the light receiving portion 3 of the CCD shown in FIG. 1 or 2. Note that FIG. 3 representatively shows the structure of the main part of one charge transfer path shown in FIGS. 1 and 2.

In FIG. 3, an n-type channel layer 11 is laminated on a p-type silicon substrate 10, and a large number of transfer electrodes G ₀ , G ₁ , G ₂ ... G _n (n: integer) are provided via a thinner insulating layer. ) ... Are arrayed along the vertical charge transfer direction y. Of these electrodes, the first transfer electrode group G _2m (m: integer) has the same shape as each other, and the second transfer electrode group G _{2m + 1.}
(M: integer) is different from the first transfer electrode group G _2m and has the same shape. Further, the transfer electrodes G ₁ , G ₅ ... G _{4l + 1} (l: integer) belonging to the second transfer electrode group G _{2m + 1} are p-type or n-type on the surface layer portion of the lower channel layer 11.
Barrier portions B ₁ , B ₂ ... _Bl are formed by diffusion or ion implantation of the shape impurities.

The transfer electrode G _{4l + 1} and the transfer electrode G
_{4l + 2} has a clock signal P1, a transfer electrode G _{4l + 3} has a clock signal P2, and a transfer electrode G _{4l + 4} has a clock signal P3.
Is being applied. Note that the transfer electrodes G ₀ , G ₁ , G ₂ ... G _n ... Of the same arrangement are formed in the other charge transfer path groups, and the clock signals P1, P2, P3 are applied in the same manner as above.

FIG. 4 shows vertical three-phase clocks P1, P2.
It is a timing chart of P3. In the light receiving period τ1 (imaging period), all the clock signals P1, P2, P3 are held at a predetermined low voltage (hereinafter, referred to as “L” level) V _L. On the other hand, at the time of vertical charge transfer, which will be described later, the clock signals P1, P2 and P3 are supplied with the "L" level voltage V _L and a predetermined voltage (referred to as "H" level) V _H higher than the "L" level voltage V _L. The potential profile for charge transfer is generated by alternately changing with. The voltage applied to the transfer electrode is V _L
The amount of change in the potential in the channel layer below the transfer electrode caused by the change from V _H to V _H is larger than the value of the potential difference between the barrier part and the part which is not the barrier part when the same voltage is applied to the corresponding transfer electrode. The applied voltage value is set so as to increase.

In this way, the clock signals P1, P2, P3
During the light receiving period τ1 in which both are held at “L” level,
As represented by the time t ₀ , the potential profile shown in FIG. That is, the barrier portions B ₁ , B ₂
.. are not formed in the portion where the barriers B ₁ , B ₂ ... Are formed, and the potential according to the “L” level voltage V _L is relatively shallow. A potential well is created. The signal charges q ₀ , q ₁ , q _2, ... Generated during the light receiving period τ1 are integrated in these potential wells.

Next, in the vertical charge transfer period τ ₂ , as shown in FIG. 4, the clocks P1, P2 and P3 are at "L" level voltage V _L and "H" level voltage in a predetermined cycle and a predetermined phase relationship. Alternately changes with V _H.

First, while the clock signals P1 and P2 remain at "L" level, the clock signal P3 is inverted to "H" level (transfer phase state 1). Transfer electrodes (G ₁ , G ₂ , G ₃ ) and transfer electrodes (G ₅ , G ₆ ,
G ₇ ) ..., that is, transfer electrodes (G _{4l + 1} , G _{4l + 2} ,
The potential profile corresponding to G _{4l + 3} ) does not change, but the transfer electrode G ₀ and the transfer electrode G are at the “H” level.
₄ and the transfer electrodes G ₈ ..., That is, the potentials corresponding to the transfer electrodes G _{4l + 4} become deep (see FIG. 5B). Therefore, the potential of the potential well below the transfer electrodes G _{4l + 4} at the “H” level becomes maximum (in other words, deepest), and the potential wells below the transfer electrodes G _{4l + 2} and G _{4l + 3} are integrated. The signal charge (q ₀ , q ₁ ,
q ₂ ...) moves toward the potential well below the transfer electrode G _{4l + 4} .

Next, from transfer phase state 1 to clock signal 1
Is inverted to the “H” level (transfer phase state 2), the potential profile corresponding to the transfer electrodes (G _{4l + 1} , G _{4l + 2} ) changes (see FIG. 5C). As a result, the signal charge is transferred from the transfer electrode G _{4l + 4} side to the transfer electrode (G _{4l + 1} ,
Move to the G _{4l + 2} ) side. Subsequently, the transfer phase state 2 inverts the clock signal P3 to the “L” level (transfer phase state 3; see FIG. 5D), and the transfer phase state 3 inverts the clock signal P2 to the “H” level (transfer) Phase state 4; see FIG. 6A), transfer phase state 4 to clock signal P1
Is inverted to "L" level (transfer phase state 5; FIG. 6B)
From the transfer phase state 5, the clock signal P3 is "H".
Inversion to the level (transfer phase state 6; see FIG. 6C) occurs sequentially. Then, when the clock signal P2 is inverted from the transfer phase state 6 to the "L" level, the transfer phase state 1'having the same potential profile as the transfer phase state 1 is obtained (see FIG. 6D). After that, the above-mentioned periodical change of the potential profile continues. As the transition of the transfer phase state progresses, as shown in FIGS. 5A to 5D and FIGS. 6A to 6D, the potential profile continuously changes and is separated for each signal charge. Charge transfer is performed.

FIG. 7 is a timing chart of a modification of the vertical three-phase clock signals P1, P2, P3 with respect to FIG. Three-phase clock signals P1 ', P2', P shown in FIG.
3'have the same phase relationship as in FIG. 4, but the voltage value V _H2 of the clock signal P1 'at the "H" level is higher than the voltage value V _H1 of the "H" level of the clock signals P2' and P3 '. Is also different in that it is set larger. Hereinafter, the difference between the potentials in the channel layer generated when the voltage value applied to the transfer electrode is V _H2 and V _H1 is the barrier part and the barrier when the same voltage is applied to the corresponding transfer electrode. To be larger than the value of the potential difference between the non-part and
The case where the applied voltage value is set will be described.

8 and 9 show a three-phase clock signal P
It is explanatory drawing of the change of the potential profile in the channel layer by the drive of 1 ', P2', and P3 ', and movement of a signal charge. 8 (a)-(d) and 9 (a)-(d)
5A to 5D and 6A to 6D, respectively. Comparing FIG. 8 and FIG. 9 with FIG. 5 and FIG. 7, it is the charge transfer barrier seen in FIG. 5C in transfer phase state 2 (see FIG. 8C and FIG. 5C). It can be confirmed in FIG. 8C that the potential profile of the barrier portion does not serve as a barrier for charge transfer.

The voltage value applied to the transfer electrode is V _H2
And the potential difference in the channel layer between V _H1 and V _H1 is smaller than the potential difference between the barrier portion and the non-barrier portion when the same voltage is applied to the corresponding transfer electrodes. Even in this case, the barrier height due to the potential profile of the barrier portion in the transfer state 2 is reduced as compared with FIG. 5, and the three-phase clock signals P1, P
Charge transfer is executed more smoothly than when driven by P2 and P3.

"L" level voltage V in the above embodiment
It is preferable that _L is determined based on the characteristics of the CCD shown in FIG. FIG. 10 shows the gate voltage V _G (volt) applied to the transfer electrode and the dark current Id (nA).
/ Cm ² ) is a result of an experiment showing a correlation with
It is clear that has a characteristic that the dark current Id decreases as the gate voltage V _G decreases. Then, the decrease tendency of the dark current Id stops when the gate voltage V _G crosses the pinning voltage V _P. Therefore, setting a predetermined voltage lower than the pinning voltage V _P as the “L” level voltage V _L is
Special measurement fields such as capturing extremely weak light images,
For example, it is particularly desirable in a special measurement field such as collecting light arriving from a star at an extremely long distance and analyzing the image.

In the FT type CCD shown in FIG. 1, the charge transfer path of the storage section 4 also performs the charge transfer operation, so that the signal charges are gradually held in the storage section 4. On the other hand, in the FFT type CCD shown in FIG.
Each time the signal charges for the columns are transferred, the horizontal charge transfer path 7 repeats the horizontal charge transfer operation in synchronization with the horizontal clock signals S1 and S2 of a predetermined cycle, so that the signal charges can be read. There is. In addition, the FT type CCD shown in FIG.
Then, the signal charge corresponding to one frame once held in the storage unit 4 is transferred by the charge transfer path of the storage unit 4 and the horizontal charge transfer path 7 as in the charge transfer of the FFT CCD shown in FIG. Output.

The light receiving portion of the CCD solid-state image pickup device of the above embodiment is manufactured by the following steps. In the following explanation,
Although the manufacture of one vertical charge transfer path will be described, other vertical charge transfer paths are manufactured similarly and simultaneously. Figure 1
1 and 12 are manufacturing process diagrams of a light receiving portion of a CCD solid-state imaging device.

First, after forming the n-type channel layer 11 on the surface of the p-type Si substrate 10 (see FIG. 11A), the SiO ₂ insulating layer 12 is formed on the surface of the channel layer 11 (FIG. 11A). 11 (b)). Then, the SiO ₂ insulating layer 12
After forming a polysilicon layer on the surface of the SiO ₂ insulating film 12, selective etching is performed to form a polysilicon electrode 21 which is a first electrode group on the surface of the SiO ₂ insulating layer 12 (see FIG. 11C).

Next, after forming an SiO ₂ insulating layer on the entire surface, a resist on the region of the channel layer 11 where ion implantation is not performed is formed, and when activated in the channel layer, p-type conductivity which shows p-type conductivity is formed. A dopant is selectively ion-implanted to form the p-type barrier portion 15 (see FIG. 12A).

Next, after removing the resist, a polysilicon layer is formed on the surface of the SiO ₂ insulating layer and then selectively etched to form a polysilicon electrode 22 which is a second electrode group on the surface of the SiO ₂ insulating layer 12. (See FIG. 12B). Subsequently, a connection wiring for supplying a clock signal is provided on each electrode, and finally an SiO ₂ insulating layer is formed on the entire surface (see FIG. 12C) to complete the light receiving portion.

In this manner, the barrier section is formed in a self-aligned manner, and the light receiving section having the three-phase clock driven charge transfer path group is manufactured by the two electrode forming steps.

The present invention is not limited to the above embodiments, but can be modified. For example, in the above-described embodiment, the CCD is driven by three-phase clock, but if the interval for forming the barrier portion and the connection wiring of the supply clock signal are changed, it becomes four.
Clock driven CCDs of more than one phase can be similarly constructed.

[0036]

As described in detail above, the C of the present invention
According to the CD solid-state imaging device, a group of transfer electrodes that supplies a transfer drive clock signal of the charge transfer path is electrically separated from each other, and two electrodes arranged in the charge transfer direction are set as one set. Since the method of supplying the clock signals of each phase of the transfer driving clock signals of three or more phases can be determined by the wiring connection after the elements are periodically arranged in the charge transfer direction and formed, the transfer electrode formation step is performed twice. It is possible to realize a CCD solid-state imaging device in which all the transfer electrodes can be formed, the manufacturing process can be simplified, and the process before the connection wiring can be unified. Further, since the barrier portion for efficiently accumulating the signal charges of each pixel is formed below the region occupied by the selected transfer electrode, the barrier portion can be formed in a self-aligned manner.

Furthermore, by applying a voltage lower than the pinning voltage of the CCD to all the transfer electrodes at the time of image pickup, the dark current can be reduced, and a special measurement field for picking up an image of an extremely faint light. For example, it is particularly effective in a special measurement field such as collecting light arriving from a star at an extremely long distance and analyzing the image.

Further, according to the CCD solid-state image pickup device of the present invention, the barrier portion is formed after forming one electrode of the above-mentioned pair of electrodes, and subsequently the connection for clock supply is formed after forming the other pair of electrodes. Since the wiring is decided, the CC of the present invention
D can be manufactured efficiently.

[Brief description of drawings]

FIG. 1 is a configuration explanatory view showing a configuration of an embodiment of a CCD solid-state imaging device to which the present invention is applied.

FIG. 2 is a structural explanatory view showing the structure of another embodiment of the CCD solid-state imaging device to which the present invention is applied.

FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along the line AA of the charge transfer path in FIGS. 1 and 2.

FIG. 4 is a timing chart of an example of a clock for driving a charge transfer path.

5 is a diagram showing a potential profile generated by the clock shown in FIG.

6 is a diagram showing a potential profile generated by the clock shown in FIG.

FIG. 7 is a timing chart of another example of a clock for driving the charge transfer path.

8 is a diagram showing a potential profile generated by the clock shown in FIG.

9 is a diagram showing a potential profile generated by the clock shown in FIG. 7. FIG.

FIG. 10 is a characteristic diagram showing a relationship between a gate voltage applied to a transfer electrode and a dark current.

FIG. 11 is a process (first half) diagram of the method for manufacturing the CCD solid-state imaging device of the present invention.

FIG. 12 is a process (second half) diagram of the method for manufacturing the CCD solid-state imaging device according to the present invention.

FIG. 13 is a configuration diagram of a light receiving unit of a conventional CCD solid-state imaging device.

[Explanation of symbols]

3 ... Light receiving part, 4 ... Storage part, 7 ... Horizontal charge transfer path, 10 ...
Semiconductor substrate, 11 ... Channel layer, 12 ... Insulating layer, 15,
B ₁ , B ₂ ... Barrier layers 21, 22, G ₁ , G ₂ , G
₃ ... Transfer electrodes.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/335 Z

Claims (5)

[Claims] 1. A CCD solid-state imaging device having a charge transfer path group having photoelectric conversion and charge transfer functions, wherein the charge transfer path group comprises: a channel layer for transferring signal charges; and a surface of the channel layer. A first electrode group consisting of an insulating layer formed on the surface of the insulating layer, and a plurality of first and second types of electrodes formed alternately on the surface region of the insulating layer along the charge transfer direction; An electrode group, and a barrier portion formed in the channel layer below the second type electrode for every predetermined number of two or more along the charge transfer direction with respect to the second type electrode. At the time of imaging, the voltage forming the potential well group corresponding to the pixel generated in the channel layer region where the barrier portion is not formed is applied to all the electrodes of the first transfer electrode group and the second transfer electrode group. Applied, At the time of load transfer, a clock signal having three or more phases is applied to the first electrode group and the second electrode group, so that the signal charges accumulated in one potential well are different from the signal charges accumulated in another potential well. A CCD solid-state image pickup device characterized in that charges are transferred separately. 2. The predetermined number is 2, the number of phases of the clock signal is 3, and the first electrode and the first electrode of the second electrode group formed above the barrier layer. A first electric wire for applying a clock signal of a first phase of the three-phase clock signal to a second electrode of the first electrode group adjacent to the electrode on the charge transfer direction side; A second electric wire for applying a clock signal of a second phase of the three-phase clock signal to a third electrode of the second electrode group which is adjacent to the second electrode on the charge transfer direction side; Third electrical wiring for applying a clock signal of a third phase of the three-phase clock signal to a fourth electrode of the first electrode group adjacent to the third electrode on the charge transfer direction side, The CCD solid-state imaging device according to claim 1, further comprising: 3. A voltage value applied to all the electrodes of the first transfer electrode group and the second transfer electrode group at the time of the image pickup is a pinning voltage value or less, and the clock signal is a pinning voltage and a pinning voltage. 2. The CC according to claim 1, wherein a voltage value higher than the voltage is alternately generated.
D solid-state imaging device. 4. A method of manufacturing a CCD solid-state imaging device having a charge transfer path group having a photoelectric conversion function and a charge transfer function, wherein the method of manufacturing the charge transfer path group is performed on a semiconductor substrate of a first conductivity type. A step of forming a channel layer for transferring signal charges on the surface; a step of forming an insulating layer on one surface of the channel layer; and a plurality of surface regions of the insulating layer that are present alternately along the charge transfer direction. Forming a first electrode group composed of a plurality of electrodes of a first type on the first region group of the first and second region groups consisting of the first and second regions; Forming a barrier layer of a first conductivity type in a channel layer below a predetermined number of two or more regions along the charge transfer direction with respect to a region; and the first electrode group; Are electrically isolated and have a plurality of second regions on the second region group. A step of forming a second electrode group composed of electrodes of the above type, a step of forming a second electrode group, and electrodes of all the first transfer electrode group and the second transfer electrode group during imaging. Is supplied with a voltage forming a potential well group corresponding to a pixel generated in the channel layer region in which the barrier portion is not formed, and at the time of charge transfer, the signal charge accumulated in one potential well is transferred to the signal accumulated in another potential well. And a step of providing electrical wiring for supplying a clock signal having a number of phases of three or more phases separated from charges to the charge transfer to the first electrode group and the second electrode group. Method for manufacturing CCD solid-state imaging device. 5. The predetermined number is 2, the number of phases of the clock signal is 3, and the step of applying the electric wiring includes the step of forming a second electrode group of the second electrode group formed above the barrier layer. A first phase clock signal of the three-phase clock signal is applied to the first electrode and the second electrode of the first electrode group that is adjacent to the first electrode on the charge transfer direction side. The first sub-step of providing the first electrical wiring and the second electrode of the three-phase clock signal are applied to the third electrode of the second electrode group which is adjacent to the second electrode on the charge transfer direction side. A second sub-step of applying a second electric wire for applying a phase clock signal; and a fourth electrode of the first electrode group adjacent to the third electrode on the charge transfer direction side, A third sub-step of applying a third electric wiring for applying a clock signal of a third phase of the three-phase clock signal, Method of manufacturing a CCD solid-state imaging device according to claim 4, characterized in that it comprises.