JP3334992B2 - CCD solid-state imaging device and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CC for capturing an optical image.
The present invention relates to a D solid-state imaging device and a method of manufacturing the same, and more particularly to a CCD solid-state imaging device that executes charge transfer based on clock signals of three or more phases and a method of manufacturing the same.

[0002]

2. Description of the Related Art In capturing an image of light, a CCD solid-state imaging device (hereinafter simply referred to as a CCD) is widely used as an imaging device. From the viewpoint of configuration, such CCDs have an interline transfer method (IT method) and a frame interline transfer method (FIT method) having an interline function, and a frame transfer method (FT method) without an interline function. And full frame transfer method (F
FT method).

[0003] Consumer video equipment such as a camera-integrated VTR and an electronic still camera includes an IT having an interline function.
Or FIT type CCD is generally used.
In a special measurement field such as capturing an image of an extremely weak light, for example, in a special measurement field such as collecting light arriving from an extremely distant star and analyzing the image,
The FT method or the FFT method having no interline function can obtain more excellent effects. FT and FFT C
This is because the CD can improve the aperture ratio by providing the charge transfer path group with a charge transfer function and a photoelectric conversion function.

[0004] In any of the above-mentioned methods, when transferring charges for reading out signal charges generated in response to light incident during an imaging period, electrodes periodically arranged in a charge transfer direction on a charge transfer path are used. A plurality of phases of clock voltage signals are supplied to the group to separate and transfer signal charges for each pixel.

FIG. 13 is a configuration diagram of a light receiving section of a conventional CCD having no interline function. This CCD is 3
This is a device that performs charge transfer by phase clock driving, and clock signals of each phase are wired and connected to each electrode of each set of a set of three electrodes arranged in the charge transfer direction. As shown in FIG. 9, a set of electrodes is periodically arranged.
The electrodes in a set have different shapes and are formed in different manufacturing steps to ensure electrical isolation between the individual electrodes.

[0006]

Since the conventional CCD is configured as described above, in the case of a CCD using a clock signal of n (n ≧ 2) phases, the surface of the channel layer for one pixel area is formed. Since n electrodes to which a voltage can be applied independently of each other in the charge transfer direction are sequentially arranged and clock signals of each phase are individually supplied to each electrode, when n is an even number, an electrode forming process is performed. Is required at least twice, but when n is an odd number, at least three times of electrode formation is indispensable in the electrode formation process.

The present invention has been made in view of the above points, and has a CCD solid-state imaging device having a structure capable of improving the simplification and unification of the manufacturing process.
A method for manufacturing a CD solid-state imaging device.

[0008]

The CCD solid-state imaging device according to the present invention is a CCD solid-state imaging device having a charge transfer path group having a photoelectric conversion function and a charge transfer function. A channel layer for transferring signal charges, (b) an insulating layer formed on one surface of the channel layer, and (c)
A first electrode group and a second electrode group including a plurality of first type and second type electrodes alternately formed in the surface region of the insulating layer along the charge transfer direction; and (d) a second electrode group. A barrier portion formed in the channel layer below every second electrode of the second type along the charge transfer direction with respect to the type of electrode; and (e) a second electrode formed above the barrier portion A first electrode of a three-phase clock signal is applied to a first electrode of the group and a second electrode of the first electrode group adjacent to the first electrode on the charge transfer direction side.
A first electric wiring for applying a clock signal of a phase of
(F) a second electric wiring for applying a clock signal of the second phase of the three-phase clock signal to the third electrode of the second electrode group adjacent on the charge transfer direction side of the second electrode; g) a third electric wiring for applying a clock signal of a third phase of the three-phase clock signal to the fourth electrode of the first electrode group adjacent on the charge transfer direction side of the third electrode; Prepare.

At the time of imaging, the first electric wiring,
A potential corresponding to a pixel generated in a channel layer region where a barrier portion is not formed in all of the electrodes of the first electrode group and the second electrode group by using the second electric wiring and the third electric wiring. A voltage is applied so as to form a well group, and during charge transfer, three-phase clock signals are applied to the electrodes of the first electrode group and the second electrode group by the first electric wiring, the second electric wiring, and the third electric wiring. It is characterized in that the signal charges applied to the potential wells applied through the electric wiring are transferred separately from the signal charges accumulated in the other potential wells.

Further, during imaging, the voltage value applied to all the electrodes of the first transfer electrode group and the second transfer electrode group is equal to or less than the pinning voltage value, and the clock signal is higher than the pinning voltage. It may be characterized in that the voltage value and the voltage value are generated alternately.

Further, a method of manufacturing a CCD solid-state imaging device according to the present invention is a method of manufacturing a CCD solid-state imaging device having a charge transfer path group having a photoelectric conversion function and a charge transfer function. The method includes: (a) forming a channel layer for transferring signal charges on a surface of a semiconductor substrate of a first conductivity type; (b) forming an insulating layer on one surface of the channel layer; A) a plurality of first types on a first region group of a first and second region group consisting of a plurality of first and second regions that alternately exist in a surface region of an insulating layer along a charge transfer direction; Forming a first electrode group consisting of the first and second electrodes; and (d) forming a first conductivity type barrier portion in the channel layer below the second region by a predetermined number of two or more with respect to the second region. Forming; and (e) the first electrode group is electrically separated; Forming a second electrode group composed of a plurality of second type electrodes on the second region group; and (f) at the time of imaging, all the electrodes of the first transfer electrode group and the second transfer electrode group. A potential well group corresponding to a pixel generated in a channel layer region where a barrier portion is not formed, and a signal charge accumulated in a potential well is accumulated in another potential well during charge transfer. And providing electrical wiring for supplying clock signals of three or more phases to the first electrode group and the second electrode group for performing charge transfer separately from the first electrode group and the second electrode group.

Here, the predetermined number of two or more is two, the number of clock phases is three, and the step of providing electric wiring is performed by the second electrode group formed above the barrier layer. 1
And a second electrode of a first electrode group adjacent to the first electrode on the charge transfer direction side of the first electrode is provided with a first electric wiring for applying a clock signal of a first phase of a three-phase clock signal. First to apply
And a second electric wiring for applying a clock signal of the second phase of the three-phase clock signal to the third electrode of the second electrode group adjacent to the second electrode on the charge transfer direction side. And applying a third phase clock signal of the three-phase clock signal to the fourth electrode of the first electrode group adjacent to the third electrode on the charge transfer direction side. And a third sub-step of providing the third electrical wiring.

[0013]

In the CCD solid-state imaging device according to the present invention, when light is received during an imaging period, signal charges are accumulated in a potential well portion having a barrier portion in a channel layer as a side wall. After the end of the imaging period, when transitioning to the charge transfer period, n (n ≧ n) is applied to each electrode.
3: the same applies hereinafter) A clock signal of the phase driving method is supplied, and a potential value corresponding to the voltage value applied to each electrode is periodically generated in the channel layer region below each electrode,
The signal charges are sequentially moved to the charge transfer method to realize the transfer of the signal charges.

In the method of manufacturing a CCD solid-state imaging device according to the present invention, first, a channel layer is formed on a surface of a semiconductor substrate, and an insulating layer is formed on a surface of the channel layer. Next, when the region on the surface of the insulating layer is divided into a plurality of regions in the charge transfer direction, every other region in the charge transfer direction is divided into a first region group and a first electrode group. Form. Next, when the individual divided regions of the second region group excluding the first region among the regions on the surface of the insulating layer are sequentially counted in the charge transfer direction, the second region for every integer number equal to or more than n / 2 A barrier portion is formed in a self-aligned manner in the channel layer below the group division region. Subsequently, a second electrode group is formed on the second region, and wiring connection for supplying an n-phase clock to the first electrode group and the second electrode group is performed. Thus, a charge transfer path which is a characteristic part of the CCD solid-state imaging device of the present invention is manufactured.

[0015]

An embodiment of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. First, an example of a CCD suitably applied to carry out the present invention will be described with reference to FIGS. In the present embodiment, a CC that performs vertical charge transfer by three-phase clock driving is used.
D. FIG. 1 shows an FT having no interline function.
FIG. 2 is a configuration diagram of a CCD of a system, in which a light receiving section 3 having a plurality of rows of charge transfer path groups each having both a photoelectric conversion function and a charge transfer function, and further continuing to the terminal portions of these charge transfer path groups. A storage unit 4 having a charge transfer path group formed and whose surface is shielded from light; and a signal charge connected to the end of the charge transfer path group of the storage unit 4 whose surface is shielded and transferred from the storage unit 4. A horizontal charge transfer path 7 for horizontally transferring the group in the horizontal direction x in accordance with the horizontal two-phase clocks S1 and S2, and a signal charge for each pixel, which is provided at the end of the horizontal charge transfer path 7, is converted into a pixel signal of voltage and output. An output unit 8 is provided.

On the other hand, FIG. 2 shows an FFT type CCD having no interline function and no storage section, in that a horizontal charge transfer path 6 is directly connected to the end of the charge transfer path group of the light receiving section 3. , And the FT type CCD shown in FIG.

FIG. 3 is a sectional view showing the structure of the light receiving section 3 of the CCD shown in FIG. 1 or FIG. FIG. 3 shows the structure of the main part of one charge transfer path shown in FIGS. 1 and 2 as a representative.

In FIG. 3, an n-type channel layer 11 is laminated on a p-type silicon substrate 10, and a number of transfer electrodes G ₀ , G ₁ , G ₂ ... G _n (n: integer) ) Are arranged along the vertical charge transfer direction y. Among these electrodes, the first transfer electrode group G _2m (m: integer) has the same shape as each other, and the second transfer electrode group G _{2m + 1}
(M: integer) has a shape different from that of the first transfer electrode group G _2m and is the same as each other. Further, transfer electrodes G ₁ , G _5, ..., G _{4l + 1} (1: integer) belonging to the second transfer electrode group G _{2m + 1.}
The barrier portions B ₁ , B _2, ..., B ₁ .

The transfer electrode G _{4l + 1} and the transfer electrode G
_{4l + 2} receives the clock signal P1, the transfer electrode G _{41 + 3} receives the clock signal P2, and the transfer electrode G _{41 + 4} receives the clock signal P3.
Is applied. In the other charge transfer path groups, transfer electrodes G ₀ , G ₁ , G _2, ..., G _n ...

FIG. 4 shows vertical three-phase clocks P1, P2,
It is a timing chart of P3. In the light receiving period τ1 (imaging period), all of the clock signals P1, P2, and P3 are held at a predetermined low voltage (hereinafter, referred to as “L” level) _VL . On the other hand, during the vertical charge transfer to be described later, the clock signal P1, P2, P3 a, "L" level and the voltage V _L, the "L" level voltage V _L higher than a predetermined voltage (referred to "H" level) V _H , A potential profile for charge transfer is generated. The voltage applied to the transfer electrode is V _L
Of the potential in the channel layer below the transfer electrode when the voltage changes from VH to _VH is smaller than the value of the potential difference between the barrier portion and the non-barrier portion when the same voltage is applied to the corresponding transfer electrode. The applied voltage value is set so as to increase.

As described above, the clock signals P1, P2, P3
Are held at the “L” level during the light receiving period τ1,
As represented by the time t ₀ , the potential profile shown in FIG. That is, the barrier portions B ₁ and B ₂
In the portion where... Are formed, no potential well is generated, and in the portion where the barrier portions B ₁ , B ₂ ... Are not formed, the potential according to the “L” level voltage _VL is relatively shallow. A potential well is created. The signal charges q ₀ , q ₁ , q _2, ... Generated in the light receiving period τ1 are accumulated in these potential wells.

Next, in the vertical charge transfer period τ ₂ , as shown in FIG. 4, the clocks P 1, P 2, and P 3 have the “L” level voltage V _L and the “H” level voltage in a predetermined cycle / phase relation. It alternately reverses at _VH .

First, while the clock signals P1 and P2 remain at the "L" level, the clock signal P3 is inverted to the "H" level (transfer phase state 1). The transfer electrodes (G ₁ , G ₂ , G ₃ ) and the transfer electrodes (G ₅ , G ₆ ,
G ₇ ), that is, the transfer electrodes (G _{4l + 1} , G _{4l + 2} ,
G _{4l + 3} ) does not change, but the transfer electrodes G ₀ and G _attain “H” level.
₄ and the transfer electrode G ₈ ..., That is, the potential corresponding to the transfer electrode G _{4l + 4} becomes deeper (see FIG. 5B). Therefore, the potential of the potential well under the transfer electrode G _{4l + 4} which becomes “H” level becomes the maximum (in other words, becomes deepest), and is integrated in the potential well under the transfer electrodes G _{41 + 2} and G _{41 + 3.} Signal charge (q ₀ , q ₁ ,
q ₂ ...) move toward the potential well below the transfer electrode G _{41 + 4} .

Next, from the transfer phase state 1 to the clock signal 1
Is inverted to the "H" level (transfer phase state 2), the potential profile corresponding to the transfer electrodes ( _{G4l + 1} , _{G4l + 2} ) changes (see FIG. 5C). As a result, the signal charges are transferred from the transfer electrode G _{4l + 4} side to the transfer electrode (G _{4l + 1} ,
G _{4l + 2} ) Move to the side. Subsequently, the clock signal P3 is inverted from the transfer phase state 2 to the “L” level (transfer phase state 3; see FIG. 5D), and the clock signal P2 is inverted from the transfer phase state 3 to the “H” level (transfer). Phase state 4; see FIG. 6 (a));
Is inverted to "L" level (transfer phase state 5; FIG. 6 (b)
From the transfer phase state 5, the clock signal P3 becomes “H”.
Inversion to the level (transfer phase state 6; see FIG. 6C) sequentially occurs. Then, when the clock signal P2 is inverted from the transfer phase state 6 to the "L" level, the transfer phase state 1 'has the same potential profile as the transfer phase state 1 (see FIG. 6D). Thereafter, the above-described periodic change of the potential profile continues. As the transition of the transfer phase state progresses, as shown in FIGS. 5A to 5D and FIGS. 6A to 6D, the potential profile continuously changes and separates for each signal charge. Then, charge transfer is performed.

FIG. 7 is a timing chart of a modification of the three-phase clock signals P1, P2, and P3 which are vertical to FIG. The three-phase clock signals P1 ', P2', P shown in FIG.
3 'has the same phase relationship as that of FIG. 4 except that the "H" level voltage value V _{H2 of} the clock signal P1' is higher than the "H" level voltage value V _{H1 of the} clock signals P2 'and P3'. Is also set to be large. Hereinafter, the difference in the potential in the channel layer between the case where the voltage value applied to the transfer electrode is V _{H2 and} the case where the voltage value is V _H1 is the barrier portion and the barrier when the same voltage is applied to the corresponding transfer electrode. So that it is larger than the value of the potential difference with the non-part
The case where the applied voltage value is set will be described.

FIGS. 8 and 9 show a three-phase clock signal P.
FIG. 5 is an explanatory diagram of a change in a potential profile in a channel layer and a movement of a signal charge due to driving of 1 ′, P2 ′, and P3 ′. 8 (a) to 8 (d) and FIGS. 9 (a) to 9 (d)
5 correspond to the transfer phase states of FIGS. 5A to 5D and 6A to 6D, respectively. Comparing FIGS. 8 and 9 with FIGS. 5 and 7, in the transfer phase state 2 (see FIGS. 8 (c) and 5 (c)), there is a charge transfer barrier seen in FIG. 5 (c). In FIG. 8C, it can be confirmed that the potential profile of the barrier portion does not act as a barrier for charge transfer.

The voltage applied to the transfer electrode is V _H2
The difference in potential of the channel layer that occurs in the case where the V _H1 of less than the value of the potential difference between the barrier portion and the non-barrier portion when the same voltage is applied to corresponding transfer electrodes Even in this case, the barrier height due to the potential profile of the barrier unit in the transfer state 2 is reduced as compared with FIG. 5, and the three-phase clock signals P1, P
The charge transfer is executed more smoothly than when driven by P2 and P3.

The "L" level voltage V in the above embodiment
_L is preferably determined based on the characteristics of the CCD shown in FIG. FIG. 10 shows the gate voltage V _G (volt) of the clock applied to the transfer electrode and the dark current Id (nA).
/ Cm ² ), which is the experimental result showing the correlation with
It is found to have a characteristic that the gate voltage V _G is higher dark current Id is reduced lower. The decrease of the dark current Id stops the gate voltage V _G is a boundary pinning voltage V _P. Therefore, it is a voltage V _L of the lower predetermined voltage than a pinning voltage V _P "L" level,
Special measurement fields such as capturing extremely weak light images,
For example, it is particularly desirable in the special measurement field where light arriving from an extremely distant star is collected and its image is analyzed.

In the FT type CCD shown in FIG. 1, since the charge transfer path of the storage section 4 also performs a charge transfer operation, signal charges are gradually held in the storage section 4. On the other hand, in the FFT type CCD shown in FIG.
Each time the signal charges of a column are transferred, the horizontal charge transfer path 7 repeats the horizontal charge transfer operation in synchronization with the clock signals S1 and S2 having a predetermined horizontal period, so that the signal charges can be read. I have. The FT type CCD shown in FIG.
Then, the signal charge corresponding to one frame once held in the storage unit 4 is transferred to the charge transfer path and the horizontal charge transfer path 7 of the storage unit 4 by performing the same transfer operation as the charge transfer of the FFT type CCD in FIG. Output.

The light receiving section of the CCD solid-state imaging device of the above embodiment is manufactured by the following steps. In the following description,
The manufacture of one vertical charge transfer path is described, but the other vertical charge transfer paths are manufactured similarly and simultaneously. FIG.
1 and 12 are manufacturing process diagrams of the light receiving section of the CCD solid-state imaging device.

First, after forming an n-type channel layer 11 on the surface of a p-type Si substrate 10 (see FIG. 11A), an SiO ₂ insulating layer 12 is formed on the surface of the channel layer 11 (see FIG. 11). 11 (b)). Subsequently, the SiO ₂ insulating layer 12
After a polysilicon layer is formed on the surface of the SiO ₂ insulating layer 12, selective etching is performed to form a polysilicon electrode 21 as a first electrode group on the surface of the SiO ₂ insulating layer 12 (see FIG. 11C).

Next, after an SiO ₂ insulating layer is formed on the entire surface, a resist is formed on the region of the channel layer 11 where ion implantation is not performed, and when activated in the channel layer, a p-type conductive material having p-type conductivity is formed. A p-type barrier portion 15 is formed by selectively ion-implanting a dopant (see FIG. 12A).

Next, after removing the resist, a polysilicon layer is formed on the surface of the SiO ₂ insulating layer and then selectively etched to form a polysilicon electrode 22 as a second electrode group on the surface of the SiO ₂ insulating layer 12. (See FIG. 12B). Subsequently, connection wiring for supplying a clock signal is applied to each electrode, and finally, an SiO ₂ insulating layer is formed on the entire surface (see FIG. 12C) to complete the light receiving section.

In this way, the barrier section is formed in a self-aligned manner, and the light receiving section having the charge transfer path group driven by the three-phase clock is manufactured in two electrode forming steps.

The present invention is not limited to the above embodiments, but can be modified. For example, in the above-described embodiment, a CCD driven by a three-phase clock is used.
A clock-driven CCD of more than one phase can be similarly configured.

[0036]

As described above in detail, the C of the present invention
According to the CD solid-state imaging device, the transfer electrode group for supplying the transfer drive clock signal of the charge transfer path is electrically separated from each other and two electrodes arranged in the charge transfer direction are regarded as one set, and the set of electrodes is defined as After a periodic arrangement in the charge transfer direction, the method of supplying clock signals of each phase of three or more transfer drive clock signals can be determined by wiring connection. All of the transfer electrodes can be formed, so that the manufacturing process can be simplified, and a CCD solid-state imaging device capable of unifying processes before connection wiring can be realized. Further, since the barrier portion for efficiently collecting the signal charges for each pixel is formed below the area occupied by the selected transfer electrode, the barrier portion can be formed in a self-aligned manner.

Further, when a voltage lower than the pinning voltage of the CCD is applied to all the transfer electrodes at the time of imaging, the dark current can be reduced, and a special measurement field for imaging an extremely weak light image can be obtained. For example, the present invention is particularly effective in a special measurement field in which light arriving from an extremely distant star is collected and its image is analyzed.

According to the CCD solid-state imaging device of the present invention, the barrier portion is formed after forming one electrode of the above-mentioned one set of electrodes, and then the connection for clock supply is formed after the other set of electrodes is formed. Since wiring is to be performed, the CC of the present invention is used.
D can be manufactured efficiently.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory view showing a configuration of an embodiment of a CCD solid-state imaging device to which the present invention is applied.

FIG. 2 is a configuration explanatory view showing the configuration of another embodiment of a CCD solid-state imaging device to which the present invention is applied;

FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along line AA of the charge transfer path in FIGS. 1 and 2;

FIG. 4 is a timing chart of an example of a clock for driving a charge transfer path.

FIG. 5 is a diagram showing a potential profile generated by the clock shown in FIG. 4;

FIG. 6 is a diagram showing a potential profile generated by the clock shown in FIG. 4;

FIG. 7 is a timing chart of another example of a clock for driving a charge transfer path.

FIG. 8 is a diagram showing a potential profile generated by the clock shown in FIG. 7;

FIG. 9 is a diagram showing a potential profile generated by the clock shown in FIG. 7;

FIG. 10 is a characteristic diagram showing a relationship between a gate voltage applied to a transfer electrode and a dark current.

FIG. 11 is a process diagram (first half) of a method for manufacturing a CCD solid-state imaging device according to the present invention.

FIG. 12 is a process diagram (second half) of the method for manufacturing a CCD solid-state imaging device according to the present invention;

FIG. 13 is a configuration diagram of a light receiving section of a conventional CCD solid-state imaging device.

[Explanation of symbols]

3 ... light receiving section, 4 ... accumulating section, 7 ... horizontal charge transfer path, 10 ...
Semiconductor substrate, 11: channel layer, 12: insulating layer, 15,
B ₁ , B ₂ -... barrier layer, 21, 22, G ₁ , G ₂ , G
₃ ... Transfer electrodes.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/148 H01L 21/339 H01L 29/762 H04N 5/335

Claims (4)

(57) [Claims] 1. A CCD solid-state imaging device having a charge transfer path group having a photoelectric conversion function and a charge transfer function, the charge transfer path group comprising: a channel layer for transferring signal charges; A first electrode group including a plurality of first type and second type electrodes alternately formed along a charge transfer direction on a surface region of the insulating layer; An electrode group; a barrier portion formed in a channel layer below every second electrode of the second type along the charge transfer direction with respect to the second type of electrode; The formed first electrode of the second electrode group and the second electrode of the first electrode group adjacent to the first electrode on the side of the charge transfer direction are connected to the third electrode of the three-phase clock signal. A first electric wiring for applying a clock signal of one phase; A second electric wiring for applying a clock signal of a second phase of the three-phase clock signal is provided to a third electrode of the second electrode group adjacent to the second electrode on the side of the charge transfer direction. A third electric wiring for applying a clock signal of a third phase of the three-phase clock signal to a fourth electrode of the first electrode group adjacent to the third electrode on the side of the charge transfer direction; And at the time of imaging, the first electric wiring, the second electric wiring, and the third electric wiring are used for all of the first electric wiring.
A voltage is applied to the electrodes of the second electrode group and the electrodes of the second electrode group so as to form a potential well group corresponding to a pixel generated in a channel layer region where the barrier portion is not formed. The three-phase clock signal is applied to the electrodes of the electrode group and the electrodes of the second electrode group via the first electric wiring, the second electric wiring, and the third electric wiring, and is applied to the potential well. A CCD solid-state imaging device, wherein an integrated signal charge is transferred separately from signal charges integrated in another potential well. 2. A voltage value applied to all the electrodes of the first electrode group and the electrodes of the second electrode group during the imaging is equal to or less than a pinning voltage value, and the clock signal is a pinning voltage and a pinning voltage. 2. The CCD according to claim 1, wherein a voltage value higher than the voltage is generated alternately.
Solid-state imaging device. 3. A method of manufacturing a CCD solid-state imaging device having a charge transfer path group having a photoelectric conversion function and a charge transfer function, wherein the method of manufacturing the charge transfer path group includes a method of manufacturing a semiconductor substrate of a first conductivity type. A step of forming a channel layer for transferring signal charges on the surface; a step of forming an insulating layer on one surface of the channel layer; and a plurality of the insulating layers having a surface region alternately arranged along the charge transfer direction. Forming a first electrode group including a plurality of first type electrodes on a first region group of the first and second region groups including the first and second regions; Forming a first conductivity type barrier portion in a channel layer below the second region by a predetermined number of two or more along the charge transfer direction with respect to a region; Are electrically isolated, and a plurality of second regions are formed on the second group of regions. Forming a second electrode group composed of the following types of electrodes; and at the time of imaging, all the electrodes of the first electrode group and the electrodes of the second electrode group are formed in a channel layer region where the barrier portion is not formed. A voltage for forming a potential well group corresponding to a generated pixel is supplied, and at the time of charge transfer, signal charges accumulated in a potential well are separated from signal charges accumulated in other potential wells to perform charge transfer.
Providing a wiring for supplying clock signals of a number of phases equal to or greater than the number of phases to the first electrode group and the second electrode group. 4. The method according to claim 1, wherein the predetermined number is two, the number of phases of the clock signal is three, and the step of applying the electric wiring includes a step of forming a second one of the second electrode group formed above the barrier portion. A first phase clock signal of the three-phase clock signal is applied to a first electrode and a second electrode of the first electrode group adjacent to the first electrode on the side of the charge transfer direction. A first sub-step of providing one electrical wiring; and a third electrode of the second electrode group adjacent to the second electrode on the side of the charge transfer direction. A second sub-step of providing a second electrical wiring for applying a phase clock signal; and a fourth electrode of the first electrode group adjacent to the third electrode on the side of the charge transfer direction. A third sub-step of providing third electrical wiring for applying a clock signal of a third phase of the three-phase clock signal; Method of manufacturing a CCD solid-state imaging device according to claim 3, characterized in that it comprises.