JPH07235634A - Power semiconductor module - Google Patents

Power semiconductor module

Info

Publication number
JPH07235634A
JPH07235634A JP4768694A JP4768694A JPH07235634A JP H07235634 A JPH07235634 A JP H07235634A JP 4768694 A JP4768694 A JP 4768694A JP 4768694 A JP4768694 A JP 4768694A JP H07235634 A JPH07235634 A JP H07235634A
Authority
JP
Japan
Prior art keywords
copper circuit
power semiconductor
auxiliary
terminal
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4768694A
Other languages
Japanese (ja)
Inventor
Saburo Okumura
三郎 奥村
Yorihide Toki
頼秀 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansha Electric Manufacturing Co Ltd
Original Assignee
Sansha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansha Electric Manufacturing Co Ltd filed Critical Sansha Electric Manufacturing Co Ltd
Priority to JP4768694A priority Critical patent/JPH07235634A/en
Publication of JPH07235634A publication Critical patent/JPH07235634A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PURPOSE:To obtain a high-speed power semiconductor module where inputted control signals pre hardly affected by a main current. CONSTITUTION:An auxiliary insulating board 2b provided with an auxiliary copper circuit 10 is mounted on copper circuits 9a, 9b, and 9c where a control terminal 8 aunt, of terminals led outside of a case is mounted, a control lead-nut common terminal 7 is mounted on the auxiliary copper circuit 10, and furthermore the auxiliary copper circuit 10 and the one main electrode of a power semiconductor chip 3a are connected together with a bonding wire.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、電力用半導体チップ
から銅回路へのワイヤボンディングを改良した電力用半
導体モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module with improved wire bonding from a power semiconductor chip to a copper circuit.

【０００２】[0002]

【従来の技術】従来、この種の電力用半導体モジュール
としては、例えば図２に示す構造のものがある。すなわ
ち、２ａは一方の面がその必要な個所にメタライズ又は
直接銅が張り付けられた第１，第２，第３の銅回路９
ａ，９ｂ，９ｃが設けられ、他方の面にメタライズ又は
直接銅が張り付けられた酸化アルミニウム又は窒化アル
ミニウム等の良熱伝導性で絶縁性の絶縁基板である。こ
の絶縁基板２ａは半田を介して、銅、鉄等の金属基板１
に取り付けられている。一方、銅回路９ａ，９ｂ，９ｃ
の必要な個所に半田を付け、この半田上例えば第１の銅
回路９ａの半田上に、ＩＧＢＴ，ＭＯＳＦＥＴ，バイポ
ーラトランジスタ，ＧＴＯ等の制御電極を有する電力用
半導体チップ３ａと、フライホイールダイオードのチッ
プ３ｂさらにコレクタ，ドレイン，アノード等に用いる
第１の主電極用端子５を搭載している。また、第２の銅
回路９ｂの半田上にエミッタ，ソース，カソード等に用
いる第２の主電極用端子６と制御引き出し用コモン端子
１７を搭載し、さらに第３の銅回路９ｃの半田上にベー
ス、ゲート等の制御端子８をそれぞれ搭載し、半田付け
され取り付けられている。そして、チップ３ａの制御電
極と第３の銅回路９ｃ間をボンディングワイヤ１４をボ
ンディングし、チップ３ａの第２の主電極とチップ３ｂ
の主電極さらに第２の銅回路９ｂとの間をワイヤ１５を
ボンティングによって接続されている。この後、金属基
板１の端部に図示しないシリコンゴムを塗布し、図示し
ない樹脂製ケースを接着し、ケース内にシリコンゴム，
エポキシ樹脂等の樹脂を封止して電力用半導体モジュー
ルが形成される。2. Description of the Related Art Conventionally, as this type of power semiconductor module, there is, for example, a structure shown in FIG. That is, 2a is a first, second, and third copper circuit 9 in which one surface is metallized or copper is directly attached to the required place.
a, 9b, 9c are provided, and the insulating substrate has good thermal conductivity and insulation, such as aluminum oxide or aluminum nitride, which is provided with metallized or copper directly adhered to the other surface. This insulating substrate 2a is a metal substrate 1 made of copper, iron or the like via solder.
Is attached to. On the other hand, copper circuits 9a, 9b, 9c
Of the flywheel diode and a power semiconductor chip 3a having a control electrode such as an IGBT, a MOSFET, a bipolar transistor, or a GTO on this solder, for example, on the solder of the first copper circuit 9a. 3b is further provided with a first main electrode terminal 5 used for a collector, a drain, an anode and the like. Further, the second main electrode terminal 6 used for the emitter, the source, the cathode and the like and the control lead-out common terminal 17 are mounted on the solder of the second copper circuit 9b, and further on the solder of the third copper circuit 9c. Control terminals 8 such as a base and a gate are mounted, respectively, and soldered and attached. Then, a bonding wire 14 is bonded between the control electrode of the chip 3a and the third copper circuit 9c, and the second main electrode of the chip 3a and the chip 3b.
A wire 15 is connected between the main electrode and the second copper circuit 9b by bonding. After that, silicone rubber (not shown) is applied to the end of the metal substrate 1, and a resin case (not shown) is adhered.
A resin such as an epoxy resin is sealed to form a power semiconductor module.

【０００３】このような構成の電力半導体モジュールの
動作について述べると、電力用半導体チップ３ａへの制
御信号が制御端子８とコモン端子１７との間に入力され
ると、この制御信号により電力用半導体チップ３ａはオ
ン、オフされる。そして、制御された電流が第１の主電
極用端子５から第１の銅回路９ａ、電力用半導体チップ
３ａ、ワイヤ１５、第２の銅回路９ｂを介して第２の主
電極用端子６に向かって流れる。The operation of the power semiconductor module having such a structure will be described. When a control signal for the power semiconductor chip 3a is input between the control terminal 8 and the common terminal 17, the power semiconductor is driven by this control signal. The chip 3a is turned on and off. Then, the controlled current flows from the first main electrode terminal 5 to the second main electrode terminal 6 via the first copper circuit 9a, the power semiconductor chip 3a, the wire 15, and the second copper circuit 9b. Flowing toward.

【０００４】[0004]

【発明が解決しようとする課題】このような従来の電力
用半導体モジュールにおいては、コモン端子１７が第２
の銅回路９ｂ上に設けられており、制御端子８とコモン
端子１７との間隔が長くかつ制御端子８、第３の銅回路
９ｃ、ワイヤ１４、チップ３ａ、ワイヤ１５、第２の銅
回路９ｂ及びコモン端子１７が形成する面積が大きいた
め、２つの主電極用端子５、６間に流れる電流によって
生じる磁束が大きくなり、電力用半導体モジュールのス
イッチング動作による磁束の変化がノイズとなり制御信
号に重畳され、電力用半導体モジュールが誤動作すると
いう問題があった。In such a conventional power semiconductor module, the common terminal 17 is the second one.
Is provided on the copper circuit 9b, the distance between the control terminal 8 and the common terminal 17 is long, and the control terminal 8, the third copper circuit 9c, the wire 14, the chip 3a, the wire 15, and the second copper circuit 9b are provided. Also, since the area formed by the common terminal 17 is large, the magnetic flux generated by the current flowing between the two main electrode terminals 5 and 6 is large, and the change in the magnetic flux due to the switching operation of the power semiconductor module becomes noise and is superimposed on the control signal. Therefore, there is a problem that the power semiconductor module malfunctions.

【０００５】[0005]

【課題を解決するための手段】本発明は、上記の問題点
を解決するためになされたもので、金属基板上に取り付
けられた絶縁基板の一方の面に設けられた第１の銅回路
上に制御電極を有する電力用半導体チップを搭載固定す
るとともに一方の主電極用端子が設けられ、さらに上記
絶縁基板の一方の面に設けられた第２の銅回路上に上記
電力用半導体チップの他方の主電極用端子が設けられた
電力用半導体モジュールにおいて、上記絶縁基板の一方
の面に第３の銅回路が設けられこの第３の銅回路上に上
記電力用半導体チップの制御端子と第１の補助銅回路を
有する第１の補助絶縁基板とが取付けられ、さらに上記
第１の補助銅回路上に制御引き出し用コモン端子が取り
付けられ、第１の補助銅回路と上記電力用半導体チップ
の他方の主電極とがワイヤボンディングされている。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is provided on a first copper circuit provided on one surface of an insulating substrate mounted on a metal substrate. A power semiconductor chip having a control electrode is mounted and fixed on one side, one main electrode terminal is provided, and the other side of the power semiconductor chip is provided on a second copper circuit provided on one surface of the insulating substrate. In the power semiconductor module provided with the main electrode terminal, the third copper circuit is provided on one surface of the insulating substrate, and the control terminal of the power semiconductor chip and the first copper circuit are provided on the third copper circuit. A first auxiliary insulating substrate having a second auxiliary copper circuit is mounted, and a common terminal for control lead-out is further mounted on the first auxiliary copper circuit, and the other of the first auxiliary copper circuit and the power semiconductor chip is attached. With the main electrode of It is wire-bonded.

【０００６】また、金属基板上に取り付けられた絶縁基
板の一方の面に設けられた第１の銅回路上に制御電極を
有する電力用半導体チップを搭載固定するとともに一方
の主電極用端子が設けられ、さらに上記絶縁基板の一方
の面に設けられた第２の銅回路上に上記電力用半導体チ
ップの他方の主電極用端子が設けられた電力用半導体モ
ジュールにおいて、上記第２の銅回路上に、第２の補助
銅回路を有する第２の補助絶縁基板が取付けられ、さら
に上記第２の補助銅回路上に上記制御端子が取付けら
れ、上記第２の補助銅回路と上記電力用半導体チップの
制御電極とがワイヤボンディングされている。A power semiconductor chip having a control electrode is mounted and fixed on a first copper circuit provided on one surface of an insulating substrate mounted on a metal substrate, and one main electrode terminal is provided. A power semiconductor module in which the other main electrode terminal of the power semiconductor chip is provided on the second copper circuit provided on one surface of the insulating substrate, and the second copper circuit is provided on the second copper circuit. A second auxiliary insulating substrate having a second auxiliary copper circuit, the control terminal is mounted on the second auxiliary copper circuit, and the second auxiliary copper circuit and the power semiconductor chip. And the control electrode thereof are wire-bonded.

【０００７】[0007]

【作用】この発明の電力用半導体モジュールでは、制御
端子が取り付けられる第３の銅回路上に第１の補助銅回
路を有する第１の補助絶縁基板を取付け、この第１の補
助銅回路上に制御引き出し用コモン端子を取り付け、コ
モン端子と主電極とをワイヤボンディングするので、制
御端子とコモン端子との間隔が小さくなり、これら制御
端子、コモン端子とボンディングワイヤとにより形成さ
れる面積が小さくなり、主電極間に流れる電流によって
生じる磁束が小さくなる。これにより、電力用半導体の
スイッチングによって生じるノイズは抑制される。In the power semiconductor module of the present invention, the first auxiliary insulating substrate having the first auxiliary copper circuit is mounted on the third copper circuit to which the control terminal is mounted, and the first auxiliary copper circuit is mounted on the first auxiliary insulating circuit. Since the common terminal for control lead-out is attached and the common terminal and the main electrode are wire-bonded, the space between the control terminal and the common terminal becomes small, and the area formed by these control terminal, common terminal and bonding wire becomes small. The magnetic flux generated by the current flowing between the main electrodes is reduced. As a result, noise generated by switching of the power semiconductor is suppressed.

【０００８】また、第２の銅回路上に第２の補助銅回路
を有する第２の補助絶縁基板を取付け、第２の補助銅回
路上に制御端子を取り付け、第２の補助銅回路と制御電
極とをワイヤボンディングするので、制御端子とコモン
端子との間隔が小さくなり、これら端子とワイヤとによ
り形成される面積が小さくなり、主電極間に流れる電流
によって生じる磁束が小さくなる。これにより、電力用
半導体のスイッチングによって生じるノイズは抑制され
る。Further, a second auxiliary insulating substrate having a second auxiliary copper circuit is mounted on the second copper circuit, a control terminal is mounted on the second auxiliary copper circuit, and the second auxiliary copper circuit is controlled. Since the electrodes are wire-bonded, the distance between the control terminal and the common terminal is reduced, the area formed by these terminals and the wire is reduced, and the magnetic flux generated by the current flowing between the main electrodes is reduced. As a result, noise generated by switching of the power semiconductor is suppressed.

【０００９】[0009]

【実施例】以下、この発明をその一実施例を示す図１に
基づいて詳細に説明する。図１において図２と同じ符号
は同じ機能のものを示す。図２の従来例と異なる点は、
制御端子８が接続される第３の銅回路９ｃ上に、一方の
面に第１の補助銅回路１０が設けられた第１の補助絶縁
基板２ｂが半田、接着剤等により接着され、第１の補助
銅回路１０上に制御引き出し用コモン端子７が設けられ
ている点、さらにチップ３ａの第２の主電極と、第１の
補助銅回路１０との間をボンディングワイヤ１６により
ボンディングした点にある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIG. 1 showing an embodiment thereof. 1, the same reference numerals as those in FIG. 2 indicate the same functions. 2 is different from the conventional example shown in FIG.
On the third copper circuit 9c to which the control terminal 8 is connected, the first auxiliary insulating substrate 2b having the first auxiliary copper circuit 10 provided on one surface is bonded by solder, adhesive, or the like. The common terminal 7 for control lead-out is provided on the auxiliary copper circuit 10 and the point where the second main electrode of the chip 3a and the first auxiliary copper circuit 10 are bonded by the bonding wire 16. is there.

【００１０】これにより、制御端子８とコモン端子７と
の間隔が短くかつ、制御端子８とコモン端子７及びボン
ディングワイヤ４で形成される面積が小さく、２つの主
電極間に流れる電流によって生じる磁束が小さく、ノイ
ズの発生が少なくなり、電力用半導体モジュールの誤動
作がなくなる。As a result, the distance between the control terminal 8 and the common terminal 7 is short, the area formed by the control terminal 8 and the common terminal 7 and the bonding wire 4 is small, and the magnetic flux generated by the current flowing between the two main electrodes is small. Is small, noise is reduced, and malfunction of the power semiconductor module is eliminated.

【００１１】上記実施例では、制御端子８が接続される
第３の銅回路９ｃ上に、第１の補助絶縁基板を介してコ
モン端子７を設けているが、第２の主電極用端子６が接
続される第２の銅回路９ｂ上に第２の補助銅回路を設け
た第２の補助絶縁基板を半田、接着剤等により接着し、
この第２の補助銅回路上に制御端子を設け、さらにチッ
プ３の制御電極と第２の補助銅回路間をワイヤによりボ
ンディングしてもよい。この実施例においても、制御端
子とコモン端子との間隔が短く、かつ、制御端子とコモ
ン端子及びワイヤで形成される面積が小さくなり、この
面積を通る磁束が少なく、ノイズの発生は少なくなり、
電力半導体モジュールの誤動作はなくなる。In the above embodiment, the common terminal 7 is provided on the third copper circuit 9c to which the control terminal 8 is connected via the first auxiliary insulating substrate, but the second main electrode terminal 6 is used. A second auxiliary insulating substrate provided with a second auxiliary copper circuit on the second copper circuit 9b connected to
A control terminal may be provided on the second auxiliary copper circuit and a wire may be bonded between the control electrode of the chip 3 and the second auxiliary copper circuit. Also in this embodiment, the distance between the control terminal and the common terminal is short, and the area formed by the control terminal, the common terminal and the wire is small, the magnetic flux passing through this area is small, and the generation of noise is small,
The malfunction of the power semiconductor module is eliminated.

【００１２】[0012]

【発明の効果】以上説明したように、この発明の半導体
モジュールは、制御端子又は制御引き出し用コモン端子
が接続される銅回路上に設けた補助絶縁基板にコモン端
子又は制御端子を設けているので、制御端子とコモン端
子及びワイヤで形成される面積が小さくなり、この面積
を通る磁束も小さく、ノイズの発生は小さくなり、電力
用半導体モジュールの誤動作はなくなる。As described above, in the semiconductor module of the present invention, the common terminal or the control terminal is provided on the auxiliary insulating substrate provided on the copper circuit to which the control terminal or the control lead-out common terminal is connected. The area formed by the control terminal, the common terminal, and the wire is reduced, the magnetic flux passing through this area is also reduced, the generation of noise is reduced, and the malfunction of the power semiconductor module is eliminated.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の電力用半導体モジュールの一実施例を
示す概略平面図と概略正面図である。FIG. 1 is a schematic plan view and a schematic front view showing an embodiment of a power semiconductor module of the present invention.

【図２】従来の電力用半導体モジュールの概略平面図と
概略正面図である。FIG. 2 is a schematic plan view and a schematic front view of a conventional power semiconductor module.

【符号の説明】[Explanation of symbols]

１ 金属基板 ２ａ 絶縁基板 ２ｂ （第１の）補助絶縁基板 ３ａ 電力用半導体チップ ３ｂ フライホイルダイオード ５ （第１の）主電極用端子 ６ （第２の）主電極用端子 ７ コモン端子 ８ 制御端子 ９ａ 第１の銅回路 ９ｂ 第２の銅回路 ９ｃ 第３の銅回路 １０ （第１の）補助銅回路 １４，１５，１６ ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 metal substrate 2a insulating substrate 2b (first) auxiliary insulating substrate 3a power semiconductor chip 3b flywheel diode 5 (first) main electrode terminal 6 (second) main electrode terminal 7 common terminal 8 control terminal 9a 1st copper circuit 9b 2nd copper circuit 9c 3rd copper circuit 10 (1st) auxiliary copper circuit 14,15,16 Bonding wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 金属基板上に取り付けられた絶縁基板の
一方の面に設けられた第１の銅回路上に制御電極を有す
る電力用半導体チップを搭載固定するとともに一方の主
電極用端子が設けられ、さらに上記絶縁基板の一方の面
に設けられた第２の銅回路上に上記電力用半導体チップ
の他方の主電極用端子が設けられた電力用半導体モジュ
ールにおいて、上記絶縁基板の一方の面に第３の銅回路
が設けられ、この第３の銅回路上に上記電力用半導体チ
ップの制御端子と第１の補助銅回路を有する第１の補助
絶縁基板とが取付けられ、さらに上記第１の補助銅回路
上に制御引き出し用コモン端子が取り付けられ、第１の
補助銅回路と上記電力用半導体チップの他方の主電極と
がワイヤボンディングされたことを特徴とする電力用半
導体モジュール。1. A power semiconductor chip having a control electrode is mounted and fixed on a first copper circuit provided on one surface of an insulating substrate mounted on a metal substrate, and one main electrode terminal is provided. A power semiconductor module in which the other main electrode terminal of the power semiconductor chip is provided on a second copper circuit provided on one surface of the insulating substrate, wherein one surface of the insulating substrate is provided. Is provided with a third copper circuit, and the control terminal of the power semiconductor chip and the first auxiliary insulating substrate having the first auxiliary copper circuit are mounted on the third copper circuit, and the first copper circuit is further provided. A common terminal for control lead-out is mounted on the auxiliary copper circuit, and the first auxiliary copper circuit and the other main electrode of the power semiconductor chip are wire-bonded to each other. 【請求項２】 金属基板上に取り付けられた絶縁基板の
一方の面に設けられた第１の銅回路上に制御電極を有す
る電力用半導体チップを搭載固定するとともに一方の主
電極用端子が設けられ、さらに上記絶縁基板の一方の面
に設けられた第２の銅回路上に上記電力用半導体チップ
の他方の主電極用端子が設けられた電力用半導体モジュ
ールにおいて、上記第２の銅回路上に、第２の補助銅回
路を有する第２の補助絶縁基板が取付けられ、さらに上
記第２の補助銅回路上に上記制御端子が取付けられ、上
記第２の補助銅回路と上記電力用半導体チップの制御電
極とがワイヤボンディングされたことを特徴とする電力
用半導体モジュール。2. A power semiconductor chip having a control electrode is mounted and fixed on a first copper circuit provided on one surface of an insulating substrate mounted on a metal substrate, and one main electrode terminal is provided. A power semiconductor module in which the other main electrode terminal of the power semiconductor chip is provided on the second copper circuit provided on one surface of the insulating substrate, and the second copper circuit is provided on the second copper circuit. A second auxiliary insulating substrate having a second auxiliary copper circuit, the control terminal is mounted on the second auxiliary copper circuit, and the second auxiliary copper circuit and the power semiconductor chip. A semiconductor module for electric power, characterized in that it is wire-bonded to the control electrode of.
JP4768694A 1994-02-22 1994-02-22 Power semiconductor module Pending JPH07235634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4768694A JPH07235634A (en) 1994-02-22 1994-02-22 Power semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4768694A JPH07235634A (en) 1994-02-22 1994-02-22 Power semiconductor module

Publications (1)

Publication Number Publication Date
JPH07235634A true JPH07235634A (en) 1995-09-05

Family

ID=12782173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4768694A Pending JPH07235634A (en) 1994-02-22 1994-02-22 Power semiconductor module

Country Status (1)

Country Link
JP (1) JPH07235634A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018014354A (en) * 2016-07-19 2018-01-25 富士電機株式会社 Semiconductor device manufacturing method and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018014354A (en) * 2016-07-19 2018-01-25 富士電機株式会社 Semiconductor device manufacturing method and semiconductor device

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