JP2016195223A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing unintended turn-on of an SiC semiconductor element.SOLUTION: A semiconductor device comprises: a semiconductor chip that consists of an SiC semiconductor, and that has a source electrode and a gate electrode on a front face thereof; and a capacitor chip provided on the front face of the semiconductor chip, and that electrically connects between the source electrode and the gate electrode.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a semiconductor device, in particular, a power semiconductor module including a power semiconductor chip and a manufacturing method thereof.

  As an example of a power semiconductor module, there is a power semiconductor module used in a bridge circuit constituted by an upper arm and a lower arm, with a switching element and a free wheel diode connected in reverse parallel thereto as one arm. In such a bridge circuit, when the switching element is, for example, a MOSFET, when the MOSFET of one arm turns on at high speed and changes between its drain and source at a high voltage change rate (dV / dt), the other arm Displacement current is generated in the parasitic capacitance between the gate and source of the MOSFET, and the gate-source voltage increases. When the gate-source voltage exceeds the gate threshold voltage, the MOSFET of the other arm is turned on unintentionally. Then, a through current flows through the upper and lower arms, resulting in a short circuit state, which may cause destruction of the MOSFET, shortening its life, and reducing reliability. Unintended turn-on is likely to occur particularly in a unipolar device having a high switching speed, such as a MOSFET.

In order to suppress unintended turn-on, the gate resistance of the gate driving circuit is increased to reduce the impedance and suppress the voltage rise between the gate and the source. However, increasing the gate resistance also limits the switching speed.
As another method for preventing unintended turn-on, there is a semiconductor device in which a capacitor is connected between the gate and emitter of an IGBT to suppress the generation of noise or fluctuation of the gate-emitter voltage (Patent Document 1).

JP 2004-14547 A

  In one embodiment, the semiconductor device described in Patent Literature 1 is provided with an insulating film provided on a gate electrode layer of an IGBT and an emitter electrode layer extending so as to cover the insulating film. Thus, an MIM (Metal-Insulator-Metal) type capacitor including a gate electrode layer, an insulating film, and an extension portion of the emitter electrode layer is formed. This MIM type capacitor is obtained by sequentially forming a gate electrode, an insulating film thereon, and an emitter electrode so as to cover the gate electrode in the process of manufacturing a semiconductor element. In another embodiment, the capacitor is mounted on a base substrate different from the multilayer substrate on which the IGBT is mounted.

  However, if a capacitor is mounted on the base substrate, the inductance of the wiring between the multilayer substrate and another base substrate is large, so that it is difficult to obtain the effect of the capacitor, and it may not be possible to prevent erroneous turn-on. . Further, in the process of forming the MIM type capacitor, it is difficult to form an insulating film having a predetermined capacity with high quality when the semiconductor element is made of a SiC semiconductor. In addition, even when the crystal quality of SiC has been greatly improved from the past, the process may still cause deterioration of the crystal quality, which in turn causes deterioration of the characteristics of the SiC semiconductor element or the yield. Furthermore, since the manufacturing process of the SiC semiconductor device is already complicated due to the large number of masks, especially when the semiconductor device has a MOS structure, the above-described MIM type capacitor can be selected using a photomask. It is not easy to form by typical deposition.

  The present invention advantageously solves the above problem, and provides a semiconductor device capable of avoiding undesired turn-on by avoiding characteristic deterioration of SiC semiconductor elements and interference with wiring members, and an advantageous manufacturing method thereof. The purpose is to provide.

One aspect of the present invention is a semiconductor chip made of a SiC semiconductor and having a source electrode and a gate electrode on the front surface, and provided on the front surface of the semiconductor chip, between the source electrode and the gate electrode. And a capacitor chip that electrically connects the two.
Another aspect of the present invention is a step of disposing an insulating resin between a source electrode and a gate electrode on the front surface of a semiconductor chip made of a SiC semiconductor, and disposing on the front surface of the semiconductor chip. A step of disposing a capacitor chip on the insulating resin and electrically connecting the source electrode and the gate electrode with the capacitor chip.
Still another aspect of the present invention provides a process of preparing an assembly including a printed circuit board and a plurality of conductive posts inserted in through holes of the printed circuit board, and at least the conductive posts of the assembly. First, the step of temporarily fixing the capacitor chip, and simultaneously connecting the ends of the plurality of conductive posts to the source electrode and the gate electrode on the front surface of the semiconductor chip made of SiC semiconductor, And a step of electrically connecting the source electrode and the gate electrode.

  According to the semiconductor device of the present invention, unintended turn-on can be suppressed while avoiding deterioration of the characteristics of the SiC semiconductor element and interference with the wiring member.

It is typical sectional drawing of the power semiconductor module of one Embodiment of this invention. It is a top view in the II-II line of FIG. It is a top view in the III-III line of FIG. It is a top view of a semiconductor chip. It is sectional drawing of a semiconductor chip and its vicinity. It is a circuit diagram of a power semiconductor module. It is a graph which shows the relationship between gate resistance Rg and built-in capacitor capacity Cgs. It is sectional drawing of the semiconductor chip of a modification, and its vicinity. It is a top view of the semiconductor chip of a modification. It is a top view of the semiconductor chip of a modification. It is a graph which shows the relationship between gate resistance and switching loss. It is a graph which shows the relationship between a switching frequency and total loss. It is explanatory drawing of the manufacturing method of one Embodiment of this invention. It is explanatory drawing of the manufacturing method of another embodiment of this invention. It is explanatory drawing of the manufacturing method of another embodiment of this invention. It is explanatory drawing of the manufacturing method of another embodiment of this invention.

  Embodiments of a semiconductor device of the present invention will be specifically described below with reference to the drawings. Note that the term “electrically and mechanically connected” used in the description of the present application is not limited to the case where the objects are connected to each other by direct bonding, such as solder or a sintered metal material. The case where the objects are connected to each other through the conductive bonding material is also included.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a power semiconductor module 10 according to Embodiment 1 of the present invention. FIG. 2 is a plan view of the power semiconductor module 10 of FIG. 1 at the position II-II. 1 corresponds to a cross-sectional view taken along the line II in FIG. FIG. 3 is a plan view of the power semiconductor module 10 of FIG. 1 at the position III-III. The power semiconductor module 10 is an example of a 2-in-1 module including an upper arm and a lower arm, and FIGS. 1 to 3 show one arm of the 2-in-1 module.

As shown in FIGS. 1 to 3, the power semiconductor module 10 includes a semiconductor chip 12 and a capacitor chip 16. The power semiconductor module 10 further includes a laminated substrate 11, a semiconductor chip 13, a printed board 14, a first conductive post 15 </ b> A, a second conductive post 15 </ b> C, and an insulating resin 17.
The multilayer substrate 11 includes an insulating plate 11a, a circuit board 11b provided on the main surface (upper surface in the drawing) of the insulating plate 11a, and a metal plate 11c provided on the back surface (lower surface in the drawing) of the insulating plate 11a. Has been.

FIG. 2 shows a plan view at the position of line II-II in FIG. 1 corresponds to a cross-sectional view taken along the line II in FIG. In FIG. 2, the circuit board 11b is selectively formed on the main surface of the insulating plate 11a, and includes a first area 11b1, a second area 11b2, a third area 11b3, and a fourth area 11b4.
The semiconductor chip 12 and the semiconductor chip 13 are provided side by side in the first region 11b1 of the circuit board 11b. A drain terminal 19A, which is an external terminal, is provided at the corner of the first region 11b1.

1 and 2, a semiconductor chip 12 as a switching element is an example of a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor chip 13 is an example of a diode connected in reverse parallel to the semiconductor chip 12. On the front surface of the semiconductor chip 12, a source electrode 12a as an output electrode and a gate electrode 12b as a control electrode are provided. Is provided. A capacitor chip 16 that electrically connects the source electrode 12 a and the gate electrode 12 b is provided on the front surface of the semiconductor chip 12. The capacitor chip 16 will be described in detail later.
Further, a drain electrode (not shown) that is an input electrode is provided on the back surface of the semiconductor chip 12. The drain electrode and the first region 11b1 of the circuit board 11b are electrically and mechanically connected by a solder 20 that is a conductive bonding material.

  Further, an anode electrode 13a is provided on the front surface of the semiconductor chip 13, and a cathode electrode (not shown) is provided on the back surface. The cathode electrode and the first region 11b1 of the circuit board 11b are electrically and mechanically connected by the solder 20.

The first region 11b1 of the circuit board 11b and the drain terminal 19A are electrically and mechanically connected by a conductive bonding material such as solder, ultrasonic bonding or welding.
A source terminal 19B as an external terminal is provided in the second region 11b2 and the fourth region 11b4 of the circuit board 11b, and a gate terminal 19C as an external terminal is provided in the third region 11b3. Alternatively, they are electrically and mechanically connected by welding or the like.

As shown in FIG. 1, the printed circuit board 14 is provided to face the front surface of the semiconductor chip 12, the front surface of the semiconductor chip 13, and the circuit board 11 b of the multilayer substrate 11. The printed circuit board 14 includes an insulating layer 14a and a metal layer 14b disposed on at least one surface of the insulating layer 14a.
FIG. 3 shows a plan view at the position of line III-III in FIG. In FIG. 3, the metal layer 14b is selectively formed on one surface of the insulating layer 14a and includes a first region 14b1 and a second region 14b2.
A source terminal 19B is electrically and mechanically connected to the first region 14b1 of the metal layer 14b.

  The first region 14b1 of the metal layer 14b is a region for electrically connecting the source electrode 12a of the semiconductor chip 12 and the anode electrode of the semiconductor chip 13 to the source terminal 19B. The second region 14b2 of the metal layer 14b is a region for electrically connecting the gate electrode 12b of the semiconductor chip 12 and the third region 11b3 of the circuit board 11b.

  Between the metal layer 14b of the printed circuit board 14 and the front surface electrode of the semiconductor chip 12, the front surface electrode of the semiconductor chip 13, or the circuit board 11b of the multilayer substrate 11, a plurality of conductive posts 15A to 15D are provided. Is provided. In this specification, the conductive posts 15 </ b> A to 15 </ b> D are collectively referred to as the conductive posts 15. One of the conductive posts 15 is electrically and mechanically connected by solder 20 to the front surface electrode of the semiconductor chip 12, the front surface electrode of the semiconductor chip 13, or the circuit board 11 b of the laminated substrate 11. . The other of the conductive posts 15 penetrates through the insulating layer 14a of the printed board 14 and is electrically and mechanically connected to the metal layer 14b of the printed board 14 by soldering, brazing, or caulking.

  The first conductive post 15A electrically connects the first region 14b1 of the metal layer 14b and the source electrode of the semiconductor chip 12. The conductive post 15B electrically connects the first region 14b1 of the metal layer 14b and the anode electrode of the semiconductor chip 13. The second conductive post 15C electrically connects the second region 14b2 of the metal layer 14b and the gate electrode of the semiconductor chip 12. The conductive post 15D electrically connects the second region 14b2 of the metal layer 14b and the third region 11b3 of the circuit board 11b of the multilayer substrate 11.

  With the configuration described above, the source electrode of the semiconductor chip 12, the anode electrode of the semiconductor chip 13, and the source terminal 19B are electrically connected. Further, the gate electrode of the semiconductor chip 12 and the gate terminal 19C are electrically connected.

  The conductive post 15 and the printed board 14 have a function of a wiring member that electrically connects an electrode disposed on the front surface of the semiconductor chip 12 or 13 and an external terminal (source terminal 19B or gate terminal 19C). doing. Note that the wiring member is not limited to the combination of the conductive post 15 and the printed board 14, and for example, a bonding wire can be used. However, the wiring member using the conductive posts 15 is easier to bond the capacitor chip to the narrow gate electrode of the semiconductor chip 12 than the bonding wire.

  FIG. 4 shows a plan view of the semiconductor chip 12, and FIG. 5 shows a cross-sectional view of the semiconductor chip 12 in FIG. 4 and the vicinity thereof. A source electrode 12 a and a gate electrode 12 b are disposed on the front surface of the semiconductor chip 12. One of the two first conductive posts 15 </ b> A is joined to the source electrode 12 a by solder 20. Further, one second conductive post 15C is joined to the gate electrode 12b by solder 20. One of the terminals of the capacitor chip 16 is electrically and mechanically connected to the source electrode 12 a by the solder 20, and the other terminal is electrically and mechanically connected to the gate electrode 12 b by the solder 20.

  In order to suppress current variation in the surface of the semiconductor chip 12, the capacitor chip 16 is disposed so as to connect the longitudinal center of the source electrode 12a and the longitudinal center of the gate electrode 12b. Further, in order to suppress current imbalance in the two first conductive posts 15 </ b> A, the two first conductive posts 15 </ b> A are disposed at symmetrical positions at equal distances from the capacitor chip 16. The first conductive posts 15A are not limited to two examples, and may be one, or may be three or more.

  The capacitor chip 16 functions as a capacitor that electrically connects the source electrode 12a and the gate electrode 12b. Before the capacitor chip 16 is soldered, the insulating resin 17 is disposed between the source electrode 12a and the gate electrode 12b on the front surface of the semiconductor chip 12 by, for example, applying a polyimide resin. ing. The insulating resin 17 is formed between the capacitor chip 16 and the front surface of the semiconductor chip 12 and contacts the side surface of the capacitor chip 16. Further, the entire side surface between the two terminals of the capacitor chip 16 is subjected to a coating process that reduces wettability with solder. Accordingly, it is possible to effectively prevent the solder 20 on the source electrode 12a side and the solder 20 on the gate electrode 12b side that join the capacitor chip 16 from contacting each other and short-circuiting the electrodes. Even if the insulating resin 17 is not disposed, the solder 20 on the source electrode 12a side and the solder 20 on the gate electrode 12b side are prevented from coming into contact with each other and short-circuiting by appropriately adjusting the amount of solder. You can also

  FIG. 6 shows a circuit diagram of the power semiconductor module 10 according to this embodiment including the upper arm and the lower arm. 1 and 2 show the structure of the region A shown in FIG. A phenomenon in which the switching element is turned on unintentionally will be described with reference to FIG. When the semiconductor chip 12 which is a switching element is turned off, the gate current oscillates through the gate inductance Lg due to switching dv / dt at the time of turn-off. When the gate voltage becomes equal to or higher than the threshold due to the oscillation of the current, unintended turn-on occurs in the semiconductor chip 12. When the upper arm semiconductor chip 12 is turned on at high speed and the drain voltage changes at a high voltage change rate (dV / dt), the lower arm semiconductor chip 13 (diode chip) is reversely recovered, and the lower arm semiconductor chip is recovered. The gate voltage of the chip 12 increases rapidly. This gate voltage is a value obtained by multiplying the above-mentioned voltage increase rate (dV / dt) by the feedback capacitance of the semiconductor chip 12 of the lower arm. When the gate voltage of the lower-arm semiconductor chip 12 exceeds a threshold value, an unintended turn-on occurs in the lower-arm semiconductor chip 12.

  In the power semiconductor module 10 of this embodiment, a capacitor chip 16 having a current bypass effect is connected between a source electrode 12a and a gate electrode 12b. As a result, it is possible to suppress unintended turn-on by suppressing fluctuations in the gate voltage due to current oscillation or a high voltage change rate. In addition, since unintended turn-on can be suppressed without increasing the gate resistance, the gate resistance can be lowered and the switching speed of the semiconductor chip 12 can be increased. This is particularly advantageous for MOSFETs made of SiC having a high switching speed.

  Further, by electrically and mechanically connecting one terminal of the capacitor chip 16 to the source electrode 12a and the other terminal to the gate electrode 12b, the wiring distance between the capacitor chip and the gate electrode 12b is made substantially zero. Can do. Therefore, the inductance Lg of the gate wiring can be reduced as much as possible, and unintended turn-on can be further prevented. Also, as the inductance Lg of the gate wiring is smaller, unintended turn-on can be prevented even if the built-in capacitor capacitance Cgs is reduced. Therefore, unintended turn-on can be prevented with the small and small capacitor chip 16. The downsizing of the capacitor chip 16 facilitates the mounting of the capacitor chip 16 on the semiconductor chip 12.

  The graph shown in FIG. 7 is a graph showing the relationship between the gate resistance Rg and the built-in capacitor capacitance Cgs that can prevent unintended turn-on. FIG. 7 shows a case where a capacitor chip is provided in another part of the power semiconductor module as a comparative example. The inductance Lg of the gate wiring of the example of the present invention was 2.51 nH, and the inductance Lg of the gate wiring of the comparative example was 5.12 nH. As can be seen from FIG. 7, the inventive example was able to prevent unintended turn-on with a lower gate resistance and a lower capacitor capacity than the comparative example.

  As long as the capacitor chip 16 has a heat resistant temperature of about 200 ° C., the semiconductor chip 12 is not affected even if the semiconductor chip 12 generates heat during operation.

  For example, a capacitor chip 16 having a length of 1 mm, a width of 0.5 mm, and a height of 0.5 mm and a capacitance of 2.2 nF is used as the capacitor chip 16 of the present embodiment. Further, the semiconductor chip 12 made of SiC is, for example, a square whose front surface is about 3.0 mm on a side. In the semiconductor chip 12 of this size, as an example of the size of the source electrode 12a and the gate electrode 12b, the source electrode 12a is a rectangle having a long side of 2.5 mm and a short side of 1.5 mm, and the gate electrode 12b has a side of 0. .64 mm square. An example of the diameter of the first conductive post 15A and the second conductive post 15C is 0.45 mm, and an example of the length is 0.8 mm. 4 and 5 illustrate the case where the capacitor chip 16 and the semiconductor chip 12 are applied to the present invention.

  As shown in these drawings, the capacitor chip 16 does not interfere with the first conductive post 15A, the second conductive post 15C, and the printed circuit board 14 on the front surface of the semiconductor chip 12 made of SiC of the above size. Can be arranged. One of the terminals of the capacitor chip 16 can be joined to the source electrode 12a and the other can be joined to the gate electrode 12b.

  The area occupied by the gate electrode 12b in the front surface of the semiconductor chip 12 is relatively small. It is necessary to join not only the second conductive post 15C but also one of the terminals of the capacitor chip 16 to the small gate electrode 12b. It is preferable to devise to easily join one of the terminals of the capacitor chip 16 to the gate electrode 12b.

  For example, it is preferable to join one end of the capacitor chip 16 to the gate electrode 12b to which the solder 20 paste is applied, and then join the second conductive post 15C. Further, it is also preferable that the capacitor chip 16 is fixed to the second conductive post 15C and temporarily fixed before bonding, and the capacitor chip 16 is bonded simultaneously with the second conductive post 15C. It is also preferable that the capacitor chip 16 is sandwiched between the first conductive post 15A and the second conductive post 15C before joining, and the capacitor chip 16 is joined simultaneously with the second conductive post 15C in this sandwiched state.

  As a modification, as shown in FIG. 8, the diameter of the tip of the second conductive post 15 </ b> C on the side to be joined to the gate electrode 12 b is made smaller than the diameter on the side to be connected to the printed circuit board 14. Is preferred. Further, the second conductive post 15C preferably has a small diameter from the end connected to the printed circuit board 14 to the end connected to the gate electrode 12b, instead of being tapered. Since the main current does not flow through the second conductive post 15C and only a gate signal is transmitted from the outside, even if the tapered shape or the entire diameter is small, the electrical characteristics are not affected.

  As another modified example, as shown in FIG. 9, the area of the gate electrode 12b can be enlarged by making the planar shape of the gate electrode 12b a rectangle with one side extending in the direction extending toward the source electrode 12a. Further, if the chip area of the semiconductor chip 12 made of SiC is made larger than 3 mm on a side, the area of the gate electrode can be made relatively larger than the current state. In this case, it becomes easy to join one end of the capacitor chip 16 to the gate electrode 12b.

  As described above, the wiring member is not limited to the combination of the printed board 14 and the conductive post 15, and for example, a bonding wire can be used. When the wiring member is a bonding wire, it is difficult to wire bond the bonding electrode device to the gate electrode 12b after bonding one end of the capacitor chip 16 to the gate electrode 12b shown in FIG. Therefore, as shown in FIG. 10, when the wiring member is the bonding wire 18, the planar shape of the gate electrode 12b is a rectangle whose one side orthogonal to the one side extending in the direction extending toward the source electrode 12a is longer, It is preferable that the bondin wire and the capacitor chip 16 do not interfere with each other.

On the other hand, as shown in FIG. 9 or 10, when the area of the gate electrode 12 b is enlarged as compared with FIG. 4, the active area of the semiconductor chip 12 decreases and the on-resistance increases. Therefore, a comparison was made between the amount of reduction in switching loss due to bonding of the capacitor chip 16 and the increase in on-resistance due to reduction in the active area.
For example, the gate electrode 12b of the SiC semiconductor chip 12 of the side 3 mm, one side 0.64 mm, when doubled to an area 0.8 mm ² on an enlarged scale from the area 0.4 mm ^2, the active area of the semiconductor chip 5. It decreased from 67 mm ² to 5.26 mm ^2, the on-resistance is increased by about 7%.

  FIG. 11 is a graph showing the relationship between gate resistance and switching loss. As shown here, when the capacitor chip 16 is joined to the source electrode 12a and the gate electrode 12b on the front surface of the SiC semiconductor chip 12 having a side of 3 mm, the switching loss is reduced by about 50 compared to the case where the capacitor chip 16 is not joined. % Can be reduced.

The result of estimating the total loss from these data is shown in FIG. From FIG. 12, it can be seen that the total loss decreases by about 5% at the switching frequency of 20 kHz and decreases by 25% at the frequency of 100 kHz.
Thus, even if the area of the gate electrode 12b is increased to some extent, the effect obtained by bonding the capacitor chip 16 shown in the present embodiment is larger, so that the total loss is reduced particularly in a region where the switching frequency is high. Can be reduced. Since the SiC semiconductor chip can be switched at a higher frequency than the Si semiconductor chip, the effect of the present embodiment is great.

Next, members other than the capacitor chip 16 in the power semiconductor module 10 shown in FIG. 1 will be described more specifically.
In the multilayer substrate 11, the insulating plate 11a is made of an insulating ceramic such as aluminum nitride, silicon nitride, or aluminum oxide. Insulating ceramics is advantageous for use in the power semiconductor module of the present embodiment because it has higher thermal conductivity than insulating resin. The circuit board 11b and the metal plate 11c are made of a conductive metal such as copper or aluminum. For example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Blazing) substrate can be used as the multilayer substrate 11.

  In the present embodiment, the semiconductor chip 12 is an example of a vertical power MOSFET having a source electrode and a gate electrode on the front surface and a drain electrode on the back surface. The semiconductor chip 12 is not limited to a vertical type, and may be a horizontal type semiconductor chip in which a plurality of types of electrodes are arranged only on the front surface of the semiconductor chip 12.

The semiconductor chip 12 is not limited to a power MOSFET, but can be another switching element, for example, an IGBT (insulated gate bipolar transistor). When the semiconductor chip 12 is an IGBT, the back electrode is a collector electrode, and the front electrode is an emitter electrode and a gate electrode. When the semiconductor chip 12 is an IGBT, the capacitor chip 16 is provided on the front surface of the IGBT by connecting the emitter electrode and the gate electrode.
That is, in the specification and claims of this application, “drain electrode” is a generic term for the anode side electrode of the semiconductor chip 12, and “source electrode” is a generic term for the cathode side electrode of the semiconductor chip 12. is there.

  The semiconductor chip 12 is made of a silicon carbide (SiC) semiconductor. A semiconductor chip made of SiC (for example, SiC-MOSFET, SiC-IGBT) is particularly effective because it has a higher breakdown voltage and can be switched at a higher frequency than a semiconductor chip made of silicon. Furthermore, if this embodiment is applied, the switching loss can be efficiently reduced without using the technique described in Patent Document 1, and the manufacturing cost can be reduced because a complicated manufacturing process is not required. .

  By forming the wiring member by a combination of the printed circuit board 14 and the conductive post 15, the power semiconductor module 10 having high reliability with respect to a heat cycle caused by repeated heat generation of the semiconductor chip 12 can be obtained. Also, the power semiconductor module 10 can be made thinner than when a bonding wire is used as the wiring member. In this embodiment, the conductive post 15 is particularly effective because it can be reliably connected even if the area of the electrode on the front surface of the semiconductor chip 12 is small. In addition, since the stress applied to the semiconductor chip 12 is smaller than that of the lead, the reliability is high, and the thickness of the bonding material can be reduced, which is advantageous for electric conduction and heat conduction. However, the wiring member is not limited to the combination of the printed circuit board 14 and the conductive post 15, and may be a bonding wire 18.

  In the printed board 14, the first region 14 b 1 and the second region 14 b 2 of the metal layer 14 b are arranged on the side of the insulating layer 14 a farther from the multilayer substrate 11. However, the present invention is not limited to the example shown in FIGS. 1 and 3, and the first region 14b1 and the second region 14b2 can be disposed on both surfaces of the insulating layer 14a.

  The metal layer 14b and the conductive post 15 of the printed board 14 are made of a metal having good conductivity, such as copper or aluminum. Further, the metal layer 14b and the conductive post 15 of the printed circuit board 14 can be plated with Ni or the like as necessary. The printed board 14 may be a rigid board whose insulating layer 14a is made of a glass epoxy material or the like, and may be a flexible board whose insulating layer 14a is made of a polyimide material or the like.

  The conductive post 15 can have a cylindrical shape or a rectangular parallelepiped shape, but is not particularly limited. The size of the bottom surface of the conductive post 15 is smaller than the electrodes on the front surfaces of the semiconductor chip 12 and the semiconductor chip 13. Furthermore, the number of conductive posts 15 installed on one semiconductor chip 12 or semiconductor chip 13 is arbitrary, and a plurality of conductive posts 15 can be bonded to one front surface electrode.

  In assembling the power semiconductor module 10, the printed circuit board 14 and the conductive post 15 can be an integrated assembly in advance. By using the wiring member of the integrated assembly, the manufacturing process of the power semiconductor module 10 can be simplified as compared with the bonding wire 18.

  The laminated substrate 11, semiconductor chips 12 and 13, the printed circuit board 14, and the conductive posts 15, which are members of the power semiconductor module 10, are sealed with a sealing material made of an insulating thermosetting resin (not shown). The external terminals (drain terminal 19A, source terminal 19B, gate terminal 19C) are arranged so as to protrude from the sealing material.

Next, the manufacturing method of one embodiment of the power semiconductor module 10 will be described.
First, a step of disposing the insulating resin 17 between the source electrode 12a and the gate electrode 12b which are front surface electrodes of the semiconductor chip 12 is performed. Specifically, as shown in FIG. 13, this step is to apply an insulating resin 17 that is a polyimide resin between the source electrode 12a and the gate electrode 12b.
Next, the capacitor chip 16 is disposed on the insulating resin 17, and one of the terminals of the capacitor chip 16 is joined to the source electrode 12a and the other to the gate electrode 12b by soldering. At this time, the conductive post 15 and the front surface electrode of the semiconductor chip 12 may be simultaneously joined with solder. By this step, the configuration shown in FIG. 5 can be realized.
The applied insulating resin 17 adheres to the side surface of the capacitor chip 16 and prevents one end and the other end of the capacitor chip 16 from being electrically connected by solder. The insulating resin 17 is not limited to a polyimide resin, and for example, an epoxy resin can be used. However, it is preferable to use a polyimide resin having high heat resistance.

Next, a manufacturing method of another embodiment of the power semiconductor module 10 will be described.
First, a plurality of conductive posts 15 are inserted into the through holes of the printed circuit board 14 to prepare an assembly in which the printed circuit board 14 and the plurality of conductive posts 15 are integrated.
Next, as shown in FIG. 14, the capacitor chip 16 is temporarily fixed to the second conductive post 15C in the assembly with a resin adhesive 21 or the like.
Next, the plurality of conductive posts 15 and the capacitor chip 16 are aligned and brought into contact with the semiconductor chip 12 while maintaining the temporarily fixed state. The capacitor chip 16 and the second conductive post 15C are simultaneously bonded to the gate electrode 12b by solder, and the capacitor chip 16 and the first conductive post 15A are simultaneously bonded to the source electrode 12a by solder. By simultaneously bonding the capacitor chip 16 and the second conductive post 15C, not only the second conductive post 15C but also the terminal of the capacitor chip 16 can be easily bonded to the small-area gate electrode 12b. Further, since the capacitor chip 16 can be aligned at the same time with the position of the conductive post 15 as a reference, the unique alignment of the capacitor chip 16 becomes unnecessary, and the manufacturing cost can be reduced. In this embodiment as well, as shown in FIG. 14, it is preferable to dispose an insulating resin 17 between the source electrode 12a and the gate electrode 12b which are front surface electrodes of the semiconductor chip 12.

Next, a manufacturing method of still another embodiment of the power semiconductor module 10 will be described.
First, a plurality of conductive posts 15 are inserted into the through holes of the printed circuit board 14 to prepare an assembly in which the printed circuit board 14 and the plurality of conductive posts 15 are integrated.
Next, as shown in FIGS. 15 and 16, the capacitor chip 16 is sandwiched between the first conductive posts 15A and the second conductive posts 15C in the assembly to temporarily fix them.
Next, the plurality of conductive posts 15 and the capacitor chip 16 are aligned and brought into contact with the semiconductor chip 12 while maintaining the temporarily fixed state. The capacitor chip 16 and the second conductive post 15C are simultaneously bonded to the gate electrode 12b by solder, and the capacitor chip 16 and the first conductive post 15A are simultaneously bonded to the source electrode 12a by solder. By sandwiching the capacitor chip 16 between the first conductive post 15 </ b> A and the second conductive post 15 </ b> C, the resin adhesive 21 becomes unnecessary, and thus the manufacturing cost can be reduced. Furthermore, since the capacitor chip 16 can be aligned at the same time with the position of the conductive post 15 as a reference, the unique alignment of the capacitor chip 16 becomes unnecessary, and the manufacturing cost can be reduced. Also in this embodiment, as shown in FIGS. 15 and 16, the insulating resin 17 may be disposed between the source electrode 12 a and the gate electrode 12 b which are the front surface electrodes of the semiconductor chip 12. preferable.

  Although the semiconductor device of the present invention has been specifically described with reference to the drawings and embodiments, the semiconductor device of the present invention is not limited to the description of the embodiments and drawings, and does not depart from the spirit of the present invention. Many variations in range are possible.

DESCRIPTION OF SYMBOLS 10 Power semiconductor module 11 Laminated substrate 12, 13 Semiconductor chip 12a Source electrode 12b Gate electrode 14 Printed circuit board 15 Conductive post 15A 1st conductive post 15C 2nd conductive post 16 Capacitor chip 17 Insulating resin 18 Bonding wire 19A Drain terminal 19B Source terminal 19C Gate terminal 20 Solder 21 Resin adhesive

Claims (6)

A semiconductor chip made of a SiC semiconductor and having a source electrode and a gate electrode on the front surface;
A capacitor chip provided on the front surface of the semiconductor chip and electrically connecting the source electrode and the gate electrode;
A semiconductor device comprising: In the front surface of the semiconductor chip, further comprising an insulating resin disposed between the source electrode and the gate electrode,
The semiconductor device according to claim 1, wherein the capacitor chip is disposed on the insulating resin. A printed circuit board provided to face the front surface of the semiconductor chip;
A first conductive post electrically connecting the source electrode of the semiconductor chip and the printed circuit board;
A second conductive post for electrically connecting the gate electrode of the semiconductor chip and the printed circuit board;
The semiconductor device according to claim 1, further comprising: Disposing an insulating resin between the source electrode and the gate electrode on the front surface of the semiconductor chip made of SiC semiconductor;
Disposing a capacitor chip on the insulating resin disposed on the front surface of the semiconductor chip and electrically connecting the source electrode and the gate electrode with the capacitor chip;
A method for manufacturing a semiconductor device comprising: Preparing an assembly composed of a printed circuit board and a plurality of conductive posts inserted into through holes of the printed circuit board;
Temporarily fixing a capacitor chip to at least one of the conductive posts of the assembly;
The ends of the plurality of conductive posts are connected to the source electrode and the gate electrode on the front surface of the semiconductor chip made of SiC semiconductor, and at the same time, the capacitor chip electrically connects the source electrode and the gate electrode. Connecting to
A method for manufacturing a semiconductor device comprising: A plurality of the conductive posts are composed of a first conductive post connected to the source electrode and a second conductive post connected to the gate electrode,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the capacitor chip is temporarily fixed by sandwiching the capacitor chip between the first conductive post and the second conductive post.

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