JP4142539B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP4142539B2
JP4142539B2 JP2003332847A JP2003332847A JP4142539B2 JP 4142539 B2 JP4142539 B2 JP 4142539B2 JP 2003332847 A JP2003332847 A JP 2003332847A JP 2003332847 A JP2003332847 A JP 2003332847A JP 4142539 B2 JP4142539 B2 JP 4142539B2
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wiring
power semiconductor
inductor
semiconductor chip
main electrode
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JP2005101256A (en
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勲 梅嵜
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Mitsubishi Electric Corp
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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Description

本発明は、半導体装置内部に搭載されている複数個のパワー半導体チップが互いに並列接続された電力用半導体装置に関する。例えば、本発明は、パワーモジュールに適用可能な技術を提供する。   The present invention relates to a power semiconductor device in which a plurality of power semiconductor chips mounted in a semiconductor device are connected in parallel to each other. For example, the present invention provides a technique applicable to a power module.

装置内に複数のパワー半導体チップを並列に配置した半導体装置においては、電流の導通時、及び、阻止時における複数の半導体チップの電位を揃えるために、出来る限り半導体チップの近傍で、陰極間、及び、陽極間を、ワイヤー配線で接続している。   In a semiconductor device in which a plurality of power semiconductor chips are arranged in parallel in the device, in order to align the potentials of the plurality of semiconductor chips at the time of current conduction and at the time of blocking, as close to the semiconductor chip as possible, between the cathodes, And the anodes are connected by wire wiring.

特開２００１−１８５６７９号公報JP 2001-185679 A 特開２００２−１４１４６５号公報JP 2002-141465 A 特開２００２−１５３０７９号公報JP 2002-153079 A 特開２０００−３１１９８３号公報JP 2000-311983 A 特開平９−２７０４９１号公報JP-A-9-270491

しかし、電流の通電、遮断を繰り返す半導体装置においては、通電や遮断時の急峻な電流変化の過程では、半導体チップの特性のバラツキ、配線のインピーダンスの差異に起因して、半導体チップ間に電位差が生じ、そのため、上述のワイヤー配線を通して、チップ間を比較的高周波の電流が流れる。又、急峻な電流変化に伴い半導体装置の内外に磁界が発生し、当該磁界が上述のワイヤー配線等にノイズとして乗ることで、同様に、高周波電流がこの配線に流れる。これらのパワー半導体チップ間配線に流れる高周波電流が過大な場合には、パワー半導体装置の誤動作や複数の半導体チップの不均一動作と言う様な悪影響が惹起され、半導体装置の安定動作の障害となる。   However, in a semiconductor device that repeatedly energizes and interrupts current, there is a potential difference between the semiconductor chips due to variations in characteristics of the semiconductor chips and differences in wiring impedance in the process of steep current changes during energization and interruption. Therefore, a relatively high-frequency current flows between the chips through the above-described wire wiring. In addition, a magnetic field is generated inside and outside the semiconductor device with a steep current change, and the magnetic field rides on the above-described wire wiring as noise, so that a high-frequency current similarly flows through the wiring. If the high-frequency current flowing through the wiring between these power semiconductor chips is excessive, adverse effects such as malfunction of the power semiconductor device and non-uniform operation of a plurality of semiconductor chips are caused, which hinders stable operation of the semiconductor device. .

この発明は、斯かる懸案事項を踏まえて創作されたものであり、装置内に複数のパワー半導体チップを搭載する電力用半導体装置において、複数個のパワー半導体チップの電位を合わせるための配線に発生する、高周波の電流を阻止ないしは抑制させる事で、当該半導体装置及びその周辺機器の安定動作を実現させることを、目的とする。   The present invention was created in view of such a matter of concern, and is generated in wiring for matching the potentials of a plurality of power semiconductor chips in a power semiconductor device in which a plurality of power semiconductor chips are mounted in the device. An object of the present invention is to realize stable operation of the semiconductor device and its peripheral devices by blocking or suppressing high-frequency current.

この発明の主題に係る電力用半導体装置は、互いに並列接続される第１及び第２パワー半導体チップと、前記第１パワー半導体チップの一方の主電極と、前記第１パワー半導体チップの前記一方の主電極と同電位にある前記第２パワー半導体チップの一方の主電極とを互いに接続する配線経路とを備え、前記配線経路は、その途中に、インダクター部材を含んでおり、前記インダクター部材は、ワイヤー配線、導電性板又は金属線材の何れかより成る導電性配線部材のインダクタンス値よりも大きなインダクタンス値を有するチップインダクター又はコイル部品から成るディスクリート部品であることを特徴とする。 A power semiconductor device according to a subject of the present invention includes first and second power semiconductor chips connected in parallel to each other, one main electrode of the first power semiconductor chip, and the one of the first power semiconductor chips. A wiring path that connects one main electrode of the second power semiconductor chip having the same potential as the main electrode to each other, and the wiring path includes an inductor member in the middle of the wiring path. It is a discrete component composed of a chip inductor or a coil component having an inductance value larger than the inductance value of a conductive wiring member made of any one of a wire wiring, a conductive plate and a metal wire .

以下、この発明の主題の様々な具体化を、添付図面を基に、その効果・利点と共に、詳述する。   Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

この発明の主題に係る電力用半導体装置によれば、１）半導体チップの動作時に半導体チップ間電位差に起因して半導体チップ間を流れる高周波電流を、インダクター部材による回路配線の高インピーダンス化によって抑制することが出来、これに伴い本半導体装置の安定動作の確保及び信頼性の向上を図ることが出来る。   According to the power semiconductor device according to the subject of the present invention, 1) high frequency current flowing between the semiconductor chips due to the potential difference between the semiconductor chips during the operation of the semiconductor chip is suppressed by increasing the impedance of the circuit wiring by the inductor member. As a result, stable operation of the semiconductor device can be ensured and reliability can be improved.

本発明の特徴点は、互いに並列接続された複数のパワー半導体チップの同電極間の配線に、アルミワイヤー等のワイヤー配線のインダクタンス値（それ自体無視し得る程の値である）よりも遥かに大きな（つまり、無視し得ない）インダクタンス値を有する、１）インダクター部材（例えばチップインダクターやコイル部品の様なディスクリート部品）を、若しくは、２）配線インダクター部（電気配線自体が有するインダクタンス）を、積極的に導入・配置する点にある。換言すれば、１）第１パワー半導体チップの一方の主電極と、当該第１パワー半導体チップの一方の主電極と同電位にある第２パワー半導体チップの一方の主電極とを互いに接続する配線経路中に含まれるインダクター部材は、当該インダクター部材を除く配線経路の他の部分のインダクタンス値よりも大きなインダクタンス値を有する、若しくは、２）配線経路は、その一部に、当該配線経路のその他の部分におけるインダクタンス値よりも大きなインダクタンス値を有する配線インダクター部を有する。この構成により、イ）電流導通時及び阻止時における電流変化の少ない状態においては、同電極間の配線は低インピーダンスのため、半導体チップ間の電位を容易に合わすことが出来る。ロ）その一方で、電流の通電及び遮断時などの電流変化が大きな状態においては、同電極間の配線が高インピーダンスとなるため、その際にチップ間を流れようとする高周波電流を遮断、あるいは低減することが可能となり、電力用半導体装置の動作の安定性を確保する事が出来る。以下、この様な特徴点を、実施の形態１及び２として、詳述する。   A feature of the present invention is that the wiring between the same electrodes of a plurality of power semiconductor chips connected in parallel to each other is far more than the inductance value of a wire wiring such as an aluminum wire (it is a value that can be ignored in itself). It has a large inductance value (that is, a non-negligible) inductance value, 1) an inductor member (for example, a discrete component such as a chip inductor or a coil component), or 2) a wiring inductor portion (an inductance that the electric wiring itself has) , Is to actively introduce and arrange. In other words, 1) wiring that connects one main electrode of the first power semiconductor chip and one main electrode of the second power semiconductor chip that is at the same potential as the one main electrode of the first power semiconductor chip. The inductor member included in the path has an inductance value larger than the inductance value of the other part of the wiring path excluding the inductor member, or 2) The wiring path includes a part of the other part of the wiring path. It has a wiring inductor part which has an inductance value larger than the inductance value in the part. With this configuration, a) In a state where there is little change in current during current conduction and blocking, the wiring between the electrodes has a low impedance, so that the potential between the semiconductor chips can be easily matched. B) On the other hand, when the current change is large, such as when the current is turned on and off, the wiring between the electrodes has a high impedance, so that the high-frequency current that flows between the chips at that time is cut off, or Therefore, the stability of the operation of the power semiconductor device can be ensured. Hereinafter, such feature points will be described in detail as Embodiments 1 and 2.

（実施の形態１）
図１及び図２は、各々、本実施の形態に係る電力用半導体装置の内部構成を模式的に示す上面図及び側面図である。又、図３は、本実施の形態に係る電力用半導体装置の内部構成の等価回路を示す図である。尚、図３の等価回路は、後述する実施の形態２に係る電力用半導体装置にも妥当する（符号１３Ａ及び１３Ｂがそれぞれ符号１４Ａ及び１４Ｂに置換わるだけである）。図１乃至図３に示される通り、本装置は、１）主基板ないしは母基板としての、金属ベース板（以下、単に基板と称す）１００と、２）当該基板１００の表面ないしは主面１００Ｓの左側中央領域上に配設された絶縁性のコレクタ基板（第１主電極用第１基板に該当）２Ａと、３）コレクタ基板２Ａの表面上に形成・配設されたコレクタ用配線パターン（第１主電極用第１配線パターンに該当）２ａと、４）コレクタ用配線パターン２ａの対応箇所に電気的に結合（例えば接着）された裏面側のコレクタ領域（図示せず：第１主電極に該当）と、表面側のエミッタ領域（図示せず：第２主電極に該当）と、表面側のゲート領域（図示せず：制御電極に該当）とを有するＩＧＢＴチップ（第１パワー半導体チップに該当：本例では、２個の第１パワー半導体チップが同一基板２Ａ上に搭載されている）１Ａと、５）基板表面１００Ｓの左側上方領域上に別個に搭載・配設された絶縁性のエミッタ基板（第２主電極用第２基板に該当）３Ａと、６）エミッタ基板３Ａの表面上に形成・配設されたエミッタ用配線パターン（第２主電極用第２配線パターンに該当）３ａと、７）基板表面１００Ｓの左側下方領域上に搭載・配設された絶縁性のゲート基板（制御電極用基板）４Ａと、８）ゲート基板４Ａの表面上に形成・配設されたゲート用配線パターン４ａとを、備えている。更に、本装置は、９）エミッタ基板３Ａの表面の他領域（基板端部近傍面）上に配設され且つエミッタ用配線パターン３ａと一体的に接続された突出状の第１インダクター部材用第１パッド部１３ＡＰ１と、１０）エミッタ基板３Ａの表面の右上コーナー近傍領域上に配設されており、従って、配線パターン３ａに直接的に接続されることなく（一体化されることなく）、第１パッド１３ＡＰ１部に対向配置された第１インダクター部材用第２パッド部１３ＡＰ２と、１１）ＩＧＢＴチップ１Ａのエミッタ領域と配線パターン３ａとを互いに電気的に接続する様にボンディングされた第１ワイヤー（例えばアルミワイヤーより成る）９Ａと、１２）第１パッド部１３ＡＰ１と第２パッド部１３ＡＰ２との間に半田付けにより配設された第１インダクター部材１３Ａとを、備えている。そして、コレクタ電極５、エミッタ電極６、制御エミッタ電極７及びゲート電極８が、それぞれ、図示される様に、形成されている。更に、本装置は、第１パワー半導体チップ１Ａと並列接続される第２パワー半導体チップ側の構成部材として、１３）基板表面１００Ｓの右側中央領域上に搭載・配設された絶縁性のコレクタ基板（第１主電極用第３基板に該当）２Ｂと、１４）コレクタ基板２Ｂの表面上に形成・配設されたコレクタ用配線パターン（第１主電極用第３配線パターンに該当）２ｂと、１５）コレクタ用配線パターン２ｂの対応箇所に電気的に結合（例えば接着）された裏面側のコレクタ領域（図示せず：第１主電極に該当）と、表面側のエミッタ領域（図示せず：第２主電極に該当）と、表面側のゲート領域（図示せず：制御電極に該当）とを有するＩＧＢＴチップ（第２パワー半導体チップに該当：本例では、２個の第２パワー半導体チップが同一基板２Ｂ上に搭載されている）１Ｂと、１６）基板表面１００Ｓの右側上方領域上に搭載・配設された絶縁性のエミッタ基板（第２主電極用第４基板に該当）３Ｂと、１７）エミッタ基板３Ｂの表面上に形成・配設されたエミッタ用配線パターン（第２主電極用第４配線パターンに相当）３ｂと、１８）基板表面１００Ｓの右側下方領域上に搭載・配設された絶縁性のゲート基板（制御電極用基板）４Ｂと、１９）ゲート基板４Ｂの表面上に形成・配設されたゲート用配線パターン４ｂとを、備えている。加えて、本装置は、２０）エミッタ基板３Ｂの表面（基板３Ａ側端部の表面）上に形成・配設され且つエミッタ用配線パターン３ｂと一体的に接続された突出状の第２インダクター部材用第３パッド部１３ＢＰ３と、２１）エミッタ基板３Ｂの左上コーナー近傍領域における表面上に配設されており、配線パターン３ｂには一体的に接続されることなく、第３パッド部１３ＢＰ３に対向した第２インダクター部材用第４パッド部１３ＢＰ４と、２２）ＩＧＢＴチップの１Ｂのエミッタ領域とエミッタ用配線パターン３ｂとを互いに接続する第２ワイヤー（例えばアルミワイヤーより成る）９Ｂと、２３）第３パッド部１３ＢＰ３と第４パッド部１３ＢＰ４との間に半田付けにより配設された第２インダクター部材１３Ｂとを、備えている。 (Embodiment 1)
1 and 2 are a top view and a side view, respectively, schematically showing the internal configuration of the power semiconductor device according to the present embodiment. FIG. 3 is a diagram showing an equivalent circuit of the internal configuration of the power semiconductor device according to the present embodiment. Note that the equivalent circuit of FIG. 3 is also applicable to a power semiconductor device according to the second embodiment to be described later (only reference numerals 13A and 13B are replaced with reference numerals 14A and 14B, respectively). As shown in FIG. 1 to FIG. 3, this apparatus has 1) a metal base plate (hereinafter simply referred to as a substrate) 100 as a main substrate or mother substrate, and 2) a surface of the substrate 100 or a main surface 100S. Insulating collector substrate (corresponding to the first substrate for the first main electrode) 2A disposed on the left central region, and 3) collector wiring pattern (first electrode) formed and disposed on the surface of the collector substrate 2A (Corresponding to the first main electrode first wiring pattern) 2a and 4) the collector region on the back side electrically coupled (for example, bonded) to the corresponding portion of the collector wiring pattern 2a (not shown: on the first main electrode) Corresponding), a front-side emitter region (not shown: corresponding to the second main electrode), and a front-side gate region (not shown: corresponding to the control electrode) (to the first power semiconductor chip). Applicable: In this example, two first 1A on which the semiconductor chip is mounted on the same substrate 2A) and 5) an insulating emitter substrate (second substrate for the second main electrode) separately mounted and disposed on the upper left region of the substrate surface 100S 3), 6) Emitter wiring pattern formed and disposed on the surface of the emitter substrate 3A (corresponding to the second main electrode second wiring pattern) 3a, and 7) Lower left region of the substrate surface 100S An insulating gate substrate (control electrode substrate) 4A mounted and disposed thereon and 8) a gate wiring pattern 4a formed and disposed on the surface of the gate substrate 4A are provided. Further, the present apparatus 9) is provided on the other surface of the emitter substrate 3A (surface near the end of the substrate) and is connected to the emitter wiring pattern 3a in an integrated manner for the projecting first inductor member. 1 pad portion 13AP1 and 10) are disposed on the upper right corner vicinity region of the surface of the emitter substrate 3A, and therefore are not directly connected (not integrated) to the wiring pattern 3a. 1st pad 13AP2 for 1st inductor member arranged facing 1 pad 13AP1 part, 11) The 1st wire bonded so that the emitter area | region and wiring pattern 3a of IGBT chip | tip 1A may be electrically connected mutually. 9A, which is made of, for example, aluminum wire, and 12) a first electrode disposed by soldering between the first pad portion 13AP1 and the second pad portion 13AP2. And Dakuta member 13A, and includes. A collector electrode 5, an emitter electrode 6, a control emitter electrode 7 and a gate electrode 8 are formed as shown in the figure. Furthermore, this apparatus is a component on the side of the second power semiconductor chip connected in parallel with the first power semiconductor chip 1A. 13) Insulating collector substrate mounted and disposed on the right central region of the substrate surface 100S (Corresponding to the first main electrode third substrate) 2B, 14) collector wiring pattern formed and arranged on the surface of the collector substrate 2B (corresponding to the first main electrode third wiring pattern) 2b, 15) A collector region (not shown: corresponding to the first main electrode) on the back side electrically coupled (for example, bonded) to a corresponding portion of the collector wiring pattern 2b, and an emitter region (not shown: not shown) IGBT chip (corresponding to the second power semiconductor chip: corresponding to the second power semiconductor chip in this example: two second power semiconductor chips) having a gate region (not shown: corresponding to the control electrode) on the surface side Is the same substrate 2 1B) 16) mounted on the right upper region of the substrate surface 100S, and an insulating emitter substrate (corresponding to the fourth substrate for the second main electrode) 3B, 17) emitter Emitter wiring pattern (corresponding to the second main electrode fourth wiring pattern) 3b formed and disposed on the surface of the substrate 3B and 18) Insulation mounted and disposed on the lower right region of the substrate surface 100S A conductive gate substrate (control electrode substrate) 4B, and 19) a gate wiring pattern 4b formed and disposed on the surface of the gate substrate 4B. In addition, this apparatus includes 20) a protruding second inductor member formed and disposed on the surface of the emitter substrate 3B (surface of the end portion on the substrate 3A side) and integrally connected to the emitter wiring pattern 3b. The third pad portion 13BP3 and 21) are arranged on the surface in the vicinity of the upper left corner of the emitter substrate 3B and face the third pad portion 13BP3 without being integrally connected to the wiring pattern 3b. 4th pad part 13BP4 for 2nd inductor members, 22) 2nd wire (it consists of aluminum wires) 9B which mutually connects 1B emitter area | region of IGBT chip | tip, and emitter wiring pattern 3b, 23) 3rd pad A second inductor member 13B disposed by soldering between the portion 13BP3 and the fourth pad portion 13BP4.

更に、本装置は、２４）ワイヤーボンディングによって形成された、第２パッド部１３ＡＰ２と第４パッド部１３ＢＰ４とを互いに接続する第３ワイヤー（例えばアルミワイヤーより成る）１１と、２５）同じくワイヤーボンディングによって形成された、第１配線パターン２ａと第３配線パターン２ｂとを互いに接続する第４ワイヤー（例えばアルミワイヤーより成る）１２とを備えている。ここで、第３ワイヤー１１は、互いに隣接する回路パターン１３ＡＰ２，１３ＢＰ４のそれぞれの隣接端側を接続している。この配線構成により、第３ワイヤー１１のワイヤー長さを最短な値にすることが出来る。同様に、第４ワイヤー１２も、互いに隣接する回路パターン２ａ，２ｂのそれぞれの隣接端側を接続しており、以って、第４ワイヤー１２のワイヤー長を最短化している。尚、参照符号１１及び１２の部材は、第３及び第４ワイヤー１１，１２の様にアルミワイヤーで構成されている必要性はなく、そのインダクタンス値がインダクター部材１３Ａ，１３Ｂのそれらと比較して無視し得る程の小さい値である導電性の板（金属板等）あるいは金属の線材であっても良い。その意味で、第３及び第４ワイヤー１１，１２や、それらに代わる接続配線部材の各々を、「導電性配線部材」と称呼する。要は、導電性配線部材のインダクタンス値＜＜インダクター部材１３Ａ，１３Ｂのインダクタンス値と言う関係が成立すれば良い。本装置においては、第１インダクター部材１３Ａの第１インダクタンス値と、第２インダクター部材１３Ｂの第２インダクタンス値とは共に、第１ワイヤー乃至第４ワイヤー９Ａ，９Ｂ，１１，１２の各々が有するインダクタンス値よりも、相対的に見て十分に大きい値である。即ち、高周波電流が並列接続された両ＩＧＢＴ１Ａ，１Ｂのエミッタ領域間ないしはエミッタ電極間を流れる際に、当該回路配線中のインダクタンス成分がその流れを妨げるバリアと成り得るだけの高インピーダンスを呈する様に、上記第１及び第２インダクタンス値が設定されている。   In addition, the present apparatus has 24) a third wire (formed of aluminum wire, for example) 11 that connects the second pad portion 13AP2 and the fourth pad portion 13BP4 to each other, and 25) is also formed by wire bonding. A formed fourth wire (for example, made of aluminum wire) 12 is provided for connecting the first wiring pattern 2a and the third wiring pattern 2b to each other. Here, the third wire 11 connects the adjacent end sides of the circuit patterns 13AP2 and 13BP4 adjacent to each other. With this wiring configuration, the wire length of the third wire 11 can be set to the shortest value. Similarly, the fourth wire 12 also connects adjacent end sides of the circuit patterns 2a and 2b adjacent to each other, thereby minimizing the wire length of the fourth wire 12. The members 11 and 12 need not be made of aluminum wires like the third and fourth wires 11 and 12, and the inductance values thereof are compared with those of the inductor members 13A and 13B. A conductive plate (such as a metal plate) or a metal wire having a negligible value may be used. In that sense, each of the third and fourth wires 11 and 12 and the connection wiring member that replaces them is referred to as a “conductive wiring member”. In short, it is sufficient if the relationship of the inductance value of the conductive wiring member << the inductance value of the inductor members 13A and 13B is established. In this apparatus, both the first inductance value of the first inductor member 13A and the second inductance value of the second inductor member 13B are the inductances of the first to fourth wires 9A, 9B, 11, and 12. The value is sufficiently larger than the value. That is, when high-frequency current flows between the emitter regions or emitter electrodes of both IGBTs 1A and 1B connected in parallel, the inductance component in the circuit wiring exhibits a high impedance that can serve as a barrier that prevents the flow. The first and second inductance values are set.

又、図１の構造においては（後述する図４でも同様）、第１配線パターン２ａと第３配線パターン２ｂとは、それらの中間位置から見て互いに中間対称となる様に隣接配置されており（線対称配置関係）、同じく、第２配線パターン３ａと第４配線パターン３ｂも、それらの中間位置から見て互いに中間対称となる様に隣接配置されている（線対称配置関係）。又、第１及び第２インダクター部材１３Ａ，１３Ｂの両インダクタンス値は、互いに同一値に設定されているのが好ましい。この様な好ましい構成例に設定する場合には、設計及び部材配置・配線が容易となり、装置のコスト低減化をもたらす。   In the structure of FIG. 1 (the same applies to FIG. 4 described later), the first wiring pattern 2a and the third wiring pattern 2b are arranged adjacent to each other so as to be intermediately symmetric when viewed from the intermediate position thereof. (Line symmetrical arrangement relationship) Similarly, the second wiring pattern 3a and the fourth wiring pattern 3b are also arranged adjacent to each other so as to be intermediately symmetric when viewed from their intermediate positions (line symmetric arrangement relation). Moreover, it is preferable that both inductance values of the first and second inductor members 13A and 13B are set to the same value. In the case of setting to such a preferable configuration example, design and member arrangement / wiring become easy, and the cost of the apparatus is reduced.

以上の通り、ＩＧＢＴチップ１Ａ，１Ｂからのエミッタ配線を接続したエミッタ基板３Ａ，３Ｂの配線パターン部に、別個のインダクター部材１３Ａ，１３Ｂを配置していると共に、この部位より、隣り合うエミッタ基板間を第３ワイヤー１１で接続している。   As described above, the separate inductor members 13A and 13B are arranged on the wiring pattern portion of the emitter substrates 3A and 3B to which the emitter wirings from the IGBT chips 1A and 1B are connected. Are connected by a third wire 11.

本構成により、高周波電流がエミッタ基板間に流れるときに、インダクター部材１３Ａ，１３Ｂが回路配線の高インピーダンス化をもたらすため、その結果、エミッタ基板間に流れる高周波電流が遮断ないしは抑制され、本装置の誤動作あるいはチップ間の不均一動作が抑制される。これにより、安定した動作が確保される。更に、本構成では、エミッタ用配線パターン３ａ，３ｂとは別個に同一基板３Ａ，３Ｂ上にインダクター部材１３Ａ，１３Ｂをそれぞれ配設しているので、高インピーダンス化のためのインダクター設計の自由度を高め得ると言う利点が得られる。即ち、第２主電極用配線パターンとは別個に同一基板上にインダクター部材を配設しているので、高インピーダンス化のためのインダクター設計の自由度を高め得る。   With this configuration, when high-frequency current flows between the emitter substrates, the inductor members 13A and 13B increase the impedance of the circuit wiring. As a result, the high-frequency current flowing between the emitter substrates is blocked or suppressed. Malfunction or non-uniform operation between chips is suppressed. Thereby, stable operation is ensured. Further, in this configuration, the inductor members 13A and 13B are disposed on the same substrate 3A and 3B separately from the emitter wiring patterns 3a and 3b, respectively, so that the degree of freedom in designing the inductor for high impedance can be increased. The advantage that it can be increased is obtained. That is, since the inductor member is disposed on the same substrate separately from the second main electrode wiring pattern, the degree of freedom in designing the inductor for achieving high impedance can be increased.

尚、突出した第１パッド部１３ＡＰ１を積極的に設けずに、第１パッド部１３ＡＰ１に相当する部分、つまり、第１インダクター部材１３Ａの一方の電極を半田付けするためのパターン部分を、第２配線パターン３ａの端部自身としても良い。即ち、第２配線パターン３ａの端部が、第１パッド部１３ＡＰ１に相当する部分として兼用されるのである。この様な変形は、第３パッド部１３ＢＰ３についても同様に適用可能である。これらの変形は、後述する変形例１にも妥当する。   In addition, without actively providing the protruding first pad portion 13AP1, a portion corresponding to the first pad portion 13AP1, that is, a pattern portion for soldering one electrode of the first inductor member 13A, The end of the wiring pattern 3a itself may be used. That is, the end portion of the second wiring pattern 3a is also used as a portion corresponding to the first pad portion 13AP1. Such a modification can be similarly applied to the third pad portion 13BP3. These modifications are also applicable to Modification 1 described later.

＜変形例１＞
図１の特徴的構成部に代えて、あるいは、図１の特徴的構成部に加えて、ＩＧＢＴチップが配置されたコレタタ基板の配線パターンに対して、実施の形態１のインダクター部材１３Ａ，１３Ｂに相当するものを同一基板上に別個に配置した上で、この部位より、隣り合うコレクタ基板の配線パターンを第４ワイヤーで接続することとしても良い。その様な変形例１の構成例を、図１に相当する図４に示す。又、そのときの等価回路を図５に示す。本変形例によれば、高周波電流がコレクタ基板間に流れるときに、インダクター部が高インピーダンスとなるため、コレクタ基板間に流れる高周波電流が遮断あるいは抑制され、本装置の誤動作やチップ間の不均一動作が抑制される事で、安定した動作が確保される。同様に、コレクタ基板間の回路配線に対しても、高インピーダンス化のためのインダクター設計の自由度を高め得ると言う利点が得られる。 <Modification 1>
In place of or in addition to the characteristic component in FIG. 1, the inductor members 13A and 13B according to the first embodiment are connected to the wiring pattern of the collector board on which the IGBT chip is arranged, in addition to the characteristic component in FIG. It is good also as connecting the wiring pattern of an adjacent collector board | substrate with a 4th wire from this part, after arrange | positioning a corresponding thing separately on the same board | substrate. A configuration example of such modification 1 is shown in FIG. 4 corresponding to FIG. FIG. 5 shows an equivalent circuit at that time. According to this modification, when the high-frequency current flows between the collector substrates, the inductor portion has a high impedance. Therefore, the high-frequency current flowing between the collector substrates is interrupted or suppressed. Stable operation is ensured by suppressing the operation. Similarly, the advantage that the degree of freedom in designing the inductor for increasing the impedance can be increased also for the circuit wiring between the collector substrates.

（実施の形態２）
本実施の形態においては、実施の形態１における様な別個に設けたインダクター部材の搭載に代えて、ＩＧＢＴチップからの工ミッタ配線を接続したエミッタ基板自体が、その配線パターン部の一部をくし型配線とすることで形成された配線インダクター部１４Ａ，１４Ｂを有する。この部位より、隣り合うエミッタ基板同士は、第３ワイヤー１１で接続される。 (Embodiment 2)
In the present embodiment, instead of mounting the separately provided inductor member as in the first embodiment, the emitter substrate itself connected to the processer wiring from the IGBT chip combs a part of the wiring pattern portion. It has wiring inductor parts 14A and 14B formed by using a mold wiring. From this part, adjacent emitter substrates are connected by a third wire 11.

本実施の形態の特徴部分のみを抽出して拡大的に描いた構成図が、図６の平面図である。図６に描かれていない部分は、図１中の対応部分と同一である。尚、このときの等価回路は、図３に示される通りである。図６に例示されている通り、本装置における第２主電極用第２配線パターン３ａは、エミッタ基板（第２基板）３Ａの表面上に配設されており、その端部が、他部とは相違した形状（ここでは、くし型構造）を有することにより、第１配線インダクター部１４Ａを形成しており、第１ワイヤー９Ａは、第１パワー半導体チップ１Ａの第２主電極（エミッタ）と第２配線パターン３ａの上記他部とを、互いに接続している。更に、本装置における第２主電極用第４配線パターン３ｂは、エミッタ基板（第４基板）３Ｂの表面上に配設されており、その端部が、他部とは相違した形状（ここでは、くし型構造）を有することにより、第２配線インダクター部１４Ｂを形成しており、第２ワイヤー９Ｂは、第２パワー半導体チップ１Ｂの第２主電極（エミッタ）と第４配線パターン３ｂの上記他部とを、互いに接続している。しかも、第３ワイヤー１１は、第１配線インダクター部１４Ａの端部１４ＡＥと第２配線インダクター部１４Ｂの端部１４ＢＥとを、互いに接続している。又、第４ワイヤー１２は、第１配線パターン２ａと第３配線パターン２ｂとを、互いに接続している。そして、第１配線インダクター部１４Ａの第１インダクタンス値と第２配線インダクター部１４Ｂの第２インダクタンス値とは、共に、第１ワイヤー乃至第４ワイヤー９Ａ，９Ｂ，１１，１２の各々のインダクタンス値よりも、相対的に見て十分に大きな値である。   FIG. 6 is a plan view showing an enlarged configuration drawing only the characteristic portions of the present embodiment. The parts not drawn in FIG. 6 are the same as the corresponding parts in FIG. The equivalent circuit at this time is as shown in FIG. As illustrated in FIG. 6, the second wiring pattern 3a for the second main electrode in the present apparatus is disposed on the surface of the emitter substrate (second substrate) 3A, and its end portion is connected to the other portion. Have a different shape (here, a comb structure) to form the first wiring inductor portion 14A, and the first wire 9A is different from the second main electrode (emitter) of the first power semiconductor chip 1A. The other parts of the second wiring pattern 3a are connected to each other. Further, the fourth wiring pattern 3b for the second main electrode in the present apparatus is disposed on the surface of the emitter substrate (fourth substrate) 3B, and its end portion has a shape (here, different from that of the other portion). The second wire 9B is formed of the second main electrode (emitter) of the second power semiconductor chip 1B and the fourth wiring pattern 3b. The other parts are connected to each other. Moreover, the third wire 11 connects the end portion 14AE of the first wiring inductor portion 14A and the end portion 14BE of the second wiring inductor portion 14B to each other. The fourth wire 12 connects the first wiring pattern 2a and the third wiring pattern 2b to each other. The first inductance value of the first wiring inductor portion 14A and the second inductance value of the second wiring inductor portion 14B are both based on the inductance values of the first to fourth wires 9A, 9B, 11, and 12, respectively. However, the value is relatively large when viewed relatively.

又、図６の構造においては（後述する図７でも同様）、第１配線パターン２ａと第３配線パターン２ｂとは、それらの中間位置から見て互いに中間対称となる様に隣接配置されており（線対称配置関係）、同じく、第２配線パターン３ａと第４配線パターン３ｂも、それらの中間位置から見て互いに中間対称となる様に隣接配置されている（線対称配置関係）。又、第１及び第２配線インダクター部１４Ａ，１４Ｂの両インダクタンス値は、互いに同一値に設定されているのが好ましい。この様な好ましい構成例に設定する場合には、設計及び部材配置・配線が容易となり、装置のコスト低減化をもたらす。   In the structure of FIG. 6 (the same applies to FIG. 7 to be described later), the first wiring pattern 2a and the third wiring pattern 2b are arranged adjacent to each other so as to be symmetrical with respect to each other when viewed from their intermediate positions. (Line symmetrical arrangement relationship) Similarly, the second wiring pattern 3a and the fourth wiring pattern 3b are also arranged adjacent to each other so as to be intermediately symmetric when viewed from their intermediate positions (line symmetric arrangement relation). Moreover, it is preferable that both inductance values of the first and second wiring inductor portions 14A and 14B are set to the same value. In the case of setting to such a preferable configuration example, design and member arrangement / wiring become easy, and the cost of the apparatus is reduced.

本実施の形態の動作原理は、基本的に、実施の形態１のそれと同一である。従って、本実施の形態の構成によれば、高周波電流がエミッタ基板間に流れる際に、配線インダクター部が高インピーダンス部となるため、エミッタ基板間に流れる高周波電流が遮断あるいは抑制され、本装置の誤動作やチップ間の不均一動作が抑制される。その結果、安定した動作が確保され得る。   The operation principle of the present embodiment is basically the same as that of the first embodiment. Therefore, according to the configuration of the present embodiment, when the high frequency current flows between the emitter substrates, the wiring inductor portion becomes a high impedance portion, so that the high frequency current flowing between the emitter substrates is cut off or suppressed. Malfunctions and uneven operation between chips are suppressed. As a result, stable operation can be ensured.

＜変形例２＞
実施の形態２に対しても、変形例１で記載したものと同様の修正を成すことが可能である。その様な変形例の核心部を図７に拡大して示す。図７に示す通り、ＩＧＢＴチップ１Ａ，１Ｂが配置されたコレタタ基板２Ａ，２Ｂの各配線パターン２ａ，２ｂの対向し合う端部には、例えば櫛型状の（各ワイヤーと比較して）高インダクタンス値を有する第１及び第２配線インダクター部１４Ａ，１４Ｂが、形成されている。そして、各配線インダクター部の端部１４ＡＥ，１４ＢＥは、互いに、第４ワイヤー１２で接続されている。従って、隣り合うコレクタ基板を結ぶ回路配線パターン自体が、高インダクタンスの配線インダクターを備えている状態が実現されている。 <Modification 2>
The second embodiment can be modified in the same manner as that described in the first modification. The core of such a modification is shown in an enlarged manner in FIG. As shown in FIG. 7, the opposing end portions of the wiring patterns 2a and 2b of the collector boards 2A and 2B on which the IGBT chips 1A and 1B are arranged are, for example, comb-shaped (compared to the wires). First and second wiring inductor portions 14A and 14B having inductance values are formed. The end portions 14AE and 14BE of each wiring inductor portion are connected to each other by the fourth wire 12. Therefore, the circuit wiring pattern itself that connects the adjacent collector substrates is provided with a high-inductance wiring inductor.

本変形例によっても、変形例１と同様に、高周波電流がコレクタ基板間に流れるときに、インダクター部が高インピーダンスとなるため、コレクタ基板間に流れる高周波電流が遮断あるいは抑制され、本装置の誤動作やチップ間の不均一動作が抑制される事で、安定した動作が確保される。   Also in this modification, as in Modification 1, when the high-frequency current flows between the collector substrates, the inductor portion has a high impedance, so that the high-frequency current flowing between the collector substrates is interrupted or suppressed, and this apparatus malfunctions. In addition, stable operation is ensured by suppressing uneven operation between chips.

以上の通り、本実施の形態及びその変形例によれば、１）実施の形態１と同様に、半導体チップの動作時に半導体チップ間電位差に起因して半導体チップ間を流れる高周波電流を、配線インダクター部の存在による回路配線の高インピーダンス化によって抑制することが出来、これに伴い本半導体装置の安定動作の確保及び信頼性の向上を図ることが出来ると共に、２）主回路パターンの一部を、即ち、各パワー半導体チップのエミッタ電極用配線パターン及び／又はコレクタ電極用配線パターンの一部を配線インダクター部として用いているので、主回路パターンとは別体のインダクター部の配設が不要となり、組立上の生産性に優れた安価なパワー半導体装置を提供することも出来ると言う効果がある。   As described above, according to the present embodiment and the modification thereof, as in the first embodiment, the high frequency current flowing between the semiconductor chips due to the potential difference between the semiconductor chips during the operation of the semiconductor chip is converted into the wiring inductor. It can be suppressed by increasing the impedance of the circuit wiring due to the presence of the portion, and accordingly, it is possible to ensure the stable operation and improve the reliability of the semiconductor device, and 2) a part of the main circuit pattern, That is, since a part of the wiring pattern for the emitter electrode and / or the wiring pattern for the collector electrode of each power semiconductor chip is used as the wiring inductor part, it is not necessary to arrange an inductor part separate from the main circuit pattern. There is an effect that it is possible to provide an inexpensive power semiconductor device excellent in productivity in assembly.

（付記）
以上、本発明の実施の形態を詳細に開示し記述したが、以上の記述は本発明の適用可能な局面を例示したものであって、本発明はこれに限定されるものではない。即ち、記述した局面に対する様々な修正や変形例を、この発明の範囲から逸脱することの無い範囲内で考えることが可能である。例えば、本発明における「パワー半導体チップ」とは、ＩＧＢＴ以外のパワートランジスタ（縦型ＭＯＳＦＥＴ等）や、サイリスタや、あるいは、ダイオード（この場合、特にリカバリー動作時に本発明は効を奏する）を包含し得る概念である。これらの場合、複数の、ダイオード、あるいはトランジスタ、あるいはサイリスタなどのパワー半導体チップを並列に配置する半導体装置において、各半導体チップの陽極基板に、及び／又は、陰極基板に、実施の形態１及び／又は実施の形態２で記載した様な中核的構成部材を施し、同電極基板間をワイヤーで接続する。又、パワー半導体チップの陽極を「第１主電極」と称するならば、その陰極が「第２主電極」に該当し、逆に、陰極を「第１主電極」と称するならば、陽極が「第２主電極」に該当する。又、第１基板２Ａと第３基板２Ｂとを一体化して、第１配線パターン２ａと第３配線パターン２ｂとを一体化しても良い。この変形を図４に適用する場合には、ワイヤー１２に代えて、配線パターンが直接に両インダクター部材１３Ａ、１３Ｂの対応電極を電気的に接続することになる。しかも、両インダクター部材１３Ａ、１３Ｂを１個のインダクター部材に置き換えても良く成る。つまり、インダクター部材の数はすくなくとも１個である。又、第２基板３Ａと第４基板３Ｂとを一体化して、第２配線パターン３ａと第４配線パターン３ｂとを一体化しても良い。この様な変形を図１に適用する場合には、ワイヤー１１に代えて、配線パターンが直接に両インダクター部材１３Ａ、１３Ｂの対応電極を電気的に接続することになる。この変形においても、同様に、両インダクター部材１３Ａ、１３Ｂを１個のインダクター部材に置き換えても良く成る。即ち、インダクター部材の個数は１個以上となる。 (Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention. For example, the “power semiconductor chip” in the present invention includes a power transistor (vertical MOSFET or the like) other than an IGBT, a thyristor, or a diode (in this case, the present invention is particularly effective during a recovery operation). It is a concept to get. In these cases, in a semiconductor device in which a plurality of power semiconductor chips such as diodes, transistors, or thyristors are arranged in parallel, the first embodiment and / or the anode substrate and / or the cathode substrate of each semiconductor chip. Alternatively, a core constituent member as described in the second embodiment is applied, and the electrode substrates are connected by a wire. If the anode of the power semiconductor chip is referred to as a “first main electrode”, the cathode corresponds to the “second main electrode”. Conversely, if the cathode is referred to as the “first main electrode”, the anode Corresponds to “second main electrode”. Alternatively, the first substrate 2A and the third substrate 2B may be integrated, and the first wiring pattern 2a and the third wiring pattern 2b may be integrated. When this modification is applied to FIG. 4, instead of the wire 12, the wiring pattern directly connects the corresponding electrodes of both the inductor members 13 </ b> A and 13 </ b> B. In addition, both inductor members 13A and 13B may be replaced with one inductor member. That is, the number of inductor members is at least one. Alternatively, the second substrate 3A and the fourth substrate 3B may be integrated, and the second wiring pattern 3a and the fourth wiring pattern 3b may be integrated. When such a modification is applied to FIG. 1, instead of the wire 11, the wiring pattern directly connects the corresponding electrodes of both the inductor members 13 </ b> A and 13 </ b> B. In this modification, similarly, both inductor members 13A and 13B may be replaced with one inductor member. That is, the number of inductor members is one or more.

本発明の実施の形態１に係る電力用半導体装置の内部構成を模式的に示す上面図である。It is a top view which shows typically the internal structure of the power semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る電力用半導体装置の内部構成を模式的に示す側面図である。It is a side view which shows typically the internal structure of the semiconductor device for electric power which concerns on Embodiment 1 of this invention. 本発明の各実施の形態に係る電力用半導体装置の内部構成の等価回路を示す図である。It is a figure which shows the equivalent circuit of the internal structure of the power semiconductor device which concerns on each embodiment of this invention. 本発明の実施の形態１の変形例に係る電力用半導体装置の内部構成を模式的に示す上面図である。It is a top view which shows typically the internal structure of the power semiconductor device which concerns on the modification of Embodiment 1 of this invention. 本発明の各変形例に係る電力用半導体装置の内部構成の等価回路を示す図である。It is a figure which shows the equivalent circuit of the internal structure of the semiconductor device for electric power which concerns on each modification of this invention. 本発明の実施の形態２に係る電力用半導体装置におけるエミッタ基板上配線パターンの構成を模式的に示す上面図である。It is a top view which shows typically the structure of the wiring pattern on an emitter substrate in the power semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２の変形例に係る電力用半導体装置におけるコレクタ基板上配線パターンの構成を模式的に示す上面図である。It is a top view which shows typically the structure of the wiring pattern on a collector substrate in the power semiconductor device which concerns on the modification of Embodiment 2 of this invention.

符号の説明Explanation of symbols

１Ａ，１Ｂ 電力用半導体装置内のＩＧＢＴチップ（半導体チップ）、２Ａ，２Ｂ コレクタ基板、２a，２b コレクタ用配線パターン、３Ａ，３Ｂ エミッタ基板、３a，３b エミッタ用配線パターン、４Ａ，４Ｂ ゲート基板、４a，４b ゲート用配線パターン、５ コレクタ電極、６ エミッタ電極、７ 制御エミッタ電極、８ ゲート電極、９Ａ，９Ｂ 第１エミッタ配線（ワイヤ配線）、１０Ａ，１０Ｂ ゲート配線（ワイヤ配線）、１１ 第２エミッタ配線（ワイヤ配線）、１２ コレクタ配線（ワイヤ配線）、１３Ａ，１３Ｂ インダクター部材、１４Ａ，１４Ｂ 配線インダクター部。
1A, 1B IGBT chip (semiconductor chip) in power semiconductor device, 2A, 2B collector substrate, 2a, 2b collector wiring pattern, 3A, 3B emitter substrate, 3a, 3b emitter wiring pattern, 4A, 4B gate substrate, 4a, 4b Gate wiring pattern, 5 Collector electrode, 6 Emitter electrode, 7 Control emitter electrode, 8 Gate electrode, 9A, 9B First emitter wiring (wire wiring), 10A, 10B Gate wiring (wire wiring), 11 2nd Emitter wiring (wire wiring), 12 collector wiring (wire wiring), 13A, 13B inductor member, 14A, 14B wiring inductor part.

Claims (7)

互いに並列接続される第１及び第２パワー半導体チップと、
前記第１パワー半導体チップの一方の主電極と、前記第１パワー半導体チップの前記一方の主電極と同電位にある前記第２パワー半導体チップの一方の主電極とを互いに接続する配線経路とを備え、
前記配線経路は、その途中に、インダクター部材を含んでおり、
前記インダクター部材は、ワイヤー配線、導電性板又は金属線材の何れかより成る導電性配線部材のインダクタンス値よりも大きなインダクタンス値を有するチップインダクター又はコイル部品から成るディスクリート部品であることを特徴とする、
電力用半導体装置。 First and second power semiconductor chips connected in parallel to each other;
A wiring path connecting the one main electrode of the first power semiconductor chip and the one main electrode of the second power semiconductor chip having the same potential as the one main electrode of the first power semiconductor chip; Prepared,
The wiring path includes an inductor member in the middle thereof,
The inductor member is a discrete component composed of a chip inductor or a coil component having an inductance value larger than that of a conductive wiring member made of any one of a wire wiring, a conductive plate, and a metal wire. ,
Power semiconductor device. 請求項１記載の電力用半導体装置であって、
前記第１パワー半導体チップの他方の主電極と、前記第１パワー半導体チップの前記他方の主電極と同電位にある前記第２パワー半導体チップの他方の主電極とを互いに接続する他方の配線経路とを備え、
前記他方の配線経路は、その途中に、前記他方の配線経路自体のインダクタンス値よりも大きなインダクタンス値を有するチップインダクター又はコイル部品から成る個別部品としてのインダクター部材を含むことを特徴とする、
電力用半導体装置。 The power semiconductor device according to claim 1,
The other wiring path that connects the other main electrode of the first power semiconductor chip and the other main electrode of the second power semiconductor chip having the same potential as the other main electrode of the first power semiconductor chip. And
The other wiring path includes an inductor member as an individual part including a chip inductor or a coil part having an inductance value larger than the inductance value of the other wiring path itself,
Power semiconductor device. 請求項１記載の電力用半導体装置であって、
前記配線経路は、そのインダクタンス値が前記インダクター部材のそれと比較して無視し得る程の小さい値である前記導電性配線部材を介して互いに接続された、第１パワー半導体チップ用第１インダクター部材及び第２パワー半導体チップ用第２インダクター部材を、前記インダクター部材として有しており、
しかも、前記導電性配線部材は、互いに隣接する第１インダクター部材用回路パターン及び第２インダクター部材用回路パターンの互いの隣接端側を接続していることを特徴とする、
電力用半導体装置。 The power semiconductor device according to claim 1,
The wiring path, the inductance value is connected to each other via the conductive wire member is small value negligibly compared to that of the inductor member, the first inductor member and a first power semiconductor chip Having a second inductor member for a second power semiconductor chip as the inductor member;
In addition, the conductive wiring member is connected to the adjacent end sides of the first inductor member circuit pattern and the second inductor member circuit pattern adjacent to each other,
Power semiconductor device. 請求項３記載の電力用半導体装置であって、
前記第１パワー半導体チップの前記一方の主電極から前記第１インダクター部材用回路パターンまでの配線経路と、前記第２パワー半導体チップの前記一方の主電極から前記第２インダクター部材用回路パターンまでの配線経路とは、互いに線対称な配置関係に設定されており、
前記第１インダクター部材のインダクタンス値及び前記第２インダクター部材のインダクタンス値とは互いに等しいことを特徴とする、
電力用半導体装置。 A power semiconductor device according to claim 3,
A wiring path from the one main electrode of the first power semiconductor chip to the circuit pattern for the first inductor member, and from the one main electrode of the second power semiconductor chip to the circuit pattern for the second inductor member The wiring route is set in a line-symmetric arrangement relationship with each other,
The inductance value of the first inductor member and the inductance value of the second inductor member are equal to each other,
Power semiconductor device. 互いに並列接続される第１及び第２パワー半導体チップと、
前記第１パワー半導体チップの一方の主電極と、前記第１パワー半導体チップの前記一方の主電極と同電位にある前記第２パワー半導体チップの一方の主電極とを互いに接続する配線経路とを備え、
前記配線経路は、その一部分として、前記配線経路のその他の部分におけるインダクタンス値及びワイヤー配線のインダクタンス値よりも大きなインダクタンス値を有し且つ前記配線経路の前記その他の部分とは相違した配線形状より成る配線インダクター部を有することを特徴とする、
電力用半導体装置。 First and second power semiconductor chips connected in parallel to each other;
A wiring path connecting the one main electrode of the first power semiconductor chip and the one main electrode of the second power semiconductor chip having the same potential as the one main electrode of the first power semiconductor chip; Prepared,
The wiring path, as a part component, wiring shape different from the inductance value and the other portions of and the wiring path than the inductance value have a large inductance value of the wire wiring in other parts of the wiring path It has a wiring inductor part consisting of ,
Power semiconductor device. 請求項５記載の電力用半導体装置であって、
前記第１パワー半導体チップの他方の主電極と、前記第１パワー半導体チップの前記他方の主電極と同電位にある前記第２パワー半導体チップの他方の主電極とを互いに接続する他方の配線経路とを備え、
前記他方の配線経路は、その一部分として、前記他方の配線経路のその他の部分におけるインダクタンス値及びワイヤー配線のインダクタンス値よりも大きなインダクタンス値を有し且つ前記他方の配線経路の前記その他の部分とは相違した配線形状より成る配線インダクター部を有することを特徴とする、
電力用半導体装置。 The power semiconductor device according to claim 5,
The other wiring path that connects the other main electrode of the first power semiconductor chip and the other main electrode of the second power semiconductor chip having the same potential as the other main electrode of the first power semiconductor chip. And
The other wiring path, as a part component, the other portion of the other of the inductance value in the other portions of the wiring path and than the inductance value of the wire wiring have a large inductance value and the other wiring path It has a wiring inductor part made of a wiring shape different from ,
Power semiconductor device. 請求項５記載の電力用半導体装置であって、
前記配線経路は、そのインダクタンス値が前記配線インダクター部のそれと比較して無視し得る程の小さい値である導電性配線部材を介して互いに接続された、第１パワー半導体チップ用第１配線インダクター部及び第２パワー半導体チップ用第２配線インダクター部を、前記配線インダクター部として有しており、
前記第１パワー半導体チップの前記一方の主電極から前記第１配線インダクター部と前記導電性配線部材の一端との接続部までの配線経路と、前記第２パワー半導体チップの前記一方の主電極から前記第２配線インダクター部と前記導電性配線部材の他端との接続部までの配線経路とは、互いに線対称な配置関係に設定されており、
前記第１配線インダクター部のインダクタンス値及び前記第２配線インダクター部のインダクタンス値とは互いに等しいことを特徴とする、
電力用半導体装置。 The power semiconductor device according to claim 5,
The first wiring inductor portions for the first power semiconductor chip, wherein the wiring paths are connected to each other via conductive wiring members whose inductance value is negligibly small compared with that of the wiring inductor portion. And a second wiring inductor part for the second power semiconductor chip as the wiring inductor part,
A wiring path from the one main electrode of the first power semiconductor chip to a connection portion between the first wiring inductor section and one end of the conductive wiring member; and from the one main electrode of the second power semiconductor chip The wiring path to the connection portion between the second wiring inductor portion and the other end of the conductive wiring member is set in a line-symmetric arrangement relationship with each other,
The inductance value of the first wiring inductor part and the inductance value of the second wiring inductor part are equal to each other,
Power semiconductor device.
JP2003332847A 2003-09-25 2003-09-25 Power semiconductor device Expired - Lifetime JP4142539B2 (en)

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US8531013B2 (en) 2010-06-11 2013-09-10 Casio Computer Co., Ltd. Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires
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KR101186744B1 (en) 2011-01-03 2012-09-28 주식회사 케이이씨 Substrate and power module having the same
JP6838243B2 (en) * 2017-09-29 2021-03-03 日立Astemo株式会社 Power converter
CN111801795A (en) * 2018-09-14 2020-10-20 富士电机株式会社 Semiconductor device with a plurality of semiconductor chips

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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