JPH07235542A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen the contact resistance between a polycrystalline silicon film and a tungsten film and to shorten the delay time of a semiconductor device by a method wherein a gate electrode is formed and a multilayer film, which consists of the polycrystalline silicon film, a silicon nitride film, in which the surface density of nitrogen is less than a specified value, and the tungsten film, is used for the formation of the gate electrode. CONSTITUTION:A silicon oxide film 2 and a conductive impurity-doped polycrystalline silicon film 3 are formed on a silicon substrate 1. Moreover, a tungsten nitride film 4 and a tungsten film 5 are formed. When heat treatment is conducted, nitrogen is redistributed in the film 3 from the film 4 and a high- concentration nitrogen-containing silicon film 6 is formed. The surface density of nitrogen in this film 6 is less than 8X10<14>cm<-2> and the contact resistance between the films 3 and 5 is reduced to less than 100OMEGAcm<2>. Accordingly, the delay time of a semiconductor device can be significantly improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to improvements in electrodes or wirings in the semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Large-scale integrated circuits (LSIs) formed by connecting a large number of transistors, resistors, etc. to an electric circuit in important parts of a computer, communication equipment, etc. ) Is often used. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone. The performance improvement of a single LSI can be realized by increasing the degree of integration, that is, by miniaturizing the element.

However, with the recent higher integration and higher speed of semiconductor integrated circuits due to the miniaturization of elements, the RC delay of electrodes such as gate electrodes and wirings such as gate wirings limits the operating speed of the elements. The problem has become apparent.

The problem of RC delay can be solved by increasing the thickness and reducing the low resistance without changing the electrode material, but the problem remains in terms of processing. For example, in the case of a gate electrode, it is desirable not to greatly exceed gate length: gate height = 1: 1.

As a method of reducing the gate resistance without changing the thickness of the gate electrode, a laminated film of a polycrystalline silicon film and a refractory metal silicide film can be used as the gate electrode. According to this method, the threshold voltage control method in the conventional polycrystalline silicon gate technology can be followed, and the refractory metal silicide film generally has high heat resistance and is compatible with the conventional polycrystalline silicon gate process. Is also high.

However, when considering a fine MOSFET having a gate length of 0.3 μm or less, for example, the refractory metal silicide film has a thickness of 100 to 200 n.
The sheet resistance is limited to the level of m, and only a sheet resistance of several tens Ω / port can be achieved.

In such a fine MOSFET,
In order to realize a sheet resistance of about several Ω / port at 100 nm, a metal film made of a refractory metal such as tungsten or molybdenum having a lower resistance than the refractory metal silicide film and having a certain degree of heat resistance, and a polycrystalline film. The use of a laminated film with a silicon film for the gate electrode is being studied.

However, even if tungsten, which is relatively hard to react with silicon, is used as the refractory metal, the tungsten easily reacts with silicon at a temperature of about 800 ° C. to form tungsten silicide, resulting in a resistance. There is a problem of rising.

As a method of preventing such a reaction, it has been considered to insert a reaction preventive film at the interface between the polycrystalline silicon film and the refractory metal film. It is disclosed in Japanese Patent Laid-Open Publication No. Sho 60-195975 that silicon nitride is effective as a material for preventing the reaction. According to this patent publication, in order to prevent the reaction between the polycrystalline silicon film and the molybdenum film and to pass the tunnel current between these films, the thickness of the silicon nitride film should be in the range of about 1 to 5 nm. Is said to be desirable.

However, when the silicon nitride film is used as the reaction preventing film, the polycrystalline silicon film comes into contact with the refractory metal film through the silicon nitride film which is an insulating film, so that the contact resistance increases and the element A new problem arises in that the delay of is increased. This will be described in more detail below.

The delay in the gate section is affected by the gate capacitance C _OX between the silicon substrate 91 and the tungsten film 95 and the contact resistance R _C , as shown in FIG. The equivalent circuit is shown in FIG.
It becomes like (b). In the figure, 92 is a gate oxide film, and 93
Indicates a polycrystalline silicon film, and 94 indicates a silicon nitride film. Although the influence of the sheet resistance is neglected here to simplify the discussion, RC due to the contact resistance R _C
Sufficient to estimate the delay contribution.

As can be seen from FIG. 11B, the contact resistance R _C is combined with the gate capacitance C _OX and causes RC delay. The time constant of this RC delay is represented by the product of the gate capacitance C _OX and the contact resistance R _C. Since the contact resistance R _C is inversely proportional to the area and the gate capacitance C _OX is proportional to the area, the product thereof has a value that does not depend on the shape of the gate portion.

Assuming that the thickness of the gate oxide film 92 is 7 nm, the gate capacitance C _ox will be 4.9 × 10 ^-15 F / μm ² . When the contact resistance R _C is about 1 × 10 ³ Ωμm ² , the time constant of RC delay is about 4.9 × 10 ^-12 sec. That is, it has a time constant of about 5 psec.

Although the above description of the delay considers only the coupling of the contact resistance R _C and the gate capacitance C _OX as the delay factor, in reality, in addition to these delay components, the sheet resistance and the gate capacitance C are actually taken into consideration. There is a delay component due to binding with _OX .

FIG. 12 is a diagram for explaining the delay in consideration of the sheet resistance, and FIG. 12A shows the contact resistance R _C , the gate capacitance C _OX , and the polycrystalline silicon film 93 existing in the gate portion. The resistance R _poly and the resistance R _W of the tungsten film 95 are shown. The equivalent circuit of the gate portion in this case is
The lumped constant circuit has a plurality of stages (here, five stages) as shown in FIG. The gate capacitance C _OX is fixed to the value in the storage state. The element size is the channel length /
The channel width is 0.25 / 20 (μm). This is a realistic size for a MOSFET used in a logic LSI.

Here, 0.01 pse is applied to one end of the gate.
A pulse-shaped input voltage V that has a sufficiently fast rise time of c
_The delay time is defined as the time until the output voltage V _out appearing at the other end (polycrystalline silicon film 93) reaches 90% of the input voltage V _{in when in} (= 1 V) is applied.

The present inventors examined the relationship between the contact resistance R _C and the delay time in the above equivalent circuit, and obtained the following results. That is, as shown in FIG. 13, when the value of the contact resistance R _C exceeds 100 Ωμm ² , the delay time starts to increase rapidly, and when the value of the contact resistance R _C is 1 KΩμm ² , the delay time is 14 psec.
Reach

In the inverter using the fine MOSFET as described above, the switching time per inverter is 30 psec in an ideal case in which the above parasitic resistance and parasitic capacitance of the MOSFET are ignored.
It is considered to be below. Therefore, for such a short switching time, the delay time of 14 psec is no longer acceptable.

Further, when considering a next-generation MOSFET of sub-half micron or less, the switching time per logic gate stage is about several tens of psec, and RC
The value allowed as the delay must be considered to be about several psec at most.

By the way, as the reaction preventive film inserted between the polycrystalline silicon film and the tungsten film, there is a titanium nitride film in addition to the above-mentioned silicon nitride film. However, the titanium nitride film as the reaction preventing film has two major problems as described below.

First, since the titanium nitride film is very easily oxidized, there is a problem of abnormal oxidation. This problem will be described with reference to the process sectional view of FIG. In the figure, 101 indicates a silicon substrate, and FIG. 14A shows a gate electrode composed of a polycrystalline silicon film 103, a titanium nitride film 104 and a tungsten film 105 on a silicon substrate 101 with a gate oxide film 102 interposed therebetween. Shows the completed state. Thereafter, if the silicon is selectively oxidized to increase the thickness of the oxide film at the gate end, the titanium nitride film 104a is abnormally oxidized into particles as shown in FIG. 14B. Secondly, there is a problem that the crystal grain of the titanium nitride film formed on the polycrystalline silicon film is small and the specific resistance of the W film formed on the titanium nitride film becomes high.

[0022]

As described above, the conventional M
As the miniaturization of the OSFET progresses, there is a problem that the delay time due to the contact resistance becomes longer than the switch time, which hinders high-speed operation.

Further, when the laminated film of the polycrystalline silicon film, the titanium nitride film as the reaction preventing film, and the tungsten film is oxidized, the titanium nitride film is abnormally oxidized or the specific resistance of the tungsten film is increased. There was a problem.

The present invention has been made in consideration of the above circumstances, and a first object of the present invention is to provide a semiconductor device capable of shortening the delay time caused by contact resistance and a method of manufacturing the same. .

A second object of the present invention is to provide an electrode composed of a laminated film of a first conductive film containing a silicon film and nitrogen and a second conductive film, which does not cause abnormal oxidation even when subjected to oxidation. It is to provide a semiconductor device having (wiring) and a manufacturing method thereof.

[0026]

In order to achieve the first object, a semiconductor device of the present invention (claim 1) includes a silicon film, and a nitrogen film and a silicon film formed on the silicon film. A film having a nitrogen surface density of less than 8 × 10 ¹⁴ cm ⁻² and a refractory metal film formed on the film are laminated, and at least one of an electrode and a wiring is provided.

Another semiconductor device of the present invention (claim 2) is a silicon film and a silicon film formed on the silicon film.
It contains nitrogen and silicon, and the surface density of the nitrogen is 8 × 10.
Electrode and wiring formed by laminating a film having a thickness of less than ¹⁴ cm ^−2, a film formed on the film and containing a refractory metal and nitrogen, and a film formed on the film and made of the refractory metal. Of at least one of the above.

A method of manufacturing a semiconductor device according to the present invention (claim 3) is a step of forming a film containing a metal and nitrogen on a silicon film, wherein the metal is a nitride of the metal. A film containing the metal and nitrogen, wherein the value obtained by subtracting the reduction value of the Gibbs free energy generated when forming the nitride from silicon from the reduction value of the Gibbs free energy generated during formation is negative. And a heat treatment to form a film containing nitrogen and silicon at the interface between the metal film and the silicon film. And a step of forming at least one of an electrode and a wiring including a laminated film of the film containing nitrogen and silicon and the metal film.

Here, the metal is preferably a high melting point metal. Further, it is preferable that the film containing nitrogen and silicon has an area density of nitrogen of less than 8 × 10 ¹⁴ cm ^-2 .

Here, the metal is a refractory metal (for example,
W, Mo) is also included. Further, the surface density of nitrogen is the number of nitrogen per unit area when viewed from above the film, and this can be obtained by using, for example, X-ray photoelectron spectroscopy.

There is no problem if the film containing nitrogen and silicon contains some atmospheric components such as oxygen. For example, in the case of oxygen, about 20% may be contained in the film. The refractory metal is preferably one that does not chemically react with the film at the interface. For example, Mo, W, Nb, Ta and Cu are preferable. Further, a metal film containing Cu or Ag as a main component may be provided on such a refractory metal film that does not chemically react.

The film containing nitrogen and silicon is not limited to the method by redistribution from the film containing refractory metal and nitrogen, but is not limited to N.
Nitriding in an H ₃ atmosphere, plasma nitriding in a gas containing nitrogen, or the like may be used.

In order to achieve the above second object,
A semiconductor device of the present invention (claim 4) is formed on a silicon film, a first conductive film formed on the silicon film and containing nitrogen, silicon, and a refractory metal, and formed on the first conductive film. At least one of an electrode and a wiring formed by stacking the formed second conductive film is laminated.

Here, it is preferable that the first conductive film is an amorphous conductive film. Also,
A method of manufacturing a semiconductor device according to the present invention (claim 6) includes a step of forming a first conductive film containing nitrogen and a refractory metal on a silicon film, and a second conductive film on the first conductive film. By the step of forming a film and the heat treatment, part or all of the first conductive film is changed to a third conductive film containing nitrogen, silicon, and the refractory metal, and the silicon film and the first conductive film are formed. And a step of forming at least one of an electrode and a wiring including a laminated film of the conductive film and the third conductive film.

[0035]

According to the research conducted by the present inventors, the contact resistance between the silicon film and the refractory metal film is used when the laminated electrode of the silicon film / the film containing nitrogen and silicon / the refractory metal film is used. It has been found that the delay time is drastically shortened when is smaller than 100 Ωcm ² . Further, in order to make the contact resistance smaller than 100 Ωcm ² , the surface density of nitrogen of the film containing nitrogen and silicon is 8 × 10 ¹⁴ c.
It turns out that it should be smaller than m ^-2 . Similar results were obtained by using a laminated film of a film containing a first refractory metal and nitrogen and a second refractory metal film instead of the refractory metal film.

Therefore, based on such knowledge,
The surface density of nitrogen in a film containing nitrogen and silicon is set to 8 × 10 ^14.
The semiconductor device of the present invention having a ^{size of} less than cm ^-2 (claims 1 and 2)
According to this, the contact resistance is reduced and the delay time is shortened.

Further, in the method for manufacturing a semiconductor device of the present invention, when forming a film containing a metal and nitrogen on a silicon film, Gibbs which is generated when forming a nitride of the metal as the metal is formed. The value obtained by subtracting the decrease value of Gibbs free energy generated when forming the nitride from silicon from the decrease value of free energy is negative.

Therefore, when a heat treatment is performed after forming a metal film made of the metal on the film, nitrogen in the film moves to the silicon film, and nitrogen in the film changes to the metal. Spread outwards. As a result, the film is changed to a metal film made of the metal, and a film containing nitrogen and silicon is formed at the interface between the metal film and the silicon film.

This method has good controllability of the surface density of nitrogen,
A film containing nitrogen and silicon having a surface density of nitrogen of less than 8 × 10 ¹⁴ cm ^-2 can be easily formed, and the semiconductor device of the present invention can be easily manufactured.

According to the research conducted by the present inventors, a silicon film, a first conductive film formed on the silicon film and containing nitrogen, silicon, and a refractory metal, and the first conductive film. It was found that the first conductive film was not abnormally oxidized even if the stacked film formed with the second conductive film formed above was oxidized.

Therefore, if the above-mentioned laminated film is used as a film forming the electrodes and wirings, electrodes and wirings capable of preventing abnormal oxidation can be obtained (claim 4). further,
According to the study by the present inventors, if the first conductive layer is a conductive film in an amorphous state, the second conductive film having large crystal grains can be formed and the specific resistance of the second conductive film can be reduced. Do you get it.

Although the details of the mechanism are not clear, the present inventors presume as follows. When the underlying first conductive layer has a specific crystal structure, the second conductive layer is affected (strained) by the underlying crystal structure.

Here, the second conductive layer is affected differently (strained) when the crystal structure of the base is different, and when the crystal structure of the base is different depending on the place, the second conductive layer is distorted depending on the place. Receive.

Therefore, the second conductive layer formed on the first conductive layer having a different crystal structure depending on the location is subject to different strains depending on the location. If the second conductive layer exceeds a certain thickness and the strain exceeds a certain size, a grain boundary is formed, so that a large crystal grain is not formed.

On the other hand, if the underlying first conductive layer is in an amorphous state, the second conductive layer formed thereon will not be distorted differently depending on the location. For this reason, even if the second conductive layer is formed thick, no crystal grain boundary is generated, so that large crystal grains are formed and the specific resistance is reduced.

Further, in the method for manufacturing a semiconductor device of the present invention (claim 6), a part of or all of the first conductive film containing nitrogen and a refractory metal is subjected to a heat treatment to form a nitrogen gas as a reaction preventing film. , And a third conductive film containing silicon and a refractory metal.

Here, the formation rate of the third conductive film (nitride film) has a low dependency on the heat treatment temperature, and the film thickness of the third conductive film has a low dependency on the heat treatment time. Therefore, according to the present invention, since the process margin of the third conductive film is high, the third conductive film can be easily formed as designed.

[0048]

Embodiments will be described below with reference to the drawings. 1A to 1D are process sectional views showing a method of forming a gate electrode according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 is formed on a silicon substrate 1, and a 100 nm-thick polycrystalline silicon film to which a conductive impurity is added is formed on the silicon oxide film 2. 3 is formed. The natural oxide film on the surface of the polycrystalline silicon film 3 is removed in advance.

Next, as shown in FIG. 1B, a 10 nm thick tungsten nitride (specifically W ₂ N or WN) film 4 is formed on the polycrystalline silicon film 3 with N ₂ : Ar = 3: 2. Formed by reactive sputtering in an atmosphere of
A tungsten film 5 having a thickness of nm is formed by a sputtering method in an Ar atmosphere. This series of sputtering methods is preferably performed continuously without exposing the substrate to the atmosphere. Note that the tungsten nitride film 4 and the tungsten film 5 may be continuously deposited without exposing to the atmosphere after depositing the polycrystalline silicon film so that a natural oxide film is not formed on the surface of the polycrystalline silicon film 3. .

Next, as shown in FIG. 1C, a non-oxidizing atmosphere such as an inert atmosphere or a reducing atmosphere, for example, 750 to 1000 ° C. in an atmosphere of nitrogen, argon, hydrogen or a mixed gas thereof. The nitrogen film from the tungsten nitride film 4 is redistributed into the polycrystalline silicon film 3 by a heat treatment of about 10 ° C.
(Hereinafter, referred to as a silicon nitride (SiN _x ) film 6) is formed. By this method, the thickness of the silicon nitride film 6 is set to 1 nm.
The thickness of the silicon nitride film 6 can be controlled to about 0.2 to 1 nm as a result of actual control using X-ray photoelectron spectroscopy.

The tungsten nitride film 4 is changed as described above because the nitrogen in the tungsten nitride film 4 is re-distributed to the polycrystalline silicon film 3 so that the silicon nitride film 6 is formed and nitrided. This is because nitrogen in the tungsten film 4 diffuses outward, the tungsten nitride film 4 becomes a tungsten film, and is integrated with the tungsten film 5.

The mechanism by which nitrogen in the tungsten nitride film 4 moves to the polycrystalline silicon film 3 is considered as follows. The reduction in Gibbs free energy when forming tungsten nitride from tungsten is less than that when forming silicon nitride from silicon. Therefore, in the state where the tungsten nitride film 4 and the polycrystalline silicon film 3 are in contact with each other, the chemical potential of nitrogen is smaller on the polycrystalline silicon film 3 side. As a result, nitrogen in the tungsten nitride film 4 moves to the polycrystalline silicon film 3.

The reason why nitrogen in the tungsten nitride film 4 diffuses outward is that the change in Gibbs free energy changes from the negative direction to the positive direction. Therefore, outward diffusion of nitrogen is thermodynamically stable. Is.

When a natural oxide film is formed on the surface of the polycrystalline silicon film 3, the tungsten nitride film 4 and the tungsten film 5 are deposited on the native oxide film, and the heat treatment is performed as described above. Instead of the (SiN _x ) film 6, a natural oxide film of silicon nitride containing oxygen (SiO _x N
_y ) A film is formed.

Finally, as shown in FIG. 1D, the tungsten film 5, the silicon nitride film 6, and the polycrystalline silicon film 3 are processed into a gate electrode shape to complete the gate electrode. Figure 1
According to the characteristic diagram showing the relationship between the delay time and the contact resistance found by the present inventors shown in FIG. 3, it can be seen that the delay time greatly changes at the contact resistance of 100 (Ωcm ² ). . That is, the contact resistance is 100
If it is smaller than (Ωcm ² ), the delay time can be greatly reduced.

FIG. 2 shows the relationship between the contact resistance and the film thickness of the silicon nitride film 6 of the gate electrode formed according to the forming method of this embodiment. In the figure, a characteristic curve a is a polycrystalline silicon film 3 to which a high concentration of n-type impurities is added, and a characteristic curve b is a polycrystalline silicon film 3 to which a high concentration of p-type impurities is added. The result when using is shown.

In the case of the p ⁺ type polycrystalline silicon film from FIG. 2, for example, the contact resistance is 100 (Ωcm ² ).
In order to ensure the above, the nitrogen surface density at the interface of the silicon nitride film 6 with the tungsten film is less than 8 × 10 ¹⁴ cm ^-2 (converted into the thickness of the silicon nitride film 6 is less than 1 nm)
I know you need to. Further, it can be seen from FIG. 2 that the contact resistance greatly changes at a nitrogen surface density of 8 × 10 ¹⁴ cm ^-2 . That is, the nitrogen surface density is 8 ×
It can be seen that the contact resistance can be significantly reduced by setting it to less than 10 ¹⁴ cm ^-2 .

As described above, the forming method of this embodiment is
The nitrogen surface density of the silicon nitride film 6 can be made less than 8 × 10 ¹⁴ cm ^-2 . Therefore, according to this embodiment, the silicon nitride film 6 can be formed thin and the contact resistance can be reduced, so that the delay time can be improved.

FIG. 3 shows the interfacial nitrogen concentration in the laminated electrode of polycrystalline silicon film / reaction prevention film (SiN _x , SiO _x N _y , SiO ₂ ) / tungsten film and heat treatment of this laminated electrode (N ₂ atmosphere, 800). FIG. 3 is a characteristic diagram showing the relationship with the sheet resistance of the tungsten film after 1 hour (° C.). Here, the film thickness of the tungsten film was 100 nm.

From FIG. 3, the reaction prevention film is the SiN _x film, S
In the case of an iO _x N _y film, the interfacial nitrogen concentration is 2.2 × 10
Up to ¹⁴ cm ^-2 (0.3n in terms of SiN _x film thickness conversion)
m) It can be seen that the sheet resistance is kept at a low level. Therefore, as in this embodiment, S is used as the reaction preventing film.
If an iN _x film (silicon nitride film 6) or a SiO _x N _y film is used, adverse effects of heat treatment can be prevented.

On the other hand, when the reaction preventive film is a conventionally used SiO ₂ film, it can be seen that the sheet resistance increases when the film thickness becomes about 2 nm or less. The increase in sheet resistance is because the tungsten film and the polycrystalline silicon film react with each other to form silicide.

In the forming method of this embodiment, when the tungsten nitride film 4 is formed by the sputtering method,
The polycrystalline silicon film 3 may be extremely thinly nitrided by the plasma generated in the atmosphere to form a silicon nitride film. In this case, both the silicon nitride film and the silicon nitride film 6 formed by redistribution of nitrogen from the tungsten nitride film 4 can be used as the reaction preventing film.

In the present embodiment, the case where the tungsten nitride film 4 is entirely changed to the tungsten film has been described. However, as shown in FIG. 4A, the thickness of the silicon nitride film 6 is changed according to the required thickness. The gate electrode can be formed while leaving part of the tungsten nitride film 4.

Further, after the step of FIG.
As shown in (b), even if a thick tungsten nitride film 4a is formed on the polycrystalline silicon film 3, the structure shown in FIG. 1 (c) can be formed.

That is, after the step of FIG. 1A, a thick tungsten nitride film 4a having a thickness of about 100 nm is sputtered on the polycrystalline silicon film 3 in an atmosphere gas containing nitrogen or excited nitrogen or ionized nitrogen. After being formed by using the method, heat treatment is performed in a non-oxidizing atmosphere, particularly a reducing atmosphere, as in the above embodiment.

As a result, the nitrogen in the tungsten nitride film 4a migrates to the polycrystalline silicon film 3 and the thickness of 1 nm is about 1 nm.
A silicon nitride film of about atomic size is formed, and nitrogen in the tungsten nitride film 4a is diffused outward to form a tungsten film, so that a structure as shown in FIG. 1C is formed.

Furthermore, in this embodiment, the laminated film was processed into a gate electrode shape after redistribution and outdiffusion of nitrogen in the tungsten nitride film, but when this processing is performed by anisotropic etching, heat treatment is performed. The etching rate and the like may change due to the crystal growth of the tungsten film due to.

In order to eliminate such an influence, heat treatment for redistribution of nitrogen and outward diffusion may be carried out after processing the laminated film. The special heat treatment for forming the tungsten nitride film may be replaced with another heat treatment, for example, a heat treatment for activating impurities in the source diffusion layer and the drain diffusion layer in a later step.

FIGS. 5A to 5C are process sectional views showing a method of forming a gate electrode according to the second embodiment of the present invention. First, FIG.
As shown in (a), a silicon oxide film 12 as a gate insulating film is formed on a silicon substrate 11, and a polycrystalline silicon film 13 having a thickness of 100 nm is formed on the silicon oxide film 12.
To form.

Next, as shown in FIG. 5B, an ultrathin silicon nitride film 14 having a thickness of less than 1 nm, preferably about 0.7 nm is formed as a reaction preventing film. Such an ultrathin silicon nitride film 14 is preferably formed by, for example, one of the following five film forming methods (1) to (5).

(1) Film formation by thermal nitriding method at a temperature of 1000 ° C. for 30 seconds in NH ₃ atmosphere (2) Film formation by plasma nitriding in a gas containing nitrogen (3) By thermal CVD method at 600 to 800 ° C. Film formation (source gas: SiH ₂ Cl ₂ + NH ₃ or SiH ₄
+ NH ₃ ) (4) Film formation by plasma CVD method (5) Substrate temperature of 500 to 800 ° C., plasma generated in a region different from the silicon substrate 11 (plasma: N ₂ / H ₂
Alternatively, a film is formed by NH ₃ ), that is, active species in plasma are supplied to the substrate by downflow.

After this, a thickness of 10 is formed on the silicon nitride film 14.
A 0 nm tungsten film 15 is formed by the sputtering method. Finally, as shown in FIG. 5C, the laminated film of the tungsten film 15, the silicon nitride film 14, and the polycrystalline silicon film 13 is processed into a desired gate electrode shape to complete the gate electrode.

Since the thin silicon nitride film 14 can be formed also by the forming method of this embodiment, the same effect as that of the previous embodiment can be obtained. Although the gate electrode has been described in the first and second embodiments, the present invention can be applied to other electrode or wiring structures.

FIG. 6 shows an MO according to the third embodiment of the present invention.
It is an element sectional view showing the structure of SFET. This will be described according to manufacturing steps. First, an insulating film 22 for element isolation and a gate oxide film 23 are formed on the surface of a silicon substrate 21.

Next, after a laminated film composed of the polycrystalline silicon film 24, the silicon nitride film 25, and the tungsten film 26 is formed on the gate oxide film 23, silicon nitride (SiN) as an insulating film for cap is formed on the tungsten film 26. The film 27 is formed.

Here, the silicon nitride film 25 is formed thin as described above so that the contact resistance becomes sufficiently small and the delay time is improved. In addition, the silicon nitride film 2
7 is usually NH ₃ gas and inorganic silane gas SiH ₂ Cl ₂
It is formed by the LPCVD method using a gas and a source gas,
If NH ₃ and SiH ₂ Cl ₂ are introduced in advance, the surface of the tungsten film 26 is nitrided unevenly, and silicon nitride grows granularly, so that the silicon nitride film 27 may not function as a cap insulating film. is there.

In order to prevent such inconvenience, NH ₃ and S
It is effective to introduce SiH ₂ Cl ₂ alone to form a thin film containing silicon on the tungsten film 26 before introducing iH ₂ Cl ₂ . It was confirmed that a uniform silicon nitride film 27 could be formed by this method.

Next, after a laminated film composed of the polycrystalline silicon film 24, the silicon nitride film 25 and the tungsten film 26 is processed to form a gate electrode, N ₂ gas, H ₂ gas and H ₂ O are formed.
Using the mixed gas with the gas, only the polycrystalline silicon film 24 and the silicon substrate 21 are selectively oxidized. Oxidation of the polycrystalline silicon film 24 and the like increases the thickness of the oxide film at the gate end, which can prevent a decrease in reliability due to electric field concentration at the gate end.

Next, after forming a low-concentration shallow impurity diffusion layer (source / drain region) 28 by ion implantation or the like,
A silicon nitride film 29 is formed as a gate sidewall insulating film. The silicon nitride film 29 can be formed by the same method as described above. The silicon nitride film 29 and the silicon nitride film 27 cover the gate electrode composed of the polycrystalline silicon film 24, the silicon nitride film 25, and the tungsten film 26 with the silicon nitride film, so that the subsequent oxidation in an oxidizing atmosphere is performed. It is possible to prevent the tungsten film 26 from being oxidized by the process.
When a material containing Cu is used for the upper layer wiring, Cu can be prevented from entering the gate electrode. Furthermore, the polycrystalline silicon film 24 is a silicon nitride film 25,
Since it is completely covered by 27 and 29, it is possible to improve the adhesion between them.

Finally, after forming a high-concentration deep impurity diffusion layer 30, a metal silicide 31 is formed on this impurity diffusion layer 30 to complete the MOS transistor having the structure shown in FIG.

FIG. 7 is a sectional view showing the structure of the wiring according to the fourth embodiment of the present invention. This will be described according to the manufacturing process. First, the insulating film 42 for element isolation and the impurity diffusion layer 43 are formed on the silicon substrate 41.

Next, a SiO ₂ film 44 as an interlayer insulating film having a thickness of about 600 nm is formed on the entire surface by the CVD method, and then a contact hole 45 for the impurity diffusion layer 43 is opened in the SiO ₂ film 44.

Next, the thickness 100 including the impurity diffusion layer 43 is the same.
A laminated film including a polycrystalline silicon film 46 having a thickness of about nm, a thin silicon nitride film 47, and a tungsten film 48 having a thickness of about 100 nm is formed by, for example, any of the above-described methods.

Finally, the laminated film is processed into a wiring having a desired shape to complete the wiring having the structure shown in FIG. According to the wiring having such a structure, the contact resistance is reduced and the delay time is improved by forming the silicon nitride film 47 thin.

FIG. 8 is a process sectional view showing a method of forming a gate electrode according to the fifth embodiment of the present invention. First, FIG.
As shown in (a), a silicon oxide film 52 as a gate insulating film is formed on a silicon substrate 51, and a polycrystalline silicon film 53 containing conductive impurities and having a thickness of 100 nm is formed on the silicon oxide film 52. .

Next, as shown in FIG. 8B, a tungsten nitride film 54 having a thickness of about 1 to 10 nm and a tungsten film 55 having a thickness of 10 nm are sequentially formed on the polycrystalline silicon film 53.

Specifically, for example, Ar: N ₂ = 1: 1
After sputtering the tungsten target in the atmosphere of (reactive sputtering) to form the tungsten nitride film 54,
By removing N ₂ and sputtering a tungsten target with Ar alone, the tungsten film 55 is continuously formed in the same vacuum without exposing the silicon substrate 51 to the atmosphere.

The tungsten film 55 and the tungsten nitride film 54 can also be formed by the CVD method. In this case, the tungsten film is 400 to 500 ° C., the source gas is WF ₆ + H ₂ , and the tungsten nitride film is 500 to 500 ° C.
A film is formed under the conditions of 700 ° C. and source gas WF ₆ + NF ₃ .

Next, as shown in FIG. 8C, heat treatment is performed at 800 ° C. or higher for 30 minutes in a reducing atmosphere containing hydrogen to form a tungsten nitride film 54 of tungsten, silicon and nitrogen (see FIG. 10n thick (consisting of 3 elements)
The reaction preventive film 56 having a thickness of m or less is used.

The reason why the heat treatment is performed in a reducing atmosphere containing hydrogen is to prevent the tungsten film 55 from being oxidized. The mechanism by which the reaction preventing film 56 is formed is as follows. First, by heat treatment, part of nitrogen in the tungsten nitride film 54 escapes to the outside through the tungsten film 55 or diffuses outward into the polycrystalline silicon film 53 to form a tungsten film. This tungsten film is integrated with the tungsten film 55.

Further, part of the tungsten nitride forming the tungsten nitride film 54 diffuses into the polycrystalline silicon film 53, and conversely, a part of the polycrystalline silicon film 54 diffuses into the tungsten nitride film 54, so that tungsten is formed. A reaction preventive film 56 made of silicon and nitrogen is formed.

Even if the reaction preventing film 56 contains oxygen of the natural oxide film formed on the polycrystalline silicon film 53, the barrier property of the interface between the tungsten film 55 and the polycrystalline silicon film 53 is maintained. Be drunk

At this time, the reaction preventing film 56 can be easily formed as designed for the reason explained in the item of action. Further, since the reaction preventive film 56 is conductive, the contact resistance between the reaction preventive film 56 and the polycrystalline silicon film 53,
The contact resistance between the reaction preventing film 56 and the tungsten film 55 is small.

Further, as a result of examination by cross-sectional TEM and EDX analysis, the proportions of tungsten, silicon and nitrogen in the reaction preventive film 56 are 20%, 60% and 20%, respectively.
It was about.

Finally, as shown in FIG. 8D, the polycrystalline silicon film 53, the reaction preventive film 56, and the tungsten film 55.
The gate electrode is completed by patterning the laminated film of.
FIG. 9 is a sectional view showing the structure of a CMOS transistor according to the sixth embodiment of the present invention.

Explaining this in accordance with the manufacturing process, first,
Insulating film 62 for element isolation, p on the surface of silicon substrate 70
The type well layer 71 and the n-type well layer 72 are formed. An n-type MOS transistor is formed in the p-type well layer 71, and a p-type MOS transistor is formed in the n-type well layer 72.

Next, the gate oxide film 6 is formed on the p-type well layer 71.
After the gate oxide film 63p is formed on the 3n, n-type well layer 72, a polycrystalline silicon film 64n containing an n-type impurity is formed on the gate oxide film 63n, and the gate oxide film 63 is formed.
A polycrystalline silicon film 64p containing p-type impurities is formed on p.

Next, on the polycrystalline silicon films 64n and 64p, reaction preventing films 65n and 65p containing nitrogen, tungsten and silicon, and tungsten films 66n and 6 respectively.
After sequentially forming 6p, tungsten films 66n and 66p are formed.
Silicon nitride (SiN) films 67n and 67p as insulating films for caps are formed on the respective layers.

The method of forming the reaction preventing films 65n and 65p is the same as that of the fifth embodiment. In addition, the reaction prevention film 65
n and 65p are formed, the polycrystalline silicon film 64n,
Even if a natural oxide film is formed on the surface of 64p, it does not affect the barrier effect.

Next, the polycrystalline silicon film 64n, the reaction preventive film 65n, the tungsten film 66n and the silicon nitride 67.
By etching n, the gate electrode of the n-type MOS transistor is formed.

At this time, the polycrystalline silicon film 64p, the reaction preventing film 65p, the tungsten film 66p and the silicon nitride 67p are simultaneously etched to form the gate electrode of the p-type MOS transistor.

Next, using a mixed gas of N ₂ gas, H ₂ gas and H ₂ O gas, the polycrystalline silicon films 64n, 65p, p
Silicon of the type well layer 71 and the n-type well layer 72 is selectively oxidized. This method is, for example, JP-A-60-9.
The method disclosed in 166 is used. As a result, the oxide film at the gate end becomes thicker, and it is possible to prevent a decrease in reliability due to electric field concentration at the gate end.

Here, in this embodiment, the reaction preventive film 65 is used.
Since a nitride of the same metal as the metal forming the gate electrode (metal nitride) is used as n and 65p,
During the selective oxidation of silicon, the reaction preventive films 65n and 6n are formed.
It is possible to effectively prevent abnormal oxidation of 5p. This is a new fact found by the inventors of the present application and the reason is not clear. Of course, the above metals may be different.

The metal is preferably a material capable of reducing a metal nitride to a metal by a heat treatment in a reducing atmosphere in a subsequent step. In the case of the present embodiment, the metal is tungsten, The metal nitride is tungsten nitride.

Tungsten nitride becomes amorphous depending on the content of nitrogen. In this embodiment, the amorphous state is obtained by setting the proportion of nitrogen in the reaction preventing films 65n and 65p to 5 to 20%. In addition, the polycrystalline silicon films 64n and 64p and the tungsten films 66n and 66
The reaction with p can be effectively prevented.

When the reaction preventing films 65n and 65p are in the amorphous state, the crystal grains of the tungsten films 65n and 65p on the reaction preventing films 65n and 65p are large, as described in the item of the action, so that the specific resistance is reduced.

Next, low-concentration shallow source / drain regions (impurity diffusion layers) 68n and 68p are formed by ion implantation, and then silicon nitride films 69n and 69p are formed as gate sidewall insulating films. These silicon nitride films 69
The side surfaces and the upper surface of the gate electrode are protected by the n and 69p and the silicon nitride films 67n and 67p. Therefore, the tungsten films 66n and 66p are not oxidized by the oxidation process in the subsequent process.

Finally, after the high concentration deep source / drain regions 60n and 60p are formed by the ion implantation method,
Metal silicides 61n and 61p are formed on the source / drain regions 60n and 60p to complete the CMOS transistor having the structure shown in FIG.

FIG. 10 is a process sectional view showing the method of forming a gate electrode according to the seventh embodiment of the present invention. First, as shown in FIG. 10A, a silicon oxide film 82 as a gate insulating film is formed on a silicon substrate 81, and a thickness of 100 nm including conductive impurities is formed on the silicon oxide film 82.
Of polycrystalline silicon film 83 is formed.

Next, as shown in FIG. 10B, a molybdenum nitride film 84 having a thickness of about 1 to 10 nm and a molybdenum film 85 having a thickness of 10 nm are sequentially formed on the polycrystalline silicon film 83.

Specifically, for example, Ar: N ₂ = 1: 1
After the molybdenum target is sputtered in the atmosphere (reactive sputtering) to form the molybdenum nitride film 84, N ₂
By removing the target and sputtering a molybdenum target with Ar alone, the molybdenum film 85 is continuously formed in the same vacuum without exposing the silicon substrate 81 to the atmosphere.

Next, as shown in FIG. 10C, heat treatment is performed at 800 ° C. or higher for 30 minutes in a reducing atmosphere containing hydrogen to form a molybdenum nitride film 84 with a thickness of molybdenum, silicon and nitrogen. Reaction prevention film 86 of 10 nm or less
Change to.

Here, the reason why the process is performed in a reducing atmosphere containing hydrogen is to prevent the molybdenum film 85 from being oxidized. Further, similarly to the case of the fifth embodiment, the reaction preventing film 86 as designed can be easily formed. Further, since the reaction preventive film 86 is conductive, the contact resistance between the reaction preventive film 86 and the polycrystalline silicon film 83 and the contact resistance between the reaction preventive film 86 and the molybdenum film 85 are small.

Finally, as shown in FIG. 10D, the polycrystalline silicon film 83, the reaction preventive film 86, the molybdenum film 85.
The gate electrode is completed by patterning the laminated film of.
In the examples described so far including this example, the laminated film was patterned after forming the reaction preventing film.
The reaction preventive film may be formed after patterning the laminated film.

[0116]

As described in detail above, according to the present invention, when a laminated film of silicon film / film containing nitrogen and silicon / refractory metal film is used for electrodes (wiring), nitrogen and silicon Since the surface area density of nitrogen of the film including is less than 8 × 10 ¹⁴ cm ^-2 , the contact resistance is sufficiently small, and the delay time can be greatly improved.

Furthermore, according to the present invention, since the laminated film of the silicon film / first conductive film / second conductive film containing nitrogen, silicon and refractory metal is used for the electrodes (wiring), It is possible to prevent abnormal oxidation of the first conductive film during the oxidation process.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of forming a gate electrode according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between a film thickness of a silicon nitride film and a contact resistance.

FIG. 3 is a characteristic diagram showing the relationship between the film thickness of the reaction preventive film and the sheet resistance.

FIG. 4 is a sectional view showing a modification of the first embodiment.

FIG. 5 is a process sectional view showing a method of forming a gate electrode according to a second embodiment of the present invention.

FIG. 6 is an element sectional view showing a structure of a MOSFET according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing the structure of a wiring according to a fourth embodiment of the present invention.

FIG. 8 is a process sectional view showing a method of forming a gate electrode according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing the structure of a CMOS transistor according to a sixth embodiment of the present invention.

FIG. 10 is a process sectional view showing a method of forming a gate electrode according to a seventh embodiment of the present invention.

FIG. 11 is a diagram for explaining a conventional problem.

FIG. 12 is a diagram for explaining a conventional problem.

FIG. 13 is a characteristic diagram showing a relationship between contact resistance and delay time.

FIG. 14 is a diagram for explaining abnormal oxidation of a gate electrode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Polycrystalline silicon film, 4 ... Tungsten nitride film, 5 ... Tungsten film, 6 ... Silicon nitride film 11 ... Silicon substrate, 12 ... Silicon oxide film, 13 ... Polycrystalline silicon Film, 14 ... Silicon nitride film, 15 ... Tungsten film 21 ... Silicon substrate, 22 ... Insulating film, 23 ... Gate oxide film, 24 ... Polycrystalline silicon film, 25 ... Silicon nitride film,
26 ... Tungsten film, 27 ... Silicon nitride film, 28 ...
Impurity diffusion layer, 29 ... Shallow silicon nitride film, 30 ... Deep impurity diffusion layer, 31 ... Metal silicide 41 ... Silicon substrate, 42 ... Insulating film, 43 ... Impurity diffusion layer, 44 ... SiO ₂ film, 45 ... Contact hole, 46
... Polycrystalline silicon film, 47 ... Silicon nitride film, 48 ... Tungsten film 51 ... Silicon substrate, 52 ... Insulating film, 53 ... Polycrystalline silicon film, 54 ... Tungsten nitride film, 55 ... Tungsten film, 56 ... Reaction prevention film 60n , 60 ... Deep source / drain regions, 61n, 6
1p ... Metal silicide layer, 62n, 62p ... Insulating film, 6
3n, 63p ... Gate oxide film, 64n, 64p ... Polycrystalline silicon film, 65n, 65p ... Reaction prevention film, 66n, 6
6p ... Tungsten film, 67n, 67p ... Silicon nitride film, 68n, 68p ... Shallow source / drain region, 69
n, 69p ... Silicon nitride film, 70 ... Silicon substrate, 7
1 ... p-type well layer, 72n ... n-type well layer, 81 ... silicon substrate, 82 ... silicon oxide film, 83 ... polycrystalline silicon film, 84 ... molybdenum nitride film, 85 ... molybdenum film,
86 ... Reaction prevention film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication 7514-4M H01L 29/78 301 G (72) Inventor Kazuaki Nakajima Komukai, Kawasaki City, Kanagawa Prefecture Toshiba Town No. 1 Incorporated company Toshiba Research and Development Center (72) Inventor Tadashi Iijima Komukai Toshiba No. 1 in Kawasaki City, Kanagawa Prefecture

Claims (6)

[Claims] 1. A silicon film, which is formed on the silicon film and contains nitrogen and silicon, wherein the nitrogen has an area density of 8 ×.
A semiconductor device comprising at least one of an electrode and a wiring formed by laminating a film having a thickness of less than 10 ¹⁴ cm ^-2 and a refractory metal film formed on the film. 2. A silicon film, which is formed on the silicon film and contains nitrogen and silicon, wherein the nitrogen has an area density of 8 ×.
An electrode having a film of less than 10 ¹⁴ cm ^-2, a film formed on the film, containing a refractory metal and nitrogen, and a film formed on the film, the film being made of the refractory metal, and A semiconductor device comprising at least one of wirings. 3. A step of forming a film containing a metal and nitrogen on a silicon film, wherein the value of the Gibbs free energy lowering value generated when forming a nitride of the metal as the metal A step of forming a film containing the metal and nitrogen using a material in which the value obtained by subtracting the lowering value of the Gibbs free energy that occurs when forming the nitride is negative, and a step of forming a film from the metal by heat treatment. While changing to a metal film that becomes, the interface between the metal film and the silicon film,
And a step of forming a film containing nitrogen and silicon and forming at least one of an electrode and a wiring including a laminated film of the silicon film, the film containing nitrogen and silicon, and the metal film. A method of manufacturing a semiconductor device, comprising: 4. A silicon film, a first conductive film formed on the silicon film and containing nitrogen, silicon, and a refractory metal, and a second conductive film formed on the first conductive film. A semiconductor device comprising at least one of an electrode and a wiring formed by stacking and. 5. The semiconductor device according to claim 4, wherein the first conductive film is an amorphous conductive film. 6. A step of forming a first conductive film containing nitrogen and a refractory metal on a silicon film, a step of forming a second conductive film on the first conductive film, and a heat treatment, Part or all of the first conductive film is changed to a third conductive film containing nitrogen, silicon, and the refractory metal, and the silicon film, the first conductive film, and the third conductive film. And a step of forming at least one of an electrode and a wiring including a laminated film of the above.