JP3655013B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device characterized by a laminated structure electrode (wiring) and having good impurity diffusion prevention performance and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, polycrystalline silicon has been widely used as a material for electrodes and wiring of semiconductor devices. However, with the high integration and high speed of semiconductor devices, signal transmission delay due to the resistance of electrodes and wiring has become a serious problem.
[0003]
This type of delay can be suppressed by reducing the resistance of the electrodes and wiring. For example, in the case of a gate electrode such as a MOS transistor, it can be suppressed by adopting a polycide gate having a two-layer structure of a metal silicide film and a polycrystalline silicon film.
[0004]
However, after the 0.25 μm gate length, a gate electrode having a resistance lower than that of the polycide gate is required. Recently, a polymetal gate having a laminated structure of a refractory metal film, a reaction barrier layer, and a polycrystalline silicon film has attracted attention. Has been.
[0005]
If tungsten (W) is used as the refractory metal, the specific resistance of tungsten is tungsten silicide (WSi). _x The RC delay time can be greatly shortened because it is about an order of magnitude smaller than (). Tungsten is a material that easily reacts with polycrystalline silicon by heat treatment at about 600 ° C. However, there is no problem because a reaction barrier layer is sandwiched between the W film and the polycrystalline silicon film.
[0006]
In the future, a metal gate of a refractory metal single layer is considered promising instead of a polymetal gate. Thus, the use of a high melting point metal is indispensable for reducing the resistance of the gate electrode.
[0007]
However, refractory metals such as tungsten are very easily oxidized. For example, tungsten is oxidized at about 400 ° C. Tungsten oxide is an insulator, and tungsten causes volume expansion with oxidation.
[0008]
In general, in an LSI manufacturing process, a process of performing re-oxidation for the purpose of improving the reliability of an oxide film such as a gate oxide film after forming a gate electrode pattern is required. For example, in the case of a polycrystalline silicon gate, after a polycrystalline silicon film is formed on a silicon substrate and patterned to form a gate electrode, an oxidized portion called a bird's beak is formed at the end of the gate oxide film. The As a result, the lower end portion of the gate electrode is rounded and the electric field in the gate portion is relaxed, so that the characteristics and reliability of the element can be improved. Hereinafter, this process is referred to as post-oxidation. WSi with this type of post-oxidation as metal silicide _x When applied to a polycide gate using WSi _x Is usually Si-rich than the normal composition x = 2.0, so in the post-oxidation step, WSi _x The excess silicon inside is oxidized and WSi _x SiO also on the surface ₂ Thus, the same insulating effect can be obtained by an oxidation method similar to that of crystalline silicon.
[0009]
On the other hand, when this type of post-oxidation is applied to a polymetal gate using W as a refractory metal, W is also oxidized in a normal oxidation process. _Three Is formed. At this time, due to the large volume expansion, film peeling or the like occurs, and subsequent processes cannot be continued.
[0010]
Also, O mixed from the atmosphere ₂ And H ₂ Oxidizing agents such as O may oxidize W before starting the oxidation process, which can cause similar problems. Therefore, in the case of a polymetal gate, a technique (selective oxidation technique) that oxidizes only silicon without oxidizing a refractory metal is required in the post-oxidation process.
[0011]
When the exposed portion of silicon and the exposed portion of the refractory metal such as W are mixed on the same substrate as in the case of the polymetal gate, only the silicon is selectively oxidized without oxidizing the exposed portion of the refractory metal. A selective oxidation method for oxidizing is known (Japanese Patent Laid-Open No. 60-9166).
[0012]
This selective oxidation method uses H as an oxidizing agent. ₂ O and H as a reducing agent ₂ When oxidizing in a mixed atmosphere with H ₂ O / H ₂ The partial pressure ratio is set within a certain range.
[0013]
As an application example of this technology, a W single-layer metal gate is replaced with H. ₂ / H ₂ There is a report of oxidation in an O atmosphere (RFKwasnick et al., J. Electrochem. Soc., Vol 135, pp176 (1988)). According to the experimental results of the reporters, a sample in which a W film (gate electrode) having a thickness of 200 nm is stacked on a thin silicon oxide film (gate oxide film) having a thickness of 5 nm is used. ₂ / H ₂ As a result of oxidation at 900 ° C. for about 30 minutes in an O atmosphere, the silicon oxide film immediately below the W film was thickened to 20 nm.
[0014]
This phenomenon is caused by the diffusion of the oxidizing agent through the grain boundary of the W film. That is, the selective oxidation technique does not oxidize the W film, but oxidizes silicon in the silicon oxide film immediately below the W film. Therefore, when the selective oxidation is applied to the metal gate, the thickness of the gate oxide film increases, which causes a fatal problem that the driving capability of the transistor is reduced.
[0015]
Considering that the selective oxidation is applied to a polymetal gate having a laminated structure of a W film and a polycrystalline silicon film, it can be easily estimated that the polycrystalline silicon film immediately below the W film is similarly oxidized. Oxidation of the polycrystalline silicon film at the interface between the W film and the polycrystalline silicon film causes an increase in contact resistance at this interface, which causes a problem that RC delay increases.
[0016]
As described above, in order to reduce the resistance of the gate electrode, a metal having a high conductivity is laminated with polycrystalline silicon, and an electrode structure having both high compatibility with the gate insulating film and the substrate and high conductivity is obtained. It may be used, but the combination with a normal metal cannot withstand the high temperature during the LSI manufacturing process. In particular, in the self-aligned ion implantation technique using the gate electrode as a mask recently introduced with the miniaturization and speeding up of the element, it is necessary to perform the activation heat treatment after the impurity implantation after the gate electrode is formed. High heat resistance is required.
[0017]
Further, in the high-temperature heat treatment after the ion implantation at 800 to 900 ° C. including the post-oxidation step, Si atoms or additive impurity atoms are thermally diffused from the polycrystalline silicon into the refractory metal or its silicide. As a result of gate impurity depletion due to lowering of the impurity concentration, or in CMOS (complementary MOS), impurities pass through the refractory metal or silicide and the n and p regions are interdiffused to change the work function. There has been a problem that the threshold voltage fluctuates.
[0018]
[Problems to be solved by the invention]
As described above, the conventional polymetal gate has a problem in that the polycrystalline silicon under the refractory metal film constituting the polymetal gate is oxidized in the post-oxidation process, and the RC delay is increased. Further, the conventional metal gate has a problem that the gate oxide film under the refractory metal, which is the metal gate, is oxidized and thickened in the post-oxidation process, and the driving capability of the transistor is lowered.
[0019]
The present invention has been made in view of the above circumstances, and the object of the present invention is to suppress oxidation of a semiconductor film under the high melting point film in an electrode or wiring using a high melting point metal. Manufacturing method of semiconductor device Is to provide.
[0025]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a silicon film on a substrate, and as a refractory metal, At least one of Mo, W, Cr, Co And at least one of nitrogen and carbon and the refractory metal on the silicon film. Compound film consisting of Forming a step; Forming a metal film made of the refractory metal on the compound film; , By heat treatment, Compound The refractory metal film Integrated with the metal film And said Integrated A conductive antioxidant film containing at least one of nitrogen and carbon, the refractory metal, and silicon is formed at the interface between the metal film and the silicon film, and the metal film, the antioxidant film, and the silicon film are formed. Forming at least one of an electrode and a wiring including the laminated film, and the antioxidant film After forming And a step of oxidizing the silicon film.
[0026]
Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor film on a substrate, and a step of forming a semiconductor film on the semiconductor film. Including a compound composed of at least one refractory metal of Mo, W, Cr, Co, at least one of nitrogen and carbon, and silicon Forming a conductive anti-oxidation film, and on the anti-oxidation film; Said Forming a metal film made of a refractory metal, etching the laminated film made of the metal film, the antioxidant film, and the semiconductor film to form at least one of an electrode and a wiring including the laminated film; The antioxidant film After forming And a step of oxidizing the semiconductor film.
[0027]
Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor region, and a step of forming an insulating film on the insulating film. Including a compound composed of at least one refractory metal of Mo, W, Cr, Co, at least one of nitrogen and carbon, and silicon Forming a conductive anti-oxidation film, and on the anti-oxidation film; Said Forming a metal film made of a refractory metal, etching the laminated film made of the metal film and the antioxidant film to form at least one of an electrode and a wiring including the laminated film, and the antioxidant film After forming And a step of oxidizing the semiconductor region.
[0028]
Another semiconductor device manufacturing method according to the present invention is characterized in that, in the semiconductor device manufacturing method, the step of performing the oxidation treatment is performed in an atmosphere containing hydrogen and water.
[0033]
In addition, the present inventors have provided a reaction preventing film provided between a refractory metal film and a silicon film. The In the process of research, a film made of at least one of nitrogen and carbon, a refractory metal, and silicon not only prevents the reaction between the refractory metal film and the silicon film, but the oxidant is a refractory metal. It has been found that it also has a function of preventing diffusion through the film into the silicon oxide film. Thereby, in a film containing silicon (silicon film, silicon oxide film) underlying a metal film made of a refractory metal, oxidation of the film containing silicon and reaction between the film and the metal film in post-oxidation can be prevented. Become. Further, according to the studies by the present inventors, silicon nitride (carbide) is formed from the Gibbs free energy reduction value that occurs when forming a nitride (carbide) of a refractory metal as a refractory metal. It was found that an antioxidant film composed of a refractory metal, nitrogen (carbon), and silicon can be easily formed by using a negative value obtained by subtracting the Gibbs free energy reduction value generated at the time. Specifically, Mo, W, Cr, Co It is preferable to use a refractory metal such as It has also been found that if the above-described conditions are satisfied, the antioxidant film may contain about 20% oxygen.
[0034]
In the method of manufacturing a semiconductor device for safely performing selective oxidation of silicon in the above invention, a substrate to be processed having an exposed portion of silicon is accommodated in a processing container, and H is contained in the processing container. ₂ Gas, H ₂ O gas and H ₂ While introducing a non-oxidizing gas different from the gas, the H in the processing vessel ₂ It is desirable to selectively oxidize the exposed portion of the silicon by setting the partial pressure of the gas to less than 4% and the temperature of the substrate to be processed to 600 ° C. or higher.
[0035]
The semiconductor manufacturing apparatus that performs the selective oxidation includes a processing container that accommodates a substrate to be processed and performs an oxidation process, and an H in the processing container. ₂ Gas, H ₂ O gas and H ₂ Gas introduction means for introducing a non-oxidizing gas different from the gas, and the H in the processing vessel ₂ A partial pressure control means for setting the partial pressure of the gas to less than 4% and a heating means for heating the substrate to be processed at a temperature of 600 ° C. or higher may be provided.
[0036]
Further, the semiconductor device manufacturing method and the semiconductor manufacturing apparatus preferably have the following characteristics.
[0037]
(1) Oxidation is performed while maintaining the pressure in the processing vessel at a negative pressure rather than atmospheric pressure.
[0038]
(2) The inside of the processing vessel is once depressurized to 1 Pa or less, and then an oxidation treatment is performed.
[0039]
According to a preferable method of manufacturing a semiconductor device of the present invention, in a state where the substrate temperature is set to a temperature of 600 ° C. or more which is not less than the oxidation limit, ₂ Since the partial pressure of the gas is set to a low pressure (low concentration) below the explosion limit, silicon can be selectively oxidized safely.
[0040]
Further, according to a desirable semiconductor manufacturing apparatus of the present invention, H ₂ Since the gas partial pressure can be set to a low pressure (low concentration) below the explosion limit, H ₂ The gas can be treated in the same way as an inert gas. Therefore, the selective oxidation of silicon can be performed safely without complicating the device configuration and incurring high costs.
[0041]
As an application of the present invention, in an electrode or wiring using a refractory metal, it is possible to provide a semiconductor device and a manufacturing method capable of suppressing the diffusion of impurities from the underlying semiconductor film in the refractory metal.
[0042]
A semiconductor device according to this object includes at least a first layer made of polycrystalline silicon, a second layer formed on the first layer and made of one of metal and metal silicide, and the first layer. And a third layer made of an alloy containing at least tungsten, silicon, and nitrogen, and the third layer is an impurity contained in the first layer. Is suppressed from spreading into the second layer.
[0043]
The semiconductor device manufacturing method includes a first step of depositing a polycrystalline silicon layer on a silicon substrate, and an alloy containing at least tungsten, silicon, and nitrogen on the polycrystalline silicon layer. A second step of forming an impurity diffusion suppression layer that suppresses impurity diffusion from the silicon layer; a third step of forming one of a metal and a metal silicide layer on the impurity diffusion suppression layer; And a step of patterning the laminated structure obtained by the first to third steps.
[0044]
According to the semiconductor device and the method for manufacturing the same, since the diffusion of impurities in the polycrystalline silicon into the metal or metal silicide can be suppressed in the polycide or polymetal structure electrode or wiring, the electrical characteristics are excellent. In addition, a highly reliable semiconductor device and a manufacturing method thereof can be obtained.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments will be described with reference to the drawings.
(First embodiment)
The present inventors made the following samples and evaluated them.
[0046]
First, as shown in FIG. 1A, Ar and N are formed on a single crystal silicon substrate 1 with W as a target. ₂ A tungsten nitride film 2 (film thickness of 5 nm) is deposited by a reactive sputtering method using as a sputtering gas. Subsequently, a tungsten film 3 (film thickness 100 nm) is deposited by sputtering.
[0047]
Next, as shown in FIG. ₂ / H ₂ / H ₂ The silicon substrate 1 is subjected to an oxidation treatment in a temperature range of 1000 ° C. for 30 minutes in an O atmosphere to form an oxide film 4 at the interface between the silicon substrate 1 and the tungsten nitride film 2. The partial pressure ratio in the oxidizing atmosphere is P (N ₂ ) / P (H ₂ ) / P (H ₂ O) = 0.9591 / 0.040 / 0.009 [atm].
[0048]
Finally, a tungsten film (W film) 3 and a tungsten nitride film (WN) _X The membrane 2 is peeled off with a mixed solution of sulfuric acid and hydrogen peroxide.
The W film 3 / WN at each oxidation temperature of the sample thus obtained _X The film thickness (oxide film thickness) of the oxide film 4 immediately below the film 2 was measured using an ellipsometry method.
[0049]
FIG. 2 shows the measurement results (white circles in the figure). In addition, as a comparative example, a measurement result (black circle in the figure) of the oxide film thickness when the silicon substrate 1 on which no surface is formed is oxidized under the same conditions is also shown. From FIG. 2, W film 3 / WN _X It can be seen that the sample on which the film 2 is formed has a considerably smaller oxide film thickness than the comparative example and is hardly oxidized at 800 ° C.
[0050]
As mentioned above, H ₂ / H ₂ There is a report example of oxidation in an O atmosphere applied to a W single layer metal gate (J. Electrochem. Soc., Vol 135, pp176 (1988)). According to the reporter of this paper, RFKwasnick et al., A thin silicon oxide film was formed on a silicon substrate and a W film was stacked on it. ₂ / H ₂ When oxidation is performed in an O atmosphere, the thin silicon oxide film immediately below the W film becomes thick. This is because the oxidizing agent diffuses through the grain boundary of the W film.
[0051]
Here, our experiment differs from this _X The film 2 is inserted between the W film 3 and the silicon substrate 1. WN _X The purpose of the film 2 is to prevent the reaction between the W film 3 and the silicon substrate 1. _X Most of the nitrogen in the film 2 is desorbed. Therefore, WN after the above heat treatment _X The film 2 is almost the same as the W film, and the function as a reaction preventing film is lowered.
[0052]
As a result of observing the interface (W / Si interface) between the W film 3 after the heat treatment and the silicon substrate 1 by the energy dispersive X-ray spectroscopy (EDX) method, the WN present immediately after the deposition _X It was found that the film 2 changed to a W film, and an ultrathin (about 10 angstrom) WSiN film was formed at the W / Si interface.
[0053]
The present inventors consider that this WSiN film functions as a reaction preventing layer for preventing the reaction between the W film 3 and the silicon substrate 1 (1994, 55th Japan Society of Applied Physics).
[0054]
Further, as a result of EDX analysis, it was found that the composition of the WSiN layer was W: Si = 1: 5 to 6 and the thickness was 1 nm or less. On the other hand, the ratio of W and N was, for example, W: N = 1: 1.
[0055]
In general, when a titanium nitride film is deposited on a Si substrate by a reactive sputtering method, N ₂ The surface of the Si substrate is nitrided by plasma discharge, and a silicon nitride film is formed immediately below the titanium nitride film in the film formation stage. Therefore, the same phenomenon occurs in the tungsten nitride film. In particular, in the case of a tungsten nitride film, if heat treatment is performed at 800 ° C. or higher even in a nitrogen atmosphere, N atoms in the film are desorbed and become a tungsten film. Therefore, in the first place, it is possible that the role of the barrier layer is not WSiN but an SiN film by plasma nitriding.
[0056]
Therefore, using a laminated sample of tungsten film / tungsten nitride film / silicon substrate, heat treatment is performed at 800 ° C. for 30 minutes in a nitrogen atmosphere, and then the tungsten film (and tungsten nitride film) is mixed with a mixed solution of sulfuric acid and oxygen peroxide water. ) Was evaluated using a photoelectron spectroscopy (XPS) method.
[0057]
The results are shown in FIG. 14. The solid line shows the narrow spectrum of W4f (FIG. 14 (a)) and Si2p (FIG. 14 (b)) obtained from the sample before the heat treatment and the dotted line after the heat treatment. About 2% of W was detected from either surface, but a large difference is seen in the binding state.
[0058]
First, in the spectrum of W4f, before the heat treatment, WO (peaks at 36 eV and 38 eV positions), metal bonds (peaks at 31 eV and 33 eV positions) and the like are mixed, which is a fairly broad peak. The metal bond peak is clearly seen after heat treatment. This metal bond is a peak of W-W bond or W-Si bond. From the result of the EDX analysis shown above, it is known that the composition of the WSiN layer is Si-rich. From this, it is considered that this metal bond is a W-Si bond.
[0059]
In addition, in the Si2p spectrum, excluding the Si—Si bond (99.6 eV) from the substrate, the Si—O bond (103.7 eV) is broader before the heat treatment, whereas the heat treatment is performed. In the latter case, a sharp Si—N bond (102 eV) peak is observed.
[0060]
That is, it can be said that the formation of the WSiN layer is due to the redistribution of nitrogen atoms in the tungsten nitride film accompanying the heat treatment, regardless of the plasma change during the formation of the tungsten nitride film.
[0061]
Thus, the formation of the WSiN film at the W / Si interface is _x This is considered to be due to redistribution of nitrogen in the film 2. The mechanism is summarized as follows.
[0062]
The Gibbs free energy drop when tungsten nitride is formed from tungsten is smaller than that when silicon nitride is formed from silicon. For this reason, WN _X When the film 2 and the silicon substrate 1 are in contact with each other, the chemical potential of nitrogen is smaller on the silicon substrate 1 side. As a result, WN _X Nitrogen in the film 2 moves (outward diffusion) to the silicon substrate 1 side. In this way, WN at the W / Si interface _X Nitrogen in the film 2 is segregated to form a WSiN film.
[0063]
Nitrogen segregated at the interface is combined with dangling bonds of silicon to form a Si—N bond layer. The surface density of nitrogen and silicon is about 5 × 10 ¹⁷ / Cm ² That was all. For this reason, it is considered that the movement of atoms between W / Si is suppressed. At this time, it is important that nitrogen can move relatively freely. This is because when the nitrogen contained in the metal has a strong bond with the metal, it cannot diffuse to the interface, so that segregation as described above does not occur.
[0064]
Therefore, this point should be noted when the WSiN film is formed in advance by film formation instead of the above-described formation method by redistribution of nitrogen. This is because, unlike tungsten nitride, nitrogen contained in the WSiN film has a Si—N bond and cannot move freely and cannot be redistributed at the W / Si interface.
[0065]
Therefore, when a WSiN film is used, redistribution of nitrogen at the W / Si interface cannot be expected. On the other hand, diffusion of oxygen atoms in the film must be suppressed. Therefore, the surface density of nitrogen and silicon is about 5 × 10 ¹⁷ / Cm ² It must be more than that.
[0066]
The reason why the oxidation of the W / Si interface was controlled simultaneously with the prevention of the reaction is considered to be that the WSiN film played a role of preventing the diffusion of the oxidizing agent. The reason is considered that the bonding force between Si and N is stronger than that between Si and O, and it is not easy to replace nitrogen and oxygen.
[0067]
From the above results, by adopting the structure in which the WSiN film is inserted, not only the reaction between the W film 3 and the silicon substrate 1 is prevented, but also the interface of the silicon substrate 1 to the interface between the W film 3 and the silicon substrate 1. It was found that oxidation was also suppressed.
[0068]
(Second Embodiment)
FIG. 3 is a process cross-sectional view showing stepwise a method of forming a gate electrode (polymetal gate) according to the second embodiment of the present invention.
[0069]
First, as shown in FIG. 3A, a thin silicon oxide film 11 (film thickness 5 nm) is formed as a gate oxide film on a single crystal silicon substrate 10, and chemical vapor deposition (CVD) is formed thereon. A polycrystalline silicon film 12 (film thickness 100 nm) is deposited by the method.
[0070]
Subsequently, a tungsten nitride film 13 (film thickness 5 nm) is deposited on the polycrystalline silicon film 12 by a reactive sputtering method. Subsequently, a tungsten film 14 (film thickness 100 nm) is deposited thereon by a sputtering method.
[0071]
Next, as shown in FIG. 3B, by performing a heat treatment at about 800 ° C., the nitrogen in the tungsten nitride film 13 is diffused outward, and the pole is formed at the interface between the tungsten film 14 and the polycrystalline silicon film 12. A thin WSiN film 15 is formed. At this time, the tungsten nitride film 13 becomes a tungsten film and is integrated with the tungsten film 14.
[0072]
Subsequently, a silicon nitride film 16 (film thickness 200 nm) is deposited on the tungsten film 14 by a CVD method. Note that the heat treatment may also serve as a film forming process of the silicon nitride film 16 having a film forming temperature of about 800 ° C.
[0073]
Further, after applying a photoresist (film thickness of 1 μm) on the silicon nitride film 16 by spin coating, the photoresist is exposed through a photomask and developed to form a photoresist pattern 17 having a width of, for example, 0.25 μm. To do.
[0074]
Next, as shown in FIG. 3C, after the silicon nitride film 16 is etched along the photoresist pattern 17 by using a dry etching apparatus, the remaining photoresist pattern 17 is replaced by O. ₂ Peel off by ashing.
[0075]
Next, as shown in FIG. 3D, the tungsten film 14, the WSiN film 15, and the polycrystalline silicon film 12 are etched using the silicon nitride film 16 as an etching mask.
[0076]
Next, as shown in FIG. 3E, in order to recover the gate oxide film 11 shaved during the etching of the polycrystalline silicon film 12 and to round the corner portion 18 of the polycrystalline silicon film 12, N ₂ / H ₂ / H ₂ Selective oxidation (post-oxidation) of silicon is performed in an O atmosphere. The oxidation condition is, for example, the partial pressure ratio P (N ₂ ) / P (H ₂ ) / P (H ₂ O) = 0.9951 / 0.040 / 0.009 [atm], oxidation temperature 800 ° C., oxidation time 30 minutes.
[0077]
By this selective oxidation, the gate oxide film 11 is restored to the original film thickness, and the corner portion 18 of the polycrystalline silicon film 12 (gate portion) is rounded as shown in the enlarged view of FIG. As a result, electric field concentration at the corner portion 18 of the gate electrode is avoided, and the reliability of the gate oxide film 11 is improved.
[0078]
At this time, as shown in FIG. 3 (f), the oxidant 20 enters the substrate 10 or the polycrystalline silicon film 12 in the direction of the arrow, but the WSiN between the tungsten film 14 and the polycrystalline silicon film 12. Since the film 15 prevents the diffusion of the oxidant 20, the oxidant 20 cannot enter from the upper surface of the silicon film 12 via the tungsten film 14.
[0079]
Therefore, since the polycrystalline silicon film 12 at the interface between the tungsten film 14 and the polycrystalline silicon film 12 is hardly oxidized, an increase in contact resistance can be prevented and RC delay can be suppressed.
[0080]
Since oxidant 20 diffuses from the side surface of polycrystalline silicon film 12, silicon oxide film 19 is selectively formed on the side surface of polycrystalline silicon film 12. This silicon oxide film 19 has a shape that bites into a bird's peak toward the center at the upper and lower sides of the side surface of the polycrystalline silicon film 12. Such a silicon oxide film 19 does not cause a problem such as RC delay.
[0081]
FIG. 4 shows a cross-sectional structure of a conventional gate portion in which the WSiN film 15 is not formed. As can be seen from FIG. 4, since the oxidant 20 also enters from the tungsten film 14 side, the polycrystalline silicon film 12 at the interface between the tungsten film 14 and the polycrystalline silicon film 12 is also oxidized. As a result, a silicon oxide film 19 is formed at the interface in addition to the side surface of the polycrystalline silicon film 12. Therefore, the contact resistance between the tungsten film 14 and the polycrystalline silicon film 12 increases, and the RC delay increases.
[0082]
Thus, according to the present embodiment, the WSiN film 15 as the anti-oxidation layer is inserted between the tungsten film 14 and the polycrystalline silicon film 12, so that N ₂ / H ₂ / H ₂ Even if selective oxidation (post-oxidation) is performed in an O atmosphere, the gate oxide film 12 can be recovered by selective oxidation of silicon without increasing the contact resistance between the tungsten film 14 and the polycrystalline silicon film 12. . Further, since the WSiN film 15 also functions as a reaction preventing film, the reaction between the tungsten film 14 and the polycrystalline silicon film 12 can be prevented.
[0083]
Thus, the advantage of using the tungsten film 14 which is a refractory metal can be sufficiently exerted, and a high-speed MOS transistor whose operation speed is not limited by the RC delay can be obtained even after the gate length of 0.25 μm generation.
[0084]
In the present embodiment, as a method of forming the WSiN film 15, the method of performing the heat treatment after forming the tungsten nitride film 13 by the reactive sputtering method has been described. However, the WSiN film is formed by the reactive sputtering from the beginning. ring It may be formed by a method.
[0085]
For example, WSi _X Ar gas and N ₂ Reactive sputtering using gas as sputtering gas ring By performing the above, the WSiN film 15 can also be formed.
[0086]
Further, the WSiN film 15 may be formed not only by the sputtering method but also by other film forming methods such as the CVD method. For example, WF as a source gas of N ₆ , WCl ₆ , WCl _Four Or W (CO) ₆ Gas and SiH as Si source gas _Four , SiH ₂ Cl ₂ Gas and NH as a source gas of N _Three Or N ₂ The WSiN film 15 may be formed using a mixed gas with gas.
[0087]
Next, a case where a titanium nitride film is used instead of the WSiN film will be described as a comparative example. First, as shown in FIG. 15A, a thin silicon oxide film 901 (film thickness 5 nm) is formed on a single crystal silicon substrate 900 by thermal oxidation, and a chemical vapor deposition (CVD) method is formed thereon. Thus, a polycrystalline silicon film 902 (film thickness 100 nm) is deposited.
[0088]
Furthermore, using Ti as a target, Ar and N ₂ As a sputtering gas, a titanium nitride film 903 (film thickness 10 nm) is deposited by a reactive sputtering method. A tungsten film 904 (film thickness 100 nm) is deposited thereon by sputtering.
[0089]
Thereafter, a silicon nitride film 905 (thickness: 200 nm) is deposited by a CVD method, a photoresist is applied thereon with a thickness of about 1 μm by a spin coating method, and exposed and developed to form a resist pattern 906 having a width of 0.15 μm. Form.
[0090]
Next, as shown in FIG. 15B, the silicon nitride film is etched using the resist pattern 906 as an etching mask. Thereafter, the remaining resist pattern 906 is removed using oxygen plasma ashing to obtain a mask pattern 905 made of a silicon nitride film.
[0091]
Thereafter, as shown in FIG. 15C, the tungsten film 904, the titanium nitride film 903, and the polycrystalline silicon film 902 are etched using the silicon nitride film 905 as an etching mask.
[0092]
Thereafter, as shown in FIG. 15D, N is used to recover the gate oxide film shaved during the electrode pattern formation and to round the corner portion 907 of the polycrystalline silicon film 902. ₂ / H ₂ / H ₂ Selective oxidation of silicon is performed in an O atmosphere. In this atmosphere, the side walls of the substrate silicon and the polycrystalline silicon film can be oxidized without oxidizing the tungsten film.
[0093]
However, the decrease in Gibbs free energy that occurs during the formation of oxides of titanium is lower than the decrease in Gibbs free energy that occurs during the formation of silicon oxides. Accordingly, it is thermodynamically impossible to selectively oxidize silicon without oxidizing the titanium nitride film containing titanium atoms.
[0094]
As shown in FIG. 16, since the oxidizing agent diffuses also in the tungsten film 904, the titanium nitride film 903 is oxidized not only on the side walls but also on the interface with the tungsten film 904 even if it has a laminated structure.
[0095]
Therefore, in the oxidation step, a titanium oxide layer 908 that is an insulator is formed between the refractory metal film and the polycrystalline silicon film, resulting in a significant increase in interface contact resistance. In the worst case, the refractory metal film is peeled off due to the expansion of the deposition accompanying the formation of the titanium oxide layer, so that the electrode does not function.
[0096]
In general, a titanium nitride film is used as a metal-silicon reaction preventing layer, a so-called barrier metal, but cannot be used in a semiconductor device that requires the oxidation step.
[0097]
Therefore, as a refractory metal, a value obtained by subtracting a Gibbs free energy decrease value generated when silicon forms an oxide from a Gibbs free energy decrease value generated when the oxide is formed is negative. Must be.
[0098]
(Third embodiment)
The present inventors made the following samples and evaluated them.
[0099]
That is, as shown in FIG. 5, a thin silicon oxide film 21 (film thickness 10 nm) is formed on a single crystal silicon substrate 20a, and a tungsten nitride film 22 (film thickness 5 nm) is deposited thereon by reactive sputtering. To do. Subsequently, a tungsten film 23 (film thickness 100 nm) is deposited by sputtering.
[0100]
Then N ₂ / H ₂ / H ₂ The silicon substrate 20a is subjected to an oxidation treatment for 30 minutes in a temperature range of 800 ° C. to 1000 ° C. in an O atmosphere. The partial pressure ratio of the oxidizing atmosphere is P (N ₂ ) / P (H ₂ ) / P (H ₂ O) = 0.9951 / 0.040 / 0.009 [atm].
[0101]
Finally, the tungsten film 23 and the tungsten nitride film 22 are peeled off with a mixed solution of sulfuric acid and hydrogen peroxide solution.
A laminated film (W film 23 / WN) of the tungsten film 23 and the tungsten nitride film 22 at each oxidation temperature of the sample thus obtained. _X Silicon oxide film (SiO2) directly under film 22) ₂ The film thickness of the film) 21 was measured using an ellipsometry method.
[0102]
FIG. 6 shows the measurement results (white circles in the figure). As a comparative example, WN is provided between the W film 22 and the silicon oxide film 21. _X The measurement result (black circle in the figure) of the oxide film 21 under the W film 23 when the silicon substrate 1 on which the film 22 is not formed is oxidized under the same conditions is also shown.
[0103]
6 from WN _X W film 23, W film 23 / WN with or without film 22 _X The film thickness of the oxide film 21 under the film 22 increases as the oxidation temperature rises, and the tendency is shown as WN. _X It can be seen that this is equivalent to the presence or absence of the film 22.
[0104]
Therefore, the oxidized W film 23 / WN _X Film 22 / SiO ₂ As a result of elemental analysis of the interface of the film 21 by the EDX method, it was found that the nitrogen concentration at the interface was low and the above-described WSiN film was not formed.
[0105]
Such a result can be explained from the nitrogen redistribution described above.
That is, the decrease in Gibbs free energy when tungsten nitride is formed from tungsten is smaller than that when silicon nitride is formed from silicon, but lower than that when silicon nitride is formed from silicon oxide. Is large, so SiO ₂ It is considered that the WSiN film was not formed on the film 21 and the diffusion of the oxidizing agent could not be suppressed.
[0106]
Therefore, a sample as shown in FIG. 7 was prepared. That is, a thin silicon oxide film 31 (film thickness 10 nm) is formed on a silicon substrate 30, a WSiN film 32 (film thickness 1 nm) is deposited thereon by reactive sputtering, and a W film is formed thereon by sputtering. 33 (film thickness 100 nm) was deposited to prepare another sample.
[0107]
Then N ₂ / H ₂ / H ₂ The sample was subjected to an oxidation treatment for 30 minutes in a temperature range of 800 to 1000 ° C. in an O atmosphere. The partial pressure ratio is the same as described above.
[0108]
Next, as in the case of the sample of FIG. 5, the thickness of the silicon oxide film 31 at each oxidation temperature of the sample thus obtained was examined.
FIG. 8 shows the measurement results with white circles. As a comparative example, the measurement result of the silicon oxide film 31 under the W film 23 when the silicon substrate 31 on which the WSiN film 32 is not formed is oxidized under the same conditions is also indicated by black circles.
[0109]
From FIG. 8, it can be seen that in the sample in which the WSiN film 32 / W film 23 is formed, the increase in the thickness of the silicon oxide film 31 is significantly suppressed as compared with the comparative example. That is, by forming the WSiN film 32, it becomes possible to supplement the diffusion preventing function accompanying the redistribution of nitrogen.
[0110]
From the above results, the WSiN film 32 is extremely effective as an anti-oxidation layer. By adopting a structure in which the WSiN film is interposed between the W film 23 and the thin silicon oxide film 31, a silicon oxide film by post-oxidation is used. It can be seen that the film thickness increase of 31 can be effectively prevented.
[0111]
(Fourth embodiment)
FIG. 9 is a process cross-sectional view showing stepwise a method of forming a gate electrode (metal gate) according to the fourth embodiment of the present invention.
[0112]
First, as shown in FIG. 9A, a thin silicon oxide film 41 (film thickness 4 nm) is formed as a gate oxide film on a single crystal silicon substrate 40, and a WSiN film 42 is formed thereon by reactive sputtering. (Film thickness 1 nm) is deposited.
[0113]
Subsequently, after a tungsten film 43 (film thickness 100 nm) is deposited on the WSiN film 42 by sputtering, a silicon nitride film 44 (film thickness 200 nm) is deposited thereon by CVD.
[0114]
Further, after applying a photoresist (film thickness of 1 μm) on the silicon nitride film 44 by spin coating, the photoresist is exposed through a photomask and developed to form, for example, a photoresist pattern 45 having a width of 0.15 μm. To do.
[0115]
Next, as shown in FIG. 9B, after the silicon nitride film 44 is etched along the resist pattern 45 by using a dry etching apparatus, the remaining photoresist pattern 45 is replaced by O. ₂ Peel off by ashing.
[0116]
Next, as shown in FIG. 9C, the tungsten film 43 and the WSiN film 42 are etched using the silicon nitride film 44 as an etching mask.
[0117]
Next, as shown in FIG. 9D, in order to recover the thin silicon oxide film 41 other than the gate part shaved during the etching of the tungsten film 43 and the WSiN film 42, N ₂ / H ₂ / H ₂ Selective oxidation (post-oxidation) of silicon is performed in an O atmosphere.
[0118]
The oxidation condition is, for example, the partial pressure ratio P (N ₂ ) / P (H ₂ ) / P (H ₂ O) = 0.9951 / 0.040 / 0.009 [atm], oxidation temperature 800 ° C., oxidation time 30 minutes. At this time, since the WSiN film 42 between the tungsten film 43 and the thin silicon oxide film 41 prevents diffusion of the oxidant, the oxidant cannot enter from the tungsten film 43 side. Therefore, the silicon oxide film 41, which is a gate oxide film located under the tungsten film 43, is hardly oxidized and the film thickness does not increase. Therefore, the driving capability is not reduced due to the increase in the gate oxide film thickness.
[0119]
As shown in FIG. 9E, the oxidant 46 diffuses from the side surface of the silicon oxide film 41 located under the tungsten film 43. The film 41 has a shape that bites into a bird's peak toward the center of the gate portion, but there is no problem in characteristics.
[0120]
(Fifth embodiment)
FIG. 10 is a cross-sectional view showing stepwise a method of forming a gate electrode (polymetal gate) according to the fifth embodiment of the present invention.
[0121]
This embodiment is mainly different from the first to fourth embodiments in that carbon is used in place of nitrogen, which is one of the materials of the antioxidant film. That is, the antioxidant film of this embodiment is formed of carbon, silicon, and a refractory metal.
[0122]
First, as shown in FIG. 10A, a thin silicon oxide film 51 (film thickness 5 nm) is formed as a gate oxide film on a single crystal silicon substrate 50, and a polycrystalline silicon film 52 is formed thereon by CVD. (Film thickness 100 nm) is deposited.
[0123]
Subsequently, on the polycrystalline silicon film 52, for example, WSi. _X Targeting Ar gas and CH _Four Using a gas as a sputtering gas, a WSiC film 53 (film thickness 2 nm) is deposited by reactive sputtering, and subsequently a tungsten film 54 (film thickness 100 nm) is deposited thereon by sputtering, followed by CVD. A silicon nitride film 55 (film thickness 200 nm) is deposited by the method.
[0124]
Further, after applying a photoresist (film thickness of 1 μm) on the silicon nitride film 55 by spin coating, the photoresist is exposed through a photomask and developed to form a photoresist pattern 56 having a width of, for example, 0.25 μm. To do.
[0125]
Next, as shown in FIG. 10B, after the silicon nitride film 55 is etched along the photoresist pattern 56 by using a dry etching apparatus, the remaining photoresist pattern 56 is replaced by O. ₂ Peel off by ashing.
[0126]
Next, as shown in FIG. 10C, the tungsten film 54, the WSiC layer 53, and the polycrystalline silicon film 52 are etched using the silicon nitride film 55 as an etching mask.
[0127]
Next, as shown in FIG. 10D, in order to recover the gate oxide film 51 shaved during the etching of the polycrystalline silicon film 52 and oxidize the corners of the polycrystalline silicon film 52, N ₂ / H ₂ / H ₂ Selective oxidation (post-oxidation) of silicon is performed in an O atmosphere.
[0128]
The oxidation condition is, for example, the partial pressure ratio P (N ₂ ) / P (H ₂ ) / P (H ₂ O) = 0.9951 / 0.040 / 0.009 [atm], oxidation temperature 800 ° C., oxidation time 30 minutes.
[0129]
By this selective oxidation, the gate oxide film 51 is restored to its original film thickness, and the corner portion of the polycrystalline silicon film is rounded by the oxide film 57. As a result, electric field concentration at the corner portion of the gate electrode is avoided, and the reliability of the gate oxide film 51 is improved.
[0130]
At this time, as in the case of the first embodiment, the WSiC film 53 between the tungsten film 54 and the polycrystalline silicon film 52 prevents the oxidant from diffusing, so that the oxidant enters from the tungsten film 54 side. I can't do it.
[0131]
Therefore, since the polycrystalline silicon film 52 at the interface between the tungsten film 54 and the polycrystalline silicon film 52 is hardly oxidized, an increase in contact resistance can be prevented and RC delay can be suppressed. In addition, the same effect as the first embodiment can be obtained in this embodiment.
[0132]
Since the oxidizing agent diffuses from the side wall of the polycrystalline silicon film 52, the silicon oxide film 57 is selectively formed on the side surface of the polycrystalline silicon film 52. The silicon oxide film 57 has a shape that bites into a bird's peak toward the center at the upper and lower side surfaces of the polycrystalline silicon film 52.
[0133]
In this embodiment, as a method for forming the WSiC layer, WSi _X Reactive sputtering method was used, but Ar gas and CH were selected using W as the target. _Four The WSiC film 53 may be formed by depositing a tungsten carbide (WC) film by a reactive sputtering method using a gas as a sputtering gas and then performing a heat treatment.
[0134]
The film forming method is not limited to the sputtering method, and the WSiC layer 53 may be formed by a CVD method. For example, WF ₆ And SiH _Four And CH _Four The WSiC layer 53 may be formed using a gas. Furthermore, in the reactive sputtering method and the CVD method, as a carbon-based gas, CH _Four Choose gas, but C ₂ H ₉ , C _Three H ₈ , C ₂ H ₂ Etc.
[0135]
(Sixth embodiment)
11 and 12 are process cross-sectional views showing stepwise a method of forming a field effect transistor (MOSFET) according to the sixth embodiment of the present invention.
[0136]
First, as shown in FIG. 11A, an element isolation insulating film 61 is formed on the surface of a single crystal silicon substrate 60 to perform element isolation. Next, after forming a gate oxide film 62 (film thickness 5 nm) on the surface of the silicon substrate 60 surrounded by the element isolation insulating film 61, a polycrystalline silicon film 63 (film thickness 100 nm) is formed thereon by CVD. .
[0137]
Subsequently, a tungsten nitride film 64 (film thickness of 5 nm) is formed on the polycrystalline silicon film 63 by reactive sputtering, and then a tungsten film 65 (film thickness of 100 nm) is formed on the tungsten nitride film 64 by reactive sputtering. Form.
[0138]
Next, as shown in FIG. 11B, a heat treatment at about 800 ° C. is performed to form an extremely thin WSiN layer 66 at the interface between the tungsten film 65 and the polycrystalline silicon film 63. Next, a silicon nitride film 67 (thickness: 200 nm) is formed on the tungsten film 65 by CVD. Since the film formation temperature of this silicon nitride film 67 is about 800 ° C., the above heat treatment may be performed in this film formation step without performing the heat treatment in advance.
[0139]
Next, after applying a photoresist (film thickness: 1 μm) on the silicon nitride film 67 by spin coating, the photoresist is exposed through a photomask and developed to form a resist pattern 68 having a width of, for example, 0.25 μm. .
[0140]
Next, as shown in FIG. 11C, the silicon nitride film 67 is etched along the resist pattern 68 using a dry etching apparatus. Thereafter, the remaining resist pattern 68 is set to 0. ₂ Peel off by ashing. Subsequently, using the silicon nitride film 67 as an etching mask, the tungsten film 65, the WSiN layer 66, and the polycrystalline silicon film 63 are sequentially etched.
[0141]
Next, as shown in FIG. 11D, a corner portion 69 at the bottom of the polycrystalline silicon film 63 is used to recover the thickness of the thin gate oxide film 62 shaved during the etching of the polycrystalline silicon film 63. N to round ₂ / H ₂ / H ₂ Selective oxidation of silicon is performed in a temperature range of 700 to 900 ° C. while controlling each gas partial pressure in an O atmosphere. Due to this oxidation, only silicon is oxidized, and the corner portion 69 is rounded, so that it is possible to prevent a decrease in the reliability of the FET due to the concentration of the electric field in this portion.
[0142]
After this oxidation, no oxide film is formed or grown near the interface between the polycrystalline silicon film 63 and the tungsten film 65, and the WSiN layer 66 prevents inward diffusion of the oxidizing agent from the external atmosphere. It was confirmed that
[0143]
A similar effect is N ₂ / H ₂ / H ₂ Not only in O atmosphere, but also in trace oxygen, trace water vapor or H ₂ And O ₂ Mixed gas atmosphere and CO and CO ₂ It was also confirmed in a mixed gas atmosphere.
[0144]
Next, as shown in FIG. 11E, after a shallow impurity diffusion layer (source / drain diffusion layer) 70 is formed by ion implantation or the like, a silicon nitride film 71 is formed as a sidewall insulating film. As a result, since the tungsten film 65 is surrounded by the silicon nitride films 67 and 71, the tungsten film 65 is not oxidized even when exposed to an oxidizing atmosphere, for example. The tungsten film 65 is a substance that is soluble in a solution such as hydrogen peroxide. However, by adopting this structure, the intrusion of the solution can be prevented.
[0145]
Next, as shown in FIG. 12A, after forming a deep impurity diffusion layer (source / drain diffusion layer) 72 by ion implantation or the like, a metal silicide layer 73 is formed on the impurity diffusion layer 72.
[0146]
Next, as shown in FIG. 12B, after an interlayer insulating film 74 is formed on the entire surface, the surface of the interlayer insulating film 74 is flattened by a chemical mechanical polishing (CMP) method or the like. Next, after applying a photoresist (film thickness of 1 μm) to the interlayer insulating film 74 by spin coating, the photoresist is exposed through a photomask and developed to form a resist pattern 75 having a hole diameter of 0.3 μm, for example.
[0147]
Next, as shown in FIG. 12C, using a dry etching apparatus, the resist pattern 75 is used as an etching mask, the interlayer insulating film 74 is etched, a contact hole is opened, and then the resist pattern 75 is peeled off. To do. The etching conditions at this time are, for example, a power density of 2.0 W / cm. ² , Pressure 40mTorr, flow rate C _Four F _Three / CO / Ar = 10/100/200 SCCM.
[0148]
In this case, the interlayer insulating film 74 is etched at about 400 nm / min, while the silicon nitride films 67 and 71 are etched at about 10 nm / min. Therefore, the interlayer insulating film 74 is selected with respect to the silicon nitride films 67 and 71. The ratio is about 40.
[0149]
Therefore, in the step of forming resist pattern 75, even if a part of the hole is applied to the gate electrode having a laminated structure composed of tungsten film 65, WSiN film 66 and polycrystalline silicon film 63, silicon nitride films 67 and 71 are not etched. Therefore, a contact hole for the impurity diffusion layer 72 can be formed without inviting the gate electrode to be exposed. Accordingly, the margin of positional accuracy of the resist pattern 75 is widened.
[0150]
Next, as shown in FIG. 12D, a tungsten film 77 is selectively formed in the contact hole by using a film forming method such as a selective CVD method. At this time, since the silicon nitride films 67 and 71 cover the gate electrode, the impurity diffusion layer 72 and the gate electrode are in electrical contact, and no leakage current flows.
[0151]
As described above, according to the present embodiment, since the gate electrode 76 employs a structure surrounded by the silicon nitride films 67 and 71, even if the position of the resist pattern 75 is shifted to the gate electrode 76 side, A leakage current does not flow between the impurity diffusion layer 72 and the gate electrode 76, and the alignment margin of the resist pattern 75 is widened.
[0152]
On the other hand, in the conventional MOSFET, the width of the impurity diffusion layer 72 is widened and the position of the resist pattern 75 is separated from the gate electrode 76 as much as possible to prevent deterioration of transistor characteristics due to the shift of the resist pattern 75. The size of the MOSFET inevitably increases. That is, if a structure in which the gate electrode 76 is surrounded by the silicon nitride films 67 and 71 as in this embodiment is adopted, the element size can be reduced as compared with the conventional case.
[0153]
(Seventh embodiment)
FIG. 13 is a process cross-sectional view showing stepwise a method of forming an EEPROM field effect transistor (MOSFET) according to the seventh embodiment of the present invention.
[0154]
First, as shown in FIG. 13A, a tunnel oxide film 81 (film thickness: 5 nm) is formed on a substrate 80 made of single crystal silicon, and polycrystalline silicon is formed thereon by chemical vapor deposition (CVD). A film 82 (film thickness 300 nm) is deposited.
[0155]
Next, ONO (Oxide Nitride) is formed on the polycrystalline silicon film 82 by CVD.
Oxide) film 83 (film thickness 16 nm) is deposited, WSiN film 84 (film thickness 2 nm) is deposited thereon by reactive sputtering, and then tungsten film 85 (film thickness 100 nm) is deposited thereon by sputtering. To deposit.
[0156]
Next, as shown in FIG. 13B, a silicon nitride film 86 (thickness: 200 nm) is deposited on the tungsten film 85 by CVD, and then a photoresist (thickness: 1 μm) is spun on the silicon nitride film 86. It is applied by a coating method, this photoresist is exposed through a photomask, and developed to form a resist pattern 87 having a width of, for example, 0.25 μm.
[0157]
Next, as shown in FIG. 13C, after the silicon nitride film 86 is etched along the resist pattern 87 by using a dry etching apparatus, the remaining resist pattern 87 is replaced by O. ₂ Peel off by ashing. Next, using the silicon nitride film 86 as an etching mask, the tungsten (W) 85, the WSiN layer 84, the ONO layer 83, and the polycrystalline silicon film 82 are etched.
[0158]
Next, as shown in FIG. ₂ / H ₂ / H ₂ The silicon is selectively oxidized at 700 to 900 ° C. while controlling each gas partial pressure in an O atmosphere. This is to recover the film thickness of the tunnel silicon oxide film 81 shaved during the etching of the polycrystalline silicon film 82 and round the corner portion 88 at the bottom of the polycrystalline silicon. By this oxidation, only silicon is oxidized, and it is possible to prevent a decrease in reliability due to electric field concentration in the bottom corner portion.
[0159]
After this oxidation, the upper portion of the polycrystalline silicon 82 is not oxidized or the ONO film 83 is not increased in thickness, and the WSiN layer 84 prevents inward diffusion of the oxidizing agent from the external atmosphere. It was confirmed.
[0160]
A similar effect is N ₂ / H ₂ / H ₂ Not only in O atmosphere, but also in trace oxygen, trace water vapor or H ₂ And O ₂ Mixed gas atmosphere and CO and CO ₂ It was also confirmed in the mixed gas atmosphere.
[0161]
In a transistor used for an EEPROM, an ONO film between a control gate electrode (tungsten film 85) and a floating gate electrode (polycrystalline silicon film 82) is used as an insulating film for charge storage. Therefore, the film thickness of the ONO film defines the storage capacity, and the storage capacity decreases as the film thickness increases.
[0162]
Here, according to the present embodiment, it is possible to prevent the ONO film thickness from increasing by disposing the antioxidant film on the ONO film. Therefore, the reliability of the tunnel oxide film can be improved without deteriorating the transistor characteristics.
[0163]
In this embodiment, the ONO film formed by the CVD method is used as the charge storage insulating film, but it may be formed by heat treatment in an atmosphere containing oxygen and nitrogen atoms. Further, it may be formed by a combination of CVD and heat treatment.
[0164]
In addition, this invention is not limited to embodiment mentioned above. For example, in the above embodiment, the case where tungsten is used as the refractory metal contained in the anti-oxidation film has been described. However, from the decrease in Gibbs free energy generated when forming a nitride of a high melting point, silicon is used. A similar effect can be obtained if the refractory metal has a negative value obtained by subtracting the decrease in Gibbs free energy generated when forming the nitride. Specifically, Mo, Cr, Co Etc.
[0165]
Further, the antioxidant layer may contain both nitrogen and carbon.
[0166]
In the above-described embodiments, the case of the gate electrode has been described. However, the present invention can be applied to other electrodes and further to wiring. In particular, the present invention is preferably applied to a wiring having a remarkable RC delay such as a word wiring. The present invention can also be applied to elements other than MOS transistors.
[0167]
In the above, in the polymetal gate and the metal gate to which the silicon selective oxidation technology is applied, the gate structure capable of suppressing the RC delay due to the undesired oxidation of silicon and the manufacturing method thereof have been described. In the following embodiments, a gate structure for preventing impurities in silicon from thermally diffusing into a refractory metal or refractory metal silicide in a stacked gate structure such as polycide or polymetal will be described.
[0168]
(Eighth embodiment)
17 and 18 are data of secondary ion mass spectrometry showing the effect of preventing impurity diffusion in the multilayer structure sample according to the eighth embodiment of the present invention. The thickness of each layer of the sample having a multilayer structure is shown by providing a scale corresponding to the horizontal axis in the drawing at the top of FIG.
[0169]
That is, a 100 nm thick SiO2 film on a silicon substrate (not shown on the scale) ₂ A layer is grown, and then As or B (boron) is added as an impurity at a concentration of 1 × 10 ²⁰ / Cm ² The included polycrystalline silicon layer was grown to a thickness of 100 nm. Furthermore, Ar and N with a mixing ratio of 1: 1 ₂ In the mixed gas atmosphere, W is deposited by using a reactive sputtering method for sputtering a W target, or WSi is used. _x By depositing the target (x = 2 to 3) using the reactive sputtering method in the mixed gas atmosphere, WSi having a thickness of 5 nm is used. _x N _y A diffusion barrier layer consisting of was deposited. Subsequently, W was deposited to a thickness of 100 nm on the uppermost layer using a sputtering method, and a multilayer structure sample in the eighth example was prepared.
[0170]
In order to evaluate the impurity diffusion effect in a sample having a polycrystalline silicon layer containing As, the depth direction of impurities when this sample is heat-treated at 800 ° C. for 30 minutes or 950 ° C. for 30 minutes in an N 2 atmosphere. The distribution of is shown in FIG. The analysis result of FIG. 17A will be described in detail as follows.
[0171]
In secondary ion mass spectrometry, a multi-layer sample is irradiated with a primary ion beam for etching, and the secondary ions released at this time are subjected to mass analysis to determine the material composition. In this way, the relationship between the etching depth and the composition is obtained. The horizontal axis in FIG. 17A represents the etching depth, which corresponds to the cumulative value of the thickness of each layer of the multilayer structure sample. The vertical axis represents the intensity of the detected secondary ions.
[0172]
As shown in FIG. 17A, after heat treatment at 800 ° C. for 30 minutes, W + N and Si were observed in addition to W in the range of 100 nm on the surface of the sample made of the W layer. Is WSi at the interface between W and the polycrystalline silicon. _x N _y Since the presence of the diffusion preventing layer exists, it was found that the diffusion to W was sufficiently suppressed except for the surface portion. In FIG. 17A, the polycrystalline silicon layer, SiO ₂ Although it seems that W, W + N, etc. exist also in a layer, this is an appearance by the tailing | etching of the etching shape by a primary ion beam.
[0173]
If pure W is formed on the uppermost layer of the multilayer structure, the resistance value of the multilayer structure can be reduced. However, when impurities diffuse here, gate depletion due to a decrease in the impurity concentration in Si under the W or CMOS (complementary) This causes impurity interdiffusion between n and p regions in the type MOS). Since W, Si, and N form a stable compound, even if these elements are introduced into W to the extent shown in FIG. 17 (a), they do not cause an increase in resistance and may cause film quality deterioration. Absent. Therefore, 5 nm thick WSi _x N _y It has been found that if a diffusion preventing layer is interposed, it greatly helps to improve the reliability of the multilayer structure.
[0174]
The analysis result when the same sample is heat-treated at 950 ° C. for 30 minutes is shown in FIG. Compared to FIG. 17A, the amount of As in W increased by about one digit, but the concentration of As in W converted from this result was 1 × 10. ¹⁸ / Cm ^Three In the usual LSI thermal process, the WSi _x N _y It could be considered that the diffusion preventing effect of the layer was sufficient.
[0175]
FIG. 18 shows the analysis result when B is included as an impurity in the polycrystalline silicon layer. It was found that the diffusion of B into W during heat treatment at 800 ° C. and 950 ° C. for 30 minutes was so small that it could be ignored in practice. Moreover, it turned out that the same effect is acquired also with respect to donor and acceptor impurities other than said As and B added in the polycrystalline silicon.
[0176]
(Ninth embodiment)
Next, a ninth embodiment of the present invention will be described with reference to FIG. FIG. 19A to FIG. 19C are cross-sectional views showing a method for manufacturing a semiconductor device using the multilayer structure of the present invention.
[0177]
As shown in FIG. 19A, p-type region 502 having a depth of about 1 μm is formed by ion implantation of B into silicon substrate 501 and subsequent thermal diffusion. Next, after an element isolation oxide film 503 having a thickness of about 600 nm is formed in a predetermined region, a protective oxide film 504 having a thickness of about 10 nm is formed, and ion implantation for adjusting the threshold value of the MOSFET is performed (shaded portion 505). ).
[0178]
Next, as shown in FIG. 19B, after the protective oxide film 504 is peeled off, oxidation of several nm to several tens of nm is performed again to form a gate oxide film 506.
[0179]
Subsequently, amorphous silicon is deposited to a thickness of 100 nm by CVD, and P (phosphorus) is introduced into the amorphous silicon by ion implantation. In addition to ion implantation, the impurity element may be introduced by diffusion from a gas phase or a solid phase. In either case, the impurity concentration is about 2 × 10 ²⁰ / Cm ^Three That's it. The activation heat treatment of P ion-implanted into amorphous silicon is performed at 800 ° C. for 30 minutes. By this heat treatment, the amorphous silicon is changed to polycrystalline silicon 507.
[0180]
Next, a natural oxide film formed on the polycrystalline silicon 507 is removed by dilute hydrofluoric acid treatment, and then Ar and N are used using a W target. ₂ WSi with a film thickness of about 5 nm by reactive sputtering in a mixed gas of _x N _y A film 508 is formed. Subsequently, reactive sputtering is performed in an Ar atmosphere using a W target, or WF ₆ , SiH _Four A W film 509 having a thickness of about 100 nm is formed by a CVD method using a gas.
[0181]
Next, SiH ₂ Cl ₂ , NH _Three SiN with a thickness of about 250 nm by LP (Low Pressure) CVD method using a gas at a growth temperature of 800 ° C. for 30 minutes _x A film 510 is formed.
[0182]
This SiN for about 30 minutes at 800 ° C _x Conventionally, impurities contained in polycrystalline silicon diffused into W due to the film formation process, which has become a problem. _x N _y By using the film 508, impurity diffusion from the polycrystalline silicon film 507 to the W film 509 can be suppressed.
[0183]
Next, a desired gate electrode or wiring pattern is formed using a resist, and this is used as a mask to form SiN. _x The film 510 is removed using an RIE method, and the SiN _x W film 509, WSi using film as mask _x N _y The film 508 and the polycrystalline silicon film 507 are patterned using the RIE method to form a gate electrode or wiring having a multilayer structure.
[0184]
Next, H ₂ O, H ₂ , N ₂ By performing selective oxidation at 800 ° C. for 30 minutes in an atmosphere, an oxide film 511 shown in FIG. 19C is formed. Only silicon can be oxidized without oxidizing W by selective oxidation, and an oxide film can be formed on the surface of the silicon substrate and the side surface of the polycrystalline silicon of the gate electrode.
[0185]
Next, in the source / drain region, an acceleration voltage of 20 keV and a dose of 5 × 10 ¹⁴ / Cm ² Under the conditions, As is ion-implanted shallowly to form an LDD (Lightly Doped Drain) region 512. Subsequently, SiN having a thickness of about 50 nm is formed on the gate electrode. _x Then, anisotropic etching is performed using the RIE method to form SiN on the gate sidewall as shown in FIG. _x A gate structure in which the film 513 is formed is obtained. The acceleration voltage of 60 keV and the dose of 7 × 10 are formed on the gate having the side wall as described above. ¹⁵ / Cm ² The source / drain regions 514 are formed by deep ion implantation of As.
[0186]
In order to activate the injected As, N ₂ After performing heat treatment at a temperature of 900 ° C. for 30 seconds in the atmosphere, the interlayer insulating film is formed, Al contact, wiring, and the like are performed by a normal method. _x N _y A MOSFET having a self-aligned gate structure with a sidewall insulating film, which includes a gate electrode having a diffusion prevention layer, can be obtained.
[0187]
According to the method of the present invention, the 800 ° C., 30-minute selective oxidation treatment performed after the formation of the multilayer metal gate, the high-temperature heat treatment for As impurity activation, and the interlayer film formation using the CVD method are performed at 800 ° C. for about 1 hour. Even in the thermal process, 2 × 10 2 is applied to the polycrystalline silicon film 507 constituting the multilayer metal gate. ²⁰ / Cm ^Three Therefore, a MOSFET having a low-resistance and high-reliability gate electrode can be obtained.
[0188]
(Tenth embodiment)
Next, a tenth embodiment of the present invention will be described with reference to FIG. As shown in FIG. 20A, p-type region 602 having a depth of about 1 μm is formed by ion implantation of B into silicon substrate 601 and thermal diffusion. An element isolation oxide film 603 having a thickness of about 600 nm is formed in a predetermined region, a protective oxide film (not shown) is formed, and then ion implantation for adjusting the threshold value of the MOSFET is performed (shaded portion 605).
[0189]
After peeling off the protective oxide film, oxidation with a thickness of about 10 nm is performed again to form a tunnel oxide film 615. Subsequently, the oxide film 615 has NH. _Three Nitriding is performed at 1000 ° C. for about 30 seconds in an atmosphere, and then re-oxidation is performed at 1000 ° C. for about 30 seconds. The nitriding and re-oxidation treatment has an effect of reducing the interface state of the tunnel oxide film and the traps in the oxide film.
[0190]
Next, a polycrystalline silicon film 616 is deposited to about 200 nm, and POCl. _Three P is introduced into the polycrystalline silicon by performing a heat treatment at 850 ° C. for 30 minutes.
Next, an oxide film 617 having a thickness of about 10 nm is formed on the polycrystalline silicon by thermal oxidation, and subsequently SiN having a thickness of about 10 nm is formed by LPCVD. _x After forming the film 618, the SiN _x The film surface is oxidized at 900 ° C. for 30 minutes to form an oxide film 619. A polycrystalline silicon film 607 having a thickness of 100 nm is deposited thereon, and POCl. _Three P is introduced into the polycrystalline silicon 607 by performing a heat treatment at 850 ° C. for 60 minutes in an atmosphere.
[0191]
Thereafter, WSi is formed on the polycrystalline silicon 607 through the same process as in the ninth embodiment. _x N _y Film 608, W film 609, SiN _x A film 610 is deposited as shown in FIG. 20A, and a multi-layered gate electrode is formed on the tunnel oxide film 615 using a resist pattern as shown in FIG.
[0192]
In the source / drain region, As is accelerated by 60 keV and the dose is about 1 × 10. ¹⁶ / Cm ² After the ion implantation, a heat treatment is performed at 900 ° C. for 30 minutes to activate the implanted impurities. After that, by forming an interlayer film and forming an Al wiring or the like, a control gate (607- 610), a nonvolatile memory MOSFET device can be obtained.
[0193]
Thus, the control gate has WSi _x N _y By interposing the film 608, the heat resistance of the gate electrode is remarkably improved with respect to the thermal process after the formation of the control gate, and a highly reliable nonvolatile memory MOSFET element can be obtained.
[0194]
(Eleventh embodiment)
Next, an eleventh embodiment of the present invention will be described with reference to FIG. This example is a modification of the tenth embodiment, and the WSi _x N _y After forming the film 608, the W film 609 is replaced with WSi. _x A film 621 is formed. WSi _x N _y Since the steps up to the formation of the film 608 are the same as those in the fifteenth embodiment, the description thereof is omitted. WSi _x The film 621 is W _Five Si _Three Sputtering in an Ar atmosphere using as a target or WF ₆ , SiH _Four Is deposited to a thickness of about 300 nm by a CVD method using as a source gas.
[0195]
After patterning using a resist, the silicon film 616 is selectively oxidized, and an acceleration energy of 60 keV and a dose of 5 × 10 are applied to the source / drain regions. ¹⁵ / Cm ² As ions are implanted under the following conditions. Continuing to activate the implanted impurities, O ₂ Oxidation is performed at 900 ° C. for about 60 minutes in an atmosphere. The amount of oxidation at this time is appropriately determined according to the magnitude of the breakdown voltage required for the gate.
[0196]
In this oxidation treatment step, WSi increases the oxidation rate due to the As ion implantation. _x The consumption of Si in the film 621 increases, and the Si from the underlying polycrystalline silicon film 607 becomes WSi. _x The film 621 is supplied. For this reason, WSi _x The interface between the film 621 and the polycrystalline silicon film 607 is WSi. _x It has been found that it has been invaded into the polycrystalline silicon, which causes breakdown voltage degradation.
[0197]
According to the present invention, the polycrystalline silicon film 607 and the WSi _x Between the film 621 and WSi _x N _y By forming the diffusion preventing film 608, impurities contained in the polycrystalline silicon at a high concentration during the oxidation treatment step are changed into WSi. _x At the same time, diffusion into the film 621 is prevented, and at the same time, the underlying polycrystalline silicon film 607 forms a WSi film. _x Since the absorption of Si into the film 621 is suppressed, no deterioration in pressure resistance was observed.
[0198]
Next, a highly reliable nonvolatile memory MOSFET element can be obtained by performing an interlayer insulating film and Al wiring or the like.
[0199]
(Twelfth embodiment)
FIG. 22 is a sectional view showing the structure of a complementary MOSFET (CMOSFET) according to the twelfth embodiment of the present invention. Each MOSFET has a stacked gate structure including a silicon film 707 or 707 ′ and a W film 709.
[0200]
As described above, a laminated structure such as polycide or polymetal is susceptible to heat in a thermal process, and has a drawback that impurities in silicon diffuse into a refractory metal or silicide by thermal diffusion. Due to such diffusion, the impurity concentration in silicon is reduced, and when a gate voltage is applied to the inversion side, a depletion layer 802 ′ appears in the gate silicon 802 as shown in FIG. Reduce driving ability. This phenomenon is known as gate depletion. 23A shows a state in which no gate voltage is applied. Reference numeral 801 denotes a silicon substrate, 806 denotes a gate insulating film, 802 denotes a silicon film, 804 denotes a W film, and 805 denotes a source / drain region.
[0201]
Further, when the above laminated structure is used for the CMOSFET, as schematically shown in FIGS. 24A and 24B, impurities diffused in the refractory metal (or silicide) 804 (indicated by an arrow 810) are present. There is a problem that the threshold voltage changes by changing the work function of the gate by mutually diffusing the p-type and n-type regions. This phenomenon is a problem generally called impurity interdiffusion in CMOS.
[0202]
The present embodiment is an embodiment that provides a configuration for suppressing the above-described impurity interdiffusion. The present embodiment will be described in accordance with the manufacturing process shown in FIGS.
[0203]
First, a resist pattern is formed in a predetermined region using a photolithography technique, and B, Ga, or In is ion-implanted into a silicon substrate using the resist pattern as a mask. Similarly, ions of P, As, or Sb are implanted into a predetermined region. Subsequently, thermal diffusion is performed to form a p-type region 722 and an n-type region 722 ′ having a depth of about 1 μm (FIG. 25).
[0204]
Next, an element isolation oxide film 703 having a thickness of 600 nm is formed in a predetermined region (FIG. 26A).
Next, after forming a protective oxide film having a thickness of about 10 nm, ion implantation for adjusting the threshold value of the MOSFET is performed, and after removing the protective oxide film, a gate oxide film 706 having a thickness of about 10 nm is formed again (FIG. 26 ( b)). Subsequently, a silicon film 707 having a thickness of about 100 nm is deposited. At this time, the silicon 707 may be amorphous or polycrystalline, or may be a single crystal formed by lateral epitaxial growth in partial contact with the silicon substrate.
[0205]
An n-type impurity such as P, As, or Sb is ion-implanted into the gate formation region of the silicon film 707 on the p-type region 722 using a resist as a mask. ⁺ And Similarly, p-type impurities such as B, Ga and In are ion-implanted into the gate formation region of the silicon film 707 ′ on 722 ′ using a resist as a mask. ⁺ And Diffusion from the gas phase or solid phase may be used to introduce the impurity element into the gate region, but the impurity concentration is 2 × 10 6 in any case. ²⁰ / Cm ^Three This is done (FIG. 26 (c)).
[0206]
Next, after removing the natural oxide film formed on the surfaces of the silicon films 707 and 707 ′ during the process by, for example, dilute hydrofluoric acid treatment, W _Five Si _Three Sputtering in an Ar atmosphere using a target of WF or WF ₆ And SiH _Four WSi with a thickness of 10 nm or less by using the system LPCVD method _x A film 723 is formed (FIG. 27A). This WSi _x The film 723 is formed in order to reduce the resistance of the contact between Si and W.
[0207]
Next, W or WSi _x Ar and N using the target of ₂ By reactive sputtering in a mixed gas atmosphere of _x N _y A film 708 is formed (FIG. 27A).
[0208]
Subsequently, sputtering is performed in an Ar gas atmosphere using a W target, or WF ₆ A W film 709 having a thickness of 100 nm is formed by system CVD (FIG. 27B).
[0209]
Next, SiN with a thickness of 250 nm _x A film 710 is formed by LPCVD at 800 ° C. for 30 minutes (FIG. 27B). At this time, in the conventional process, from the polycrystalline silicon 707 and 707 ′, n ⁺ And p ⁺ There is a problem that impurities in the type polycrystalline silicon diffuse toward the W film 709 and increase the resistance value of the W film 709. _x N _y By using 708, impurity diffusion from the silicon film to the W film can be prevented. Thereby, depletion of the gate as shown in FIG. 23B and mutual diffusion as shown in FIG. 24B can be prevented.
[0210]
Subsequently, a resist pattern 750 is formed in the shape of a desired gate electrode or gate wiring by using a photolithography technique (FIG. 27C), and the resist pattern 750 is used as a mask to form SiN. _x The film 710 is patterned using the RIE method. Next, the resist 750 is removed using an asher and patterned SiN. _x W film 709, WSi using film 710 as a mask _x N _y Film 708, WSi _x The film 723 and the Si film 707 or 707 ′ are patterned using the RIE method to form a gate electrode or a wiring (FIG. 28A).
[0211]
Next, H ₂ O, H ₂ , N ₂ Selective oxidation is performed in a gas atmosphere at 800 ° C. for 30 minutes. By this selective oxidation, only silicon is oxidized without oxidizing W to form an oxide film 711 on the side surfaces of the silicon portion and the silicon portion of the gate electrode.
[0212]
Next, As is applied to the source / drain region of the p-type region 722 with an acceleration voltage of 20 keV and a dose of 5 × 10. ¹⁴ / Cm ² Ion implantation is performed under the following conditions. The source / drain region of the n-type region 722 ′ has BF ₂ Accelerating voltage 20 keV, dose amount 5 × 10 ¹⁴ / Cm ² Ion implantation is performed under the following conditions. Thereby, low concentration source / drain regions 712 and 712 ′ are formed (FIG. 28B).
[0213]
Next, SiN having a thickness of about 50 nm is formed by CVD. _x By depositing a film and subsequently performing anisotropic etching using the RIE method, SiN is formed on the gate sidewall. _x A film 713 is formed (FIG. 28B).
[0214]
Thereafter, As is applied to the source / drain region of the p-type region 722 with an acceleration voltage of 60 keV and a dose of 7 × 10 ¹⁵ / Cm ² Ion implantation is performed under the following conditions. The source / drain region of the n-type region 722 ' ₂ Accelerating voltage 60 keV, dose amount 7 × 10 ¹⁵ / Cm ² Ion implantation is performed under the following conditions. Thereby, deep source / drain regions 714 and 714 ′ are formed (FIG. 28B).
[0215]
Thereafter, an interlayer film is formed by a normal method and Al wiring is performed, whereby a complementary MOSFET having excellent reliability can be obtained.
[0216]
According to the present invention, by forming the diffusion prevention layer at the interface between silicon and metal or metal silicide, it is possible to suppress the diffusion of impurities in silicon into the metal or metal silicide by a thermal process. For example, WSi as a diffusion preventing layer _x N _y Using W / WSi _x N _y / Si laminated structure is formed, 1 × 10 in Si ²⁰ / Cm ^Three When a heat step at 950 ° C. for 30 minutes was applied to a sample containing As, the As concentration in W was 1 × 10 ¹⁸ / Cm ^Three It is as follows. Therefore, even if this degree of heat treatment is applied, the impurity concentration in W is kept sufficiently low, so that no mutual diffusion occurs in the CMOSFET. The impurity concentration in Si is approximately 1 × 10. ²⁰ / Cm ^Three So that gate depletion does not occur.
[0217]
In the above embodiment, a polycide using a W-based metal as a refractory metal or a polymetal structure has been described. However, the scope of the present invention is not limited to this, and other refractory metals or This can be achieved by forming a diffusion prevention layer made of an alloy containing a refractory metal, silicon and nitrogen at the interface between the refractory metal silicide and silicon. Further, the diffusion preventing layer may contain oxygen and carbon in addition to the three elements.
[0218]
As described above, according to the semiconductor device and the manufacturing method thereof (Embodiments 8 to 12) of the present invention, diffusion of impurities in polycrystalline silicon into metal or metal silicide in polycide or polymetal structure electrodes or wirings. Therefore, a highly reliable semiconductor device with excellent electrical characteristics and a method for manufacturing the same can be obtained.
[0219]
【The invention's effect】
As described above in detail, according to the present invention (Claim 1), an electrode (wiring) having a structure in which a conductive antioxidant film is provided between a metal film made of a refractory metal and a semiconductor film is employed. Therefore, oxidation of the semiconductor film at the interface between the metal film and the semiconductor film in the post-oxidation process can be prevented, and an increase in contact resistance can be suppressed. Therefore, the advantage of using a refractory metal can be sufficiently exhibited.
[0220]
Further, according to the present invention (Claim 2), an electrode (wiring) having a structure in which a conductive antioxidant film electrode is provided under a metal film made of a refractory metal is employed. Thus, oxidation of the semiconductor layer under the electrode (wiring) can be prevented, and deterioration of element characteristics due to the thickening of the insulating film can be prevented. Therefore, the advantage of using a refractory metal can be sufficiently exhibited.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view illustrating a method for forming a sample according to a first embodiment of the present invention.
FIG. 2 is a graph showing the oxidation temperature dependence of the oxide film thickness of the sample of FIG. 1 in comparison with the prior art.
FIG. 3 is a process cross-sectional view illustrating a method for forming a gate electrode (polymetal gate) according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view of a conventional gate electrode (polymetal gate).
FIG. 5 is a process cross-sectional view illustrating a sample forming method according to a third embodiment of the present invention.
6 is a graph showing the oxidation temperature dependence of the oxide film thickness of the sample of FIG.
FIG. 7 is a process cross-sectional view illustrating another sample forming method according to the third embodiment of the present invention.
8 is a graph showing the oxidation temperature dependence of the oxide film thickness of the sample of FIG.
FIG. 9 is a process cross-sectional view illustrating a method for forming a gate electrode (metal gate) according to a fourth embodiment of the present invention.
FIG. 10 is a process cross-sectional view illustrating a method for forming a gate electrode (polymetal gate) according to a fifth embodiment of the present invention.
FIG. 11 is a process cross-sectional view illustrating a method for forming the first half of a field effect transistor according to a sixth embodiment of the present invention.
FIG. 12 is a process cross-sectional view illustrating a method for forming a second half of a field effect transistor according to a sixth embodiment of the present invention.
FIG. 13 is a process sectional view showing a method for forming a field effect transistor for EEPROM according to a seventh embodiment of the present invention;
FIG. 14 is a diagram showing an evaluation result by XPS of a sample according to the first embodiment of the present invention.
FIG. 15 is a process cross-sectional view illustrating a conventional gate electrode manufacturing method using a titanium nitride film as a barrier layer.
FIG. 16 is a cross-sectional view showing an entrance path of an oxidant in a conventional gate electrode.
FIG. 17 is a diagram showing an As diffusion suppression effect in an eighth embodiment of the present invention.
FIG. 18 is a view showing the diffusion suppression effect of B in the eighth embodiment of the present invention.
FIG. 19 is a process sectional view showing the method for manufacturing the MOSFET according to the ninth embodiment of the invention.
FIG. 20 is a process sectional view showing the method for manufacturing the nonvolatile memory MOSFET according to the tenth embodiment of the invention.
FIG. 21 is a sectional view showing the structure of a nonvolatile memory MOSFET according to an eleventh embodiment of the present invention;
FIG. 22 is a sectional view showing the structure of a complementary MOSFET according to a twelfth embodiment of the present invention.
FIG. 23 is a cross-sectional view of a transistor for explaining problems of a conventional complementary MOSFET.
FIG. 24 is a plan view of a conventional complementary MOSFET and a cross-sectional view for explaining interdiffusion of impurities.
FIG. 25 is a cross-sectional view for explaining a complementary MOSFET manufacturing process according to the twelfth embodiment of the present invention;
FIG. 26 is a cross-sectional view for explaining a next step in a complementary MOSFET manufacturing process according to the twelfth embodiment of the present invention;
FIG. 27 is a cross-sectional view for explaining a next step in a complementary MOSFET manufacturing process according to the twelfth embodiment of the present invention;
FIG. 28 is a cross-sectional view for explaining a next step in a complementary MOSFET manufacturing process according to the twelfth embodiment of the present invention;
[Explanation of symbols]
1 ... Silicon substrate
2 ... Tungsten nitride film
3 ... Tungsten film
4 ... Oxidizing agent
10 ... Silicon substrate
11 ... Silicon oxide film (gate oxide film)
12 ... polycrystalline silicon film
13 ... Tungsten nitride film
14 ... Tungsten film
15 ... WSiN film (antioxidation film)
16 ... Silicon nitride film
17 ... Photoresist pattern
18… Corner
19 ... Silicon oxide film
20 ... Oxidizing agent
20a ... silicon substrate
21 ... Silicon oxide film
22 ... Tungsten nitride film
23 ... Tungsten film
30 ... Silicon substrate
31 ... Silicon oxide film
32 ... WSiN film (antioxidation film)
33 ... W film
40 ... Silicon substrate
41 ... Silicon oxide film (gate oxide film)
42 ... WSiN film (antioxidation film)
43 ... Tungsten film
44. Silicon nitride film
45. Photoresist pattern
46. Oxidizing agent
47 ... Corner part
50 ... Silicon substrate
51. Silicon oxide film (gate oxide film)
52. Polycrystalline silicon film
53 ... WSiC film (antioxidation film)
54. Tungsten film
55. Silicon nitride film
56 ... Photoresist pattern
57. Oxidizing agent
60 ... silicon substrate
61. Element isolation insulating film
62 ... Gate oxide film
63 ... polycrystalline silicon film
64 .. Tungsten nitride film
65. Tungsten film
66 ... WSiN layer
67. Silicon nitride film
68 ... resist pattern
69… Corner
70: Impurity diffusion layer
71 ... Silicon nitride film
72. Impurity diffusion layer
73 ... Metal silicide layer
74. Interlayer insulating film
75 ... Resist pattern
80 ... Board
81. Tunnel oxide film
82 ... polycrystalline silicon film
83 ... ONO film
84 ... WSiN
85 ... Tungsten film
86 ... Silicon nitride film
87 ... resist pattern

Claims (4)

Forming a silicon film on the substrate;
Forming a compound film comprising at least one of nitrogen and carbon and the refractory metal on the silicon film using at least one of Mo, W, Cr, and Co as the refractory metal;
Forming a metal film made of the refractory metal on the compound film;
By heat treatment, the compound film is changed to the refractory metal and integrated with the metal film, and at the interface between the integrated metal film and the silicon film, at least one of nitrogen and carbon and the refractory metal Forming a conductive anti-oxidation film containing silicon and forming at least one of the metal film, the anti-oxidation film, and an electrode and a wiring including a laminated film of the silicon film;
A step of oxidizing the silicon film after forming the antioxidant film;
A method for manufacturing a semiconductor device, comprising: Forming a semiconductor film on the substrate;
Forming a conductive antioxidant film containing a compound comprising at least one refractory metal of Mo, W, Cr, Co, at least one of nitrogen and carbon, and silicon on the semiconductor film;
Forming a metal film made of the high melting point metal on the oxidation film,
Etching the laminated film comprising the metal film, the antioxidant film and the semiconductor film to form at least one of an electrode and a wiring including the laminated film;
A step of oxidizing the semiconductor film after forming the antioxidant film;
A method for manufacturing a semiconductor device, comprising: Forming an insulating film on the semiconductor region;
Forming a conductive antioxidant film containing a compound comprising at least one refractory metal among Mo, W, Cr, and Co, at least one of nitrogen and carbon, and silicon on the insulating film;
Forming a metal film made of the high melting point metal on the oxidation film,
Etching the laminated film composed of the metal film and the antioxidant film to form at least one of an electrode and a wiring including the laminated film;
A step of oxidizing the semiconductor region after forming the antioxidant film;
A method for manufacturing a semiconductor device, comprising:   4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of performing the oxidation treatment is performed in an atmosphere containing hydrogen and water.

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