JPH05275652A - Stacked transistor provided with polysilicon thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To perform sufficiently hydrogenation of the upper TFT of the stacked transistor to improve the characteristics of the stacked transistor and to isolate the lower transistor of the stacked transistor from hydrogen at the time of the hydrogenation to improve the reliability of the stacked transistor to hot carriers. CONSTITUTION:In a stacked TFT, which is provided with a polysilicon TFT 6 and is provided with another transistor (a MOSFET) 7 under the the TFT 6, an interlayer insulating film between the upper TFT and the lower transistor is formed of a hydrogen diffusion stopping material (SiN) 2 and a wiring between the upper TFT 6 and the lower transistor 7 is formed of a conductive material (Ti) 1 of a small hydrogen permeability. An opening is made in a hydrogen transmission stopping layer (Ti) between an H diffusion source (P-SiN) and the TFT and hydrogenation of the TFT 6 is conducted through this opening.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack type transistor having a polysilicon thin film transistor (hereinafter also referred to as a TFT as appropriate), that is, a transistor having a stack structure having a transistor such as a MOSFET under a polysilicon TFT. And a method for manufacturing the transistor.

[0002]

2. Description of the Related Art Conventionally, in a polysilicon TFT, a dangling bond (unbonded bond) in poly-Si for forming a channel is hydrogenated and stabilized in order to terminate it. S
In the structure of (RAM), MOSFET under the TFT
The lower transistors such as the above are also hydrogenated, which deteriorates the hot carrier resistance.
5 Symposiumon VLSI Tech, P
106-).

Therefore, it is necessary to shield the upper TFT and the lower transistor (MOSFET or the like) against hydrogen diffusion. As a countermeasure against this, a means of forming a hydrogen diffusion blocking layer (silicon nitride SiN or the like) between the upper TFT and the lower transistor can be considered. However, even if such a hydrogen diffusion preventing layer is provided, hydrogen may diffuse into the contact hole and hydrogenate the MOSFET.

The present inventor has made a new proposal to solve this problem. This is the upper TF, as shown in FIG.
T6 (having channel poly Si61 and gate 62) and lower MOSFET 7 (gate 70, source / drain region 7)
1, 72 and the gate oxide film 73 are formed from the side wall of the contact hole 5 for forming the interlayer insulating film with the hydrogen diffusion blocking material 21 (LP-SiN) and connecting the both 6 and 7. Up to the upper surface of the hydrogen diffusion blocking material 22 (Ti
ON). The hydrogenation of the polysilicon 61 is performed by the hydrogen diffusion source material layer 8 (P-Si
It is carried out by hydrogen diffusion from N). Hydrogen is prevented from entering the MOSFET 7 as the lower transistor by the hydrogen diffusion blocking materials 21 and 22.

However, even when the contact hole 5 is filled with the plug of the material 22 having a small hydrogen diffusion coefficient as described above,
There is a problem that hydrogen diffuses around the contact hole 5 as schematically shown by an arrow A in the figure. This is because when the contact hole 5 has poor adhesion on the plug side,
Remarkably occurs.

On the other hand, it is possible to perform hydrogenation of the TFT from above the upper wiring layer. In this case, if the wiring layer contains a material (Ti or the like) having a small hydrogen permeation (diffusion) coefficient, the TFT is It is not sufficiently hydrogenated and the characteristics deteriorate. That is, P-SiN acting as a TFT and a hydrogen diffusion source
For example, Al wiring (usually Al / TiN / Ti
, Which is a metal wiring layer having a laminated structure, has a high ability of blocking hydrogen permeation by Ti in the wiring layer, and thus P-SiN which is a hydrogen diffusion source is provided.
Suppressing the diffusion of hydrogen from the
As a RAM, power consumption and data retention characteristics deteriorate.

There is also a method of hydrogenating before forming the metal wiring layer, but when an opening such as a contact hole is formed in the MOSFET, hydrogen is diffused through the opening and the MOSFET is hydrogenated, resulting in reliability. Is reduced.

[0008]

SUMMARY OF THE INVENTION The invention of the present application solves the above-mentioned problems of the prior art, and the upper TFT is sufficiently hydrogenated to have improved characteristics (characteristics of ON current and OFF current) and the lower transistor. Is not cut off from hydrogen and does not cause a problem of reliability deterioration due to hot carriers. Further, a stack type transistor having a polysilicon TFT which can be obtained by hydrogenating from above the upper wiring layer without any problem, and a method of manufacturing the same. Is to provide.

Further, according to the invention of the present application, even when a film for preventing hydrogen permeation such as a metal wiring layer is located between the hydrogen diffusion source and the TFT, the hydrogenation of the TFT is sufficiently performed. It is intended to provide a stack type transistor including a silicon TFT.

Further, according to the invention of the present application, even when a film for preventing hydrogen permeation such as a metal wiring layer is located between the hydrogen diffusion source and the TFT, hydrogen in the TFT is sufficiently performed. In addition, even in that case, it is an object of the present invention to provide a stack type transistor including a polysilicon TFT capable of suppressing hydrogen diffusion into a lower transistor such as MOSFET and preventing reliability deterioration due to hot carriers.

[0011]

The invention according to claim 1 of the present application is a stack type thin film transistor including a polysilicon thin film transistor and another transistor below the polysilicon thin film transistor, wherein an upper polysilicon thin film transistor and a lower transistor are provided. And a polysilicon thin film transistor, characterized in that an interlayer insulating film between and is formed of a hydrogen diffusion blocking material, and the wiring between the upper polysilicon thin film transistor and the lower transistor is formed of a conductive material having low hydrogen permeability. It is a stack type transistor, and achieves the above object.

According to the second aspect of the present invention, the wiring between the lower transistor and the upper polysilicon thin film transistor is formed of a conductive material having a low hydrogen permeability, and the interlayer insulating film between the lower transistor and the upper polysilicon thin film transistor is formed. A stack type transistor provided with a thin film transistor, which is formed of a hydrogen diffusion blocking material, forms a polysilicon thin film transistor, then forms a hydrogen diffusion source material layer, and hydrogenates polysilicon by the hydrogen diffusion source material layer. And a method for producing the above-mentioned object.

According to a third aspect of the present invention, the wiring between the lower transistor and the upper polysilicon thin film transistor is formed of a conductive material having a low hydrogen permeability, and an interlayer insulating film between the lower transistor and the upper polysilicon thin film transistor is formed. Formed of a hydrogen diffusion blocking material, after forming a polysilicon thin film transistor, is a method of manufacturing a stack type transistor including a thin film transistor, characterized in that hydrogenation of polysilicon is performed by processing in a hydrogenatable atmosphere, This achieves the above object.

According to the invention of claim 4 of the present application, the interlayer insulating film between the lower transistor and the upper polysilicon thin film transistor is formed of a hydrogen diffusion blocking material, and then the wiring between the lower transistor and the upper polysilicon thin film transistor is permeated with hydrogen. Formed of a conductive material having low conductivity, after forming a polysilicon thin film transistor, is a method of manufacturing a stack type transistor comprising a thin film transistor, which is characterized by performing hydrogenation of polysilicon, thereby achieving the above object. is there.

The invention of claim 5 of the present application is a stack type thin film transistor comprising a polysilicon thin film transistor and another transistor below the polysilicon thin film transistor, wherein a hydrogen diffusion source material layer is provided above the upper polysilicon thin film transistor. A film for preventing hydrogen permeation is located between the hydrogen diffusion source material layer and the upper polysilicon thin film transistor, and a hydrogenation opening is partially formed in the film for preventing hydrogen permeation. And a stack type thin film transistor which achieves the above object.

According to a sixth aspect of the present invention, there is provided a stack type thin film transistor having a polysilicon thin film transistor and another transistor provided below the polysilicon thin film transistor, wherein a hydrogen diffusion source material layer is provided above the upper polysilicon thin film transistor. A film that blocks hydrogen permeation is located between the hydrogen diffusion source material layer and the upper polysilicon thin film transistor, and a hydrogenation opening is partially formed in the film that blocks hydrogen permeation. The membrane that blocks hydrogen permeation is
A stack type thin film transistor having a structure covering an opening leading to a diffusion layer of a lower transistor, which achieves the above object.

[0017]

According to the inventions of claims 1 to 4 of the present application, the interlayer film between the upper TFT and the lower transistor is formed of a hydrogen diffusion blocking material, and the wiring between both transistors is made to pass through hydrogen permeation such as Ti. Since it is formed of a conductive material having a low rate, even if the upper TFT is sufficiently hydrogenated to improve its characteristics, the lower transistor is not affected by hydrogen, and the lower transistor performance is not deteriorated. A highly reliable device can be obtained. And,
It is not necessary to use a material having a low hydrogen permeability such as Ti for the wiring layer on the TFT, and hydrogenation from the upper wiring layer can be performed without any problem.

In the invention of claim 5 of the present application, TF
Even if a film for preventing hydrogen permeation such as a metal wiring layer is located between the hydrogen diffusion source material layer for hydrogenating T and the upper polysilicon TFT, the film for preventing hydrogen permeation does not contain hydrogen. Sufficient hydrogenation can be achieved because the hydrogenation can be carried out from where the chemical openings are partially formed.

Further, in the invention of claim 6 of the present application, in addition to the action and effect of claim 5, the film for preventing hydrogen permeation is on an opening (contact hole or the like) communicating with the diffusion layer of the lower transistor. As a result of covering the
It is possible to prevent adverse effects due to hydrogen diffusion of the lower transistor such as OSFET.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the examples described below.

Example 1 In this example, the present invention is used for manufacturing a TFT stack semiconductor device used for a highly miniaturized and integrated SRAM.

FIG. 1 shows a TFT stack type SR of this embodiment.
1 shows a schematic structure of AM. The transistor of this embodiment is
A polysilicon thin film transistor (TFT) 6 is provided, and another transistor 7 (here, MOSFET
T) which is a stack type thin film transistor, in which an interlayer insulating film between the upper polysilicon thin film transistor 6 and the lower transistor 7 is formed of a hydrogen diffusion blocking material 2 (here, SiN), and the upper polysilicon thin film transistor 6 is formed. The wiring between the lower transistor 7 and the lower transistor 7 is formed of a conductive material 1 (Ti here) having low hydrogen permeability.

Further, FIGS. 2A to 2H show a method of manufacturing a stack type transistor in this embodiment in the order of steps. In this embodiment, as shown in FIG. A wiring with the silicon thin film transistor 6 is formed of a conductive material 1 having a low hydrogen permeability (FIG. 2D), and an interlayer insulating film between the lower transistor 7 and the upper polysilicon thin film transistor 6 is formed with a hydrogen diffusion blocking material 2 (SiN). (FIG. 2 (e)), a polysilicon thin film transistor is formed (FIG. 2 (f)), and then a hydrogen diffusion source material layer 8 (P-SiN) is formed (FIG. 2).
(H)) Polysilicon hydrogenation is performed by the hydrogen diffusion source material layer 8.

In the present embodiment, in the stacked SRAM using the poly-Si TFT 6, the interlayer insulating film between the upper TFT 6 and the MOSFET which is the lower transistor is formed from LP (low pressure CVD) -SiN which is a hydrogen diffusion blocking material and is formed in the lower portion. Insulates transistor 7 from hydrogen diffusion, and
As the wiring material between the FT 6 and the lower transistor 7 (MOSFET), Ti, which is a conductive material 1 having a low hydrogen permeability, is used, and a contact is made between the wiring layer above the TFT and the MOSFET diffusion layer through this, so that the contact hole 4 is formed.
Prevent hydrogen diffusion. In this embodiment, hydrogenation is performed after the upper wiring layer is formed, but only the TFT is hydrogenated.

Specifically, in this embodiment, the stack type SRAM is manufactured by the following steps (a) to (h). 2A to 2H show steps (a) to (h).
It corresponds to each. Each step will be described below with reference to the drawings.

(A) MOSFE which is a lower transistor
T formation Using the silicon semiconductor substrate 10, after performing element isolation by the LOCOS method, the gate oxide film 73 is thermally oxidized (850
(11 nm). Next, a gate electrode material is deposited (here, a WSi / Poly-Si polycide structure is 200 nm) and patterned by lithography to form a gate electrode 70.

LDD ion implantation (P ⁺ 20 keV, dose amount 2 × 10 ¹³ atoms / cm ² ) is performed to form an LDD region 74.
After the formation of SiO ₂ , SiO ₂ is deposited by CVD and RI
By etching back with E, the gate electrode
Sidewalls 75 are formed beside 70. Using these as masks, ion implantation (As
⁺²⁰ keV, dose 5 × 10 ¹⁵ atoms / c
m ² ) to form a MOSFET, which is used as the lower transistor 7. As a result, the structure shown in FIG. 2A is obtained.

(B) Formation of Interlayer Insulating Film An interlayer insulating film 91 such as SiO ₂ or PSG is formed by CVD (300 nm). The structure shown in FIG. 1B is obtained.

(C) Formation of contact hole (lower part) After patterning by lithography, interlayer insulating film
The contact hole 4 is formed at 91. As a result,
The structure is (c).

(D) Formation of a conductive material wiring layer having a low hydrogen permeability: Ti is deposited (30 nm) by a sputtering method, and MO is formed.
A contact with the diffusion layer of the SFET is formed. Usually, this contact is W, W polycide, Mo, Mo
Polycide is used, but here T with a small hydrogen permeability is used.
i is used. Next, patterning is performed by lithography to obtain the structure shown in FIG.

(E) Formation of Hydrogen Diffusion Blocking Layer A SiN film is formed by LP-CVD to form a hydrogen diffusion blocking layer 2. The deposition conditions are a deposition temperature of 760 ° C. and a film thickness of 30 n
m. As a result, the structure shown in FIG. 2E is obtained.

(F) TFT formation Poly-Si as a gate electrode material is deposited by CVD (50 nm), and after ion implantation (BF ₂ 20).
keV, dose amount 1 × 10 ¹⁵ atoms / cm ² ), patterning by lithography, and gate electrode
Form 60. As the gate oxide film 62, S by CVD
An iO ₂ film is formed (35 nm).

Polysilicon 61 to be a TFT active layer is formed. The formation method is low pressure CVD, and the deposition temperature is 55
After depositing a (amorphous) -Si at 0 ° C. (10 n
m), annealed in N ₂ (600 ° C., 10 hours)
Then, a polysilicon film is formed. Then, patterning is performed by lithography.

Next, the channel forming portion is resist masked by lithography and ions are implanted into the remaining portion (BF ₂ 10 keV, dose amount 1 × 10 5).
¹⁵ atoms / cm ² ) and TFT source / drain regions 6a and 6b are formed. As a result, the structure of FIG. 2F in which the upper TFT 6 is formed is obtained.

(G) Formation of Interlayer Insulating Film and Formation of Upper Contact Hole An interlayer insulating film 92 of SiO ₂ , PSG or the like is formed by CVD (400 nm). Next, after patterning by lithography, the upper contact hole 5 is formed. As a result, the structure shown in FIG. 2 (g) is obtained.

(H) Formation of upper wiring layer and hydrogenation As the wiring layer 3, the TiON (10
0 nm), Al-Si (Al alloy containing 1 wt% Si)
Deposition is performed in the order of (600 nm). It is not necessary to form a Ti layer below this TiON layer. This is because Ti is previously formed in the contact hole 4. If there is no Ti in the lower layer and Ti is required here, hydrogen diffusion from the upper wiring becomes inefficient.

Next, as the hydrogen diffusion source material layer 8, a SiN film is deposited by plasma CVD (300 nm). After that, annealing (350 ° C., 30 min) is performed in an inert gas (N ₂ gas or a gas obtained by adding H ₂ to N ₂ gas in an amount of about 1 to 2 flow%) is used, and a hydrogen diffusion source material Hydrogen is diffused from the SiN film which is the layer 8 to hydrogenate the polysilicon 61.

At the time of the hydrogenation, in this embodiment, the upper TFT 6 and the lower transistor 7 are MOSFETs.
The inter-layer insulation film (SiN) having a small hydrogen diffusion coefficient is used as the hydrogen diffusion prevention layer 2, and the TFT and the MOS are
By using the conductive material 1 (Ti) having a small hydrogen permeability (coefficient) as the wiring material between the FETs, only the TFT can be sufficiently hydrogenated without the influence of hydrogen on the lower transistor 6.

Further, hydrogen is prevented from diffusing in the contact hole 5 by making contact between the upper wiring layer 3 and the diffusion layer of the lower MOSFET via Ti described above. Further, hydrogen can be diffused from the upper portion of the upper wiring layer without any problem.

As described above, in the present embodiment, it is not necessary to use Ti for the upper wiring layer 3. As a reference,
The difference in TFT characteristics when the structure of the wiring layer on the TFT is changed depending on the presence or absence of Ti is shown in FIG. Figure 3 (a)
In (b), the characteristics of each of the following structures were examined. (A) AlSi (600 nm) / Ti (30 nm) (b) AlSi (600 nm)

It should be noted that the hydrogenation of the TFT is carried out by using the P on the wiring layer.
-It is performed by hydrogen diffusion from the SiN film. (A)
When there is Ti, the ON current is small and the S value is 624 m.
V / dec is large, whereas (b) the structure without Ti has a large ON current of two digits or more and an S value of 229 mV /
It is as small as dec, and the characteristics are very good. From this, it is understood that Ti hinders diffusion of hydrogen and deteriorates TFT characteristics. The present embodiment does not cause such a problem of hydrogen inhibition by Ti.

Embodiment 2 In this embodiment, after forming the upper wiring layer 3 in Embodiment 1, the hydrogen diffusion source material layer 8 is not provided, that is, in the state of the structure shown in FIG. Is carried out by treatment in a hydrogenatable atmosphere. Here, specifically, hydrogenation was performed in plasma hydrogen. As the other process during hydrogenatable atmosphere, it is possible to use processing means in addition to the plasma treatment in H _2, in section and, or hydrogen containing compounds atmosphere other than of H ₂ such as effected by hydrogen annealing.

Embodiments 3 and 4 In this embodiment, hydrogenation is performed before forming the upper wiring layer 3 in Embodiments 1 and 2. Therefore, in these examples, as shown in FIG.
The structure is such that the upper wiring layer 3 is formed.

In the case of this example, when it is not desired to leave the P-SiN layer (hydrogen diffusion source material layer 8), the method of Example 2 is modified as in this example to perform plasma hydrogenation. Is preferred.

Example 5 In this example, the structure of Examples 1 (c) to (e) is modified to form a hydrogen diffusion blocking layer 2 (SiN), and then a contact hole 5 is formed to allow hydrogen permeation. This is an example in which a conductive material layer 1 (Ti) having a small rate is formed to be a wiring layer. The structure is
As shown in FIG.

Embodiment 6 This embodiment embodies the inventions of claims 5 and 6 to realize a PMO.
This is applied to an S load type SRAM. Please refer to FIG.

This embodiment is a cross-sectional view of FIG.
As shown in a plan view in (b), a polysilicon thin film transistor (TFT) 6 is provided, and a MOSFE is provided under the polysilicon thin film transistor (TFT) 6.
A stack type thin film transistor having another transistor 7 of T, which is a hydrogen diffusion source material 8 made of P-SiN in an upper layer of the upper polysilicon thin film transistor 6.
And forming a part of a metal wiring layer between the hydrogen diffusion source material layer 8 and the upper polysilicon thin film transistor 6.
A film 11 for blocking hydrogen permeation, which is an i layer, is located, and a hydrogenation opening 12 is partially formed in the film 11 (Ti layer) for blocking hydrogen permeation.

Further, the present embodiment is a membrane for preventing the hydrogen permeation.
The structure 11 covers the opening 4 communicating with the diffusion layer of the lower transistor 7. In this example, this opening is a contact hole.

That is, in the PMOS load type SRAM using the poly SiTFT of this embodiment, the metal wiring layer (A
Layer 11 for blocking hydrogen permeation in (Si / TiON / Ti) 11
Ti is opened only on the TFT channel (AlSi /
The TiON layer is indicated by reference numeral 13), and through this opening 12, the P-Si of the hydrogen diffusion source material layer 8 which is a passivation film.
TFT hydrogenation is performed by hydrogen diffusion from N 2.

Further, SiN is formed under the TFT by low pressure CVD.
By depositing a film (LP-SiN) and covering the opening 4 (contact hole) with Ti, which is the layer 11 that blocks the permeation of hydrogen, hydrogen diffusion to the bulk MOSFET is prevented and reliability due to hot carriers is increased. Prevent deterioration.

In this embodiment, the following steps (A)-
A transistor is obtained by (D). Please refer to FIG. (A) MOSFET formation After forming a field oxide film 14 of 290 nm on the Si substrate (P type) 10 by the LOCOS method and performing element isolation,
A gate oxide film 73 is formed by thermal oxidation (850 ° C., 1
1 nm). Next, a gate electrode material is deposited (WSi / poly Si, 200 nm) and patterned by lithography to form a gate electrode 70. After LDD ion implantation (P ⁺ 20 keV, 2E13 / cm ² ), SiO ₂ is deposited by the CVD method and etched back by RIE to form the sidewalls 75 beside the gate electrode.
To form. Source / drain 71 and 72 the ion implantation for the formation ^{(As +, 20keV, 5E15 /} cm 2) is performed, thereby forming a MOSFET as a lower transistor 7. As a result, the structure shown in FIG. 9A is obtained.

(B) TFT formation SiO ₂ and PSG are formed to a thickness of 300 nm by the CVD method to form an interlayer insulating film 91. Next, by low pressure CVD, SiN
The film 21 is deposited to 30 nm. Poly-Si by CVD method 5
0 nm formed, and ion-implanted (BF ₂ ⁺ , 20 keV, 1
After E15 / cm ² ), patterning is performed by lithography to form the gate electrode 60. As the gate oxide film 62, SiO ₂ is deposited to a thickness of 35 nm by CVD. Next, a-Si is deposited to a thickness of 10 nm by low pressure CVD, and then N
Long annealing (600 ° C., 10 hours) in ₂ performs,
A poly-Si active layer 61 is formed. By the lithography method, the channel forming portion is used as a resist mask and ion implantation is performed (BF ₂ ⁺¹⁰ keV, 1E15 / cm ² ) to form the source / drain regions 71 and 72. As a result,
The structure of (b) is obtained.

(C) Metal wiring layer formation An interlayer insulating film 92 is deposited to a thickness of 400 nm. This interlayer insulating film 92
Is patterned to form the opening 4 in the diffusion layer 71. Then, Ti is formed to 30 nm by sputtering.
This Ti film is the film 11 that blocks hydrogen permeation. By patterning this film 11 by lithography, the TFT
Ti is opened only on the channel. The opening is shown at 12. By sputtering, TiON100nm, AlSi600nm
Is deposited and patterned by lithography to form a metal wiring layer 13. As a result, FIG. 9 (c)
Get the structure of.

(D) Formation of passivation film and hydrogenation As passivation film, SiN is formed by P-CVD.
(P-SiN) is deposited to 300 nm. This is the hydrogen diffusion source material layer 8. Annealed in an inert gas (400
Then, the TFT is hydrogenated by hydrogen diffusion from P-SiN. As a result, a transistor structure having the TFT upper transistor 6 shown in FIG. 9D can be obtained. FIG. 10 shows the TFT characteristics when Ti is present in the metal wiring layer on the TFT (a) and when it is not present (b). When Ti is not present, the hydrogenation of the TFT is sufficiently performed, the TFT characteristics are dramatically improved, and the ON current is 2
It is larger than a digit. According to this embodiment, the hydrogenation of the TFT can be sufficiently performed, and low charge power and high data retention characteristics can be realized as the SRAM. In addition, the LP-SiN layer 21 is provided under the TFT which is the upper transistor 6, and the titanium layer (film 11) covers the opening 4 to form the bulk M.
Since hydrogen diffusion to the OSFET can be prevented, hot carrier reliability can be maintained.

[0055]

As described above, according to the present invention, the TF
T is sufficiently hydrogenated and its characteristics are improved, and the lower transistor is shielded from hydrogen and has good reliability with respect to hot carriers. Furthermore, hydrogenation from the upper wiring layer is also performed without any problem. It is possible to provide a stack-type transistor including a polysilicon TFT that can be obtained as described above and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a transistor of Example 1.

2A to 2D are cross-sectional views sequentially showing manufacturing steps of the transistor of Example 1. FIG.

FIG. 3 is a diagram showing a difference in characteristics depending on the presence or absence of Ti in a TFT upper layer.

FIG. 4 is a diagram showing a second embodiment.

FIG. 5 is a diagram showing Examples 3 and 4.

FIG. 6 is a diagram showing a fifth embodiment.

FIG. 7 is a diagram showing a problem.

FIG. 8 is a diagram showing a sixth embodiment.

FIG. 9 is a diagram showing a process of Example 6;

FIG. 10 is a diagram showing an operation of Example 6.

[Explanation of sign]

 1 Conductive Material (Ti) with Small Hydrogen Permeability 2 Hydrogen Diffusion Blocking Material (SiN) 3 Upper Wiring Layer 4 Opening (Contact Hole) 5 Upper Contact Hole 6 TFT 7 Lower Transistor (MOSFET) 8 Hydrogen Diffusion Source Material Layer (Plasma SiN ) 10 Substrate 11 Membrane that blocks hydrogen permeation 12 Opening of membrane that blocks hydrogen permeation

Claims (6)

[Claims] 1. A stack type thin film transistor comprising a polysilicon thin film transistor and another transistor provided below the polysilicon thin film transistor, wherein an interlayer insulating film between the upper polysilicon thin film transistor and the lower transistor is formed of a hydrogen diffusion blocking material. A stack type transistor comprising a polysilicon thin film transistor, characterized in that a wiring between the upper polysilicon thin film transistor and the lower transistor is formed of a conductive material having a low hydrogen permeability. 2. The wiring between the lower transistor and the upper polysilicon thin film transistor is formed of a conductive material having a low hydrogen permeability, and the interlayer insulating film between the lower transistor and the upper polysilicon thin film transistor is formed of a hydrogen diffusion blocking material. A method of manufacturing a stacked transistor comprising a thin film transistor, comprising forming a polysilicon thin film transistor, forming a hydrogen diffusion source material layer, and hydrogenating polysilicon by the hydrogen diffusion source material layer. 3. The wiring between the lower transistor and the upper polysilicon thin film transistor is formed of a conductive material having a low hydrogen permeability, and the interlayer insulating film between the lower transistor and the upper polysilicon thin film transistor is formed of a hydrogen diffusion blocking material. A method of manufacturing a stacked transistor including a thin film transistor, which comprises forming a polysilicon thin film transistor and then hydrogenating the polysilicon by processing in a hydrogenatable atmosphere. 4. An interlayer insulating film between the lower transistor and the upper polysilicon thin film transistor is formed of a hydrogen diffusion blocking material, and then a wiring between the lower transistor and the upper polysilicon thin film transistor is formed of a conductive material having a low hydrogen permeability. A method for manufacturing a stack type transistor having a thin film transistor, which comprises forming a polysilicon thin film transistor and then hydrogenating the polysilicon. 5. A stack type thin film transistor comprising a polysilicon thin film transistor and another transistor provided under the polysilicon thin film transistor, wherein a hydrogen diffusion source material layer is provided on an upper layer of the upper polysilicon thin film transistor. A stack type thin film transistor, wherein a film that blocks hydrogen permeation is located between the upper polysilicon thin film transistor and a hydrogenation opening is partially formed in the film that blocks hydrogen permeation. 6. A stack type thin film transistor comprising a polysilicon thin film transistor and another transistor provided below the polysilicon thin film transistor, wherein a hydrogen diffusion source material layer is provided on an upper layer of the upper polysilicon thin film transistor. A film that blocks hydrogen permeation is located between the upper polysilicon thin film transistor and the film that blocks hydrogen permeation is formed with a hydrogenation opening partially formed in the film that blocks hydrogen permeation. A stack type thin film transistor, characterized in that it is configured to cover an opening leading to a diffusion layer of a lower transistor.