JPH07231253A - Level converter circuit - Google Patents

Abstract

PURPOSE:To realize high speed operation and low power consumption for the circuit. CONSTITUTION:CMOS inverters 3, 4 with a low threshold voltage are connected in cascade and a CMOSFET M5 with a high threshold voltage is connected in series between a common connecting source of PMOSFETs of the CMOS inverters 3, 4 and a power supply terminal. Complementary signals obtained by both CMOS inverters 3, 4 are given to a latch circuit 5 comprising CMOS inverters with a high threshold voltage and an output of the latch circuit 5 is led to an output terminal via CMOS inverters 6, 7 with a high threshold voltage in cascade connection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit used for interfacing between LSIs of different power sources, and more particularly to a dry cell power source driven LSI and a conventional 3V.
The present invention relates to a level conversion circuit suitable for level conversion between a power supply driven or 5V power supply driven LSI.

[0002]

2. Description of the Related Art A circuit using a latch circuit as a conventional level conversion circuit is shown in FIG. As an example of this, for example, M.
Matsui et.al., IEEE Journal of Solid-State Circuit
s, Vol.24, No.5, pp. 1226-1232, Oct. 1989.

In FIG. 7, reference numeral 41 is an input terminal and 42 is an output terminal. Reference numeral 43 is a latch circuit to which a power supply voltage Vdd2 (= 3V) is supplied.
It is simply called "pMOS transistor". ) M41, nM
OSFET (hereinafter simply referred to as “nMOS transistor”) M42 CMOS inverter, and pMOS transistor M43 and nMOS transistor M44 CMOS
It is composed of an inverter and a pMOS transistor M41,
The gate of M43 is a cross couple connected to the drain of the other side.

44 is a pMOS transistor M45, nM
The CMOS inverter including the OS transistor M46 supplies the power supply voltage Vdd1 (= 1 V). 45 is pMO
The power supply voltage Vdd2 is supplied by a CMOS inverter composed of an S transistor M47 and an nMOS transistor M48. Reference numeral 46 is a CMOS inverter composed of a pMOS transistor M49 and an nMOS transistor M50, to which the power supply voltage Vdd2 is supplied.

In this level conversion circuit, an input signal of 1 V amplitude input between the input terminal 41 and the ground and a signal obtained by inverting the signal by the inverter 44 are nM of the latch circuit 43.
By applying to the gates of the OS transistors M43 and M44, an output voltage of 3V amplitude is generated at the output terminal 42. In particular, here, the pMOS of the latch circuit 43 is
By the cross couple of transistors M41 and M43,
The positive feedback operation is performed so that the output inversion operation is accelerated.

[0006]

By the way, in this level conversion circuit, in order to level-convert the input signal amplitude from 1V to 3V, a complementary signal of a small-amplitude signal of 1V is required. The inverter 44 that inverts is essential.

However, although the power supply voltage is used as Vdd1 (= 1V) in order to obtain a complementary signal having a signal amplitude of 1V, the inverter 44 used there is provided with a high threshold voltage for driving 3V (for example, 0. 6V) MOS transistors have the problem that the delay time increases and high-speed operation becomes impossible. Conversely, if they are composed of low threshold voltage (for example, 0.2V) MOS transistors, they will not operate There is a problem that the leakage current and the power consumption during operation increase, and when a dry battery is used there, its life becomes extremely short.

An object of the present invention is to solve the above problems by making it possible to operate at high speed and with low power consumption, and to a level suitable as an interface between a dry battery driven LSI and a conventional 3V or 5V driven LSI. It is to provide a conversion circuit.

[0009]

The above-mentioned object is achieved by the first invention, that is, a first inverter group consisting of two or more inverters to which a signal at an input terminal is inputted, and the first inverter group. A latch circuit for inputting the obtained complementary output,
Receives the output of the latch circuit and outputs a signal to the output terminal 1
A second inverter group consisting of a plurality of inverters or two or more inverters in which the output of the preceding stage is connected to the input of the following stage, and the first inverter group is provided with a low threshold voltage M
A plurality of CMOS inverters each composed of an OSFET, the high-potential power source side being commonly connected, the low-potential power source side being commonly connected, and the output of the preceding stage connected to the input of the following stage;
High threshold voltage MOS connected in series with OS inverter
FET having a high threshold voltage
A power-down control signal for reducing current consumption during non-operation is connected to the gate of the first inverter, the latch circuit and the second inverter group are configured by high threshold voltage MOSFETs, and the first inverter is provided. This is achieved by a level conversion circuit which supplies a first power supply voltage to the group and supplies a second power supply voltage larger than the first power supply voltage to the latch circuit and the second inverter group.

In the first aspect of the present invention, the first inverter group is connected in series to a first CMOS inverter composed of a low threshold voltage MOSFET and a high power supply side of the first CMOS inverter. First M of voltage
It is composed of a first inverter composed of an OSFET, a second CMOS inverter composed of a MOSFET having a low threshold voltage, and a second MOSFET having a high threshold voltage connected in series to the low power supply side of the second CMOS inverter. A second inverter having the output of the first inverter connected to the input, and the first and second MOSFEs.
It is possible to replace the gate of T with a configuration in which a power-down control signal for reducing current consumption during non-operation is connected.

The above-mentioned object is the second invention, that is, it comprises a plurality of inverters connected in n stages so that the output of the preceding stage is connected to the input of the following stage, and the first stage inverter is composed of a MOSFET of low threshold voltage. The first CMOS inverter and the first MOSFET are connected in series, the drain of the first MOSFET is connected to the pseudo power supply line, and the i-th inverter of the second and subsequent stages is connected to the low threshold value. -Th CMOS inverter and i-th MOSFE which consist of MOSFET of threshold voltage or higher
In the series connection of T, the drain of the i-th MOSFET is connected to the pseudo power supply line and the source is connected to the gate of the (i-1) -th MOSFET. The n-th CMOS inverter, which is composed of a MOSFET having a threshold voltage higher than the threshold voltage, and the n-th MOSFET are connected in series,
The source of the nth MOSFET is connected to the first power supply, the drain is connected to the gate of the n−1th MOSFET and the pseudo power supply line, and the gate is for reducing current consumption when not operating. It is also achieved by a level conversion circuit characterized in that it is connected to a power down control signal.

[0012]

In the first aspect of the invention, the high speed operation is performed by the low threshold voltage CMOS inverter of the first inverter group to which the input signal is input. In addition, the high threshold voltage MOSFET connected in series to the CMOS inverter effectively shuts off the leak current during non-operation and reduces the power consumption.

In the second invention, in addition to the operation of the first invention, the operating voltage of the CMOS inverter gradually increases during operation and the signal amplitude gradually increases, so that power consumption can be reduced during operation.

[0014]

【Example】

[First Embodiment] An embodiment of the present invention will be described below. FIG. 1 is a diagram showing a level conversion circuit of the first embodiment. Reference numeral 1 is an input terminal and 2 is an output terminal.

3 is a pMOS transistor M1, an nMOS
CMOS inverter composed of transistor M2, 4 also p
A CMOS inverter composed of a MOS transistor M3 and an nMOS transistor M4 having low threshold voltage (0.2 V) is used for these transistors M1 to M4, which enables high speed operation. In the inverters 3 and 4, the output of the front stage is connected to the input of the rear stage (cascade connection). The sources (high potential side) of the pMOS transistors M1 and M3 are commonly connected, and the sources (low potential side) of the nMOS transistors M2 and M4 are commonly connected to ground.

The pMOS transistor M5 has a power-down control signal C at the gate when it is not operating in order to reduce current consumption.
This is a transistor to which SB is applied, and the drains thereof are connected to the sources of the pMOS transistors M1 and M3. A high threshold voltage (0.6 V) is used as this transistor. The above inverters 2 and 3 and the transistor M5 constitute a first inverter group, to which the power supply voltage Vdd1 (= 1V) is supplied.

Reference numeral 5 denotes a cross-coupled latch circuit, which is a CMOS inverter including a pMOS transistor M6 and an nMOS transistor M7, and a CMOS inverter including a pMOS transistor M8 and an nMOS transistor M9.
An inverter and a pMOS transistor M6,
M8 is cross-coupled, and those transistors M6 ...
A high threshold voltage (0.6 V) is used for M9. The power supply voltage Vdd2 is applied to the latch circuit 5.
(= 3V) is supplied.

The output voltage of the inverter 3 (V1) and the output voltage of the inverter 4 (V
2) is applied. That is, the complementary signal (the input signal and its inverted signal) of the signal input to the input terminal 1 is input to the latch circuit 5. Therefore, in the latch circuit 5, the 1V amplitude signal input from the inverters 3 and 4 is level-converted into the 3V amplitude signal.

6 is a pMOS transistor M10, nMO
CMOS inverter consisting of S-transistor M11,
The power supply voltage Vdd2 is supplied. 7 is a C composed of a pMOS transistor M12 and an nMOS transistor M13
The power supply voltage Vdd2 is supplied by the MOS inverter. These two inverters 6 and 7 form a second inverter group, and are connected between the output side of the latch circuit 5 and the output terminal 2 in a configuration in which the output of the preceding stage is connected to the input of the latter stage (cascade connection). Transistor M1 used here
A high threshold voltage (0.6 V) is used for 0 to M13. As described above, here, the inverter is connected in two stages and the driving force is increased by gradually increasing the size of the inverter, but the number of stages may be one.

Now, the operation of the level conversion circuit of the first embodiment is performed as follows. First, during operation, the pMOS transistor M5 commonly connected to the inverters 3 and 4 becomes conductive, so that the inverters 3 and 4 are connected to Vdd1 (1
It becomes possible to operate at high speed with the power supply voltage of V). The complementary signals (voltages V1 and V2) obtained by the inverters 3 and 4 are input to the latch circuit 5, where the level is converted from the 1V amplitude to the 3V amplitude, and the inverters 6 and 7 generate a signal having a large driving force and output. A high-speed and large-driving signal having an amplitude of 3 V can be obtained at the terminal 2.

When not operating, the power down signal (CS
Since the pMOS transistor M5 becomes non-conductive due to B), the outputs (voltages V1 and V2) of the inverters 3 and 4 decrease while maintaining the magnitude relationship of the voltage values. That is, although a leak current flows through the transistors M1 to M5, the leak resistance of the transistors M1 to M4 is smaller than that of the transistor M5.
The output (voltages V1 and V2) of No. 4 changes toward the ground voltage side instead of the Vdd1 voltage side, and the change at this time is performed while maintaining the magnitude relationship. Therefore, the information immediately before power down is held in the latch circuit 5, and this information is transmitted to the output terminal 2 via the inverters 6 and 7.

In the non-operating power line, the inverters 3 and 4 are pMOS transistors M5 having a high threshold voltage.
Since the latch circuit 5 is a high threshold voltage transistor which constitutes the latch circuit 5 and the inverters 6 and 7 are also cut off by the high threshold voltage transistor which constitutes the latch circuit 5, an increase in current consumption due to a leak current is prevented. It can be avoided.

FIG. 2 is a diagram showing the characteristics of the level conversion circuit of the first embodiment, showing the dependence of the delay time (tpd) on the power supply voltage (Vdd1). In the conventional level conversion circuit as shown in FIG. 7 which uses multiple stages of inverters composed of high threshold voltage MOS transistors, the delay time increases sharply when the power supply voltage drops from 3V to 1V. In the level conversion circuit of the first embodiment, the increase of the delay time is small, and it can be seen that the 1V power supply can reduce the delay time to 1/4 of the conventional one.

[Second Embodiment] FIG. 3 is a circuit diagram of a level conversion circuit of the second embodiment, which is a modification of the first embodiment. Here, the pMOS of the inverter 3
The source of the transistor M1 is separated from the source of the transistor M3 of the inverter 4 to directly supply the power supply voltage Vdd1.
And the source of the nMOS transistor M2 is connected to the ground via the nMOS transistor M14 having a high threshold voltage. The power-down control signal CS is applied to the gate of the nMOS transistor M14.

In the level conversion circuit of the second embodiment,
Due to the non-operation, the power-down control signals CSB and CS are applied to the nMOS transistor M14,
The pMOS transistor M5 becomes non-conductive. At this time,
Although the leakage resistance of the low threshold voltage transistors M1 to M4 is small, the high threshold voltage transistors M5 and M1
Since the leakage resistance of the inverter 4 is large, the output voltage (V1) of the inverter 3 is finally at a high level (Vdd1 = 1V) and the output voltage (V2) of the inverter 4 is at a low level (ground voltage = 0).
Fixed to V).

As a result, the output voltage of the latch circuit 5 and the output voltage of the output terminal 2 become low level (0V). That is, in this level conversion circuit, in addition to the above-mentioned high-speed operation and low leakage current, there is an excellent effect that the output voltage during non-operation can be fixed at a low level.

In the second embodiment, a high threshold voltage pMOS transistor receiving the power down control signal CSB at its gate is connected in series between the source of the transistor M1 on the side of the inverter 3 and the power supply Vdd1. A high threshold voltage nMOS transistor receiving the power-down control signal CS at its gate may be connected in series between the source of the transistor M4 on the side of the inverter 4 and the ground. At this time, conversely to the above, the voltage V1 is 0 during non-operation.
At V, the voltage V2 is fixed at 1V.

[Third Embodiment] FIG. 4 is a circuit diagram of a level conversion circuit according to a third embodiment. Reference numeral 11 is an input terminal, and 12 is an output terminal. Here, the pMOS transistor M1
5. CMOS inverter consisting of nMOS transistor M16 and nMOS transistor M connected in series to it
An inverter 13 is composed of 17 and a CMOS inverter composed of a pMOS transistor M18 and an nMOS transistor M19 and an nMOS connected in series with the CMOS inverter.
An inverter 14 is composed of the transistor M20 and p
MOS transistor M21, nMOS transistor M2
The CMOS inverter consisting of 2 and the pMOS transistor M23 constitute the inverter 15, and each CMOS inverter is cascade-connected between the input terminal 11 and the output terminal 12 so that the output of the preceding stage is connected to the input of the following stage. ing.

Then, the source of the nMOS transistor M20 is connected to the source follower of the gate of the nMOS transistor 17 at the previous stage, and the nMOS transistors M17 and M20 are connected.
Of the pMOS transistor M21, the gate of the nMOS transistor M20, and the source of the pMOS transistor M21.
It is connected to the drain (pseudo power supply) of the transistor M23. A power down control signal CSB is supplied to the gate of the pMOS transistor M23, and a power supply voltage Vdd is supplied to the source thereof.
2 (= 3V) is applied.

In the above, low threshold voltage transistors are used as the transistors M15 and M16 of the first stage inverter 13, and high threshold voltage transistors are used as the other transistors M17 to M23.

The operation of the level conversion circuit of the third embodiment is performed as follows. First, at the time of operation, the transistor M23 becomes conductive. At this time, the source potential (V4) of the transistor M20 is higher than the power supply voltage Vdd2 (3V) by the threshold voltage of the transistor M20 (since the circuit is connected to the source side, the threshold voltage is higher than the bare threshold voltage). It will be slightly larger.) It will be reduced to about 2V. The source potential (V2) of the transistor M17 is about 1V, which is lower than the voltage V4 by the threshold value of the transistor M17.

Therefore, the transistor M of the inverter 13
The source voltage (V3) of the inverter 15 is about 1V, the source voltage (V4) of the transistor M18 of the inverter 14 is about 2V, and the source voltage of the transistor M21 of the inverter 15 is about 3V.
It becomes V. Since the transistors M15 and M16 of the CMOS inverter of the first-stage inverter 13 have a low threshold voltage, high-speed operation is possible even when the power supply voltage is 1V, and thus high-speed level conversion from 1V to 3V is possible.

The power consumption during the above operation is greatly reduced as compared with the conventional circuit shown in FIG. 7, because the level conversion circuit is a circuit in which the input amplitude (operating voltage) is gradually increased. Is possible. The reason will be described below.

The operating frequency is f, the power supply voltage is Vdd2, and the output capacitances of the inverters 13, 14 and 15 are C13 and C1, respectively.
4 and C15, the power consumption P1 is P1 = (C13 · 1/3 + C14 · 2/3 + C15) Vdd2 ² · f (1) Since the signal amplitudes (power supply voltages) of the CMOS inverters of the inverters 13, 14, and 15 are sequentially increased to 1V, 2V, and 3V, the capacitance C of the final-stage inverter 15 is increased.
Since the coefficient C1 of the first-stage inverter 13 is "1/3" and the coefficient C14 of the middle-stage inverter 14 is "2/3", the parentheses of the formula (1) are as follows. Is represented.

Here, the output capacitance is C13≈C14≈C1
If it is approximated to 5≈C, the power consumption of the level conversion circuit of the third embodiment is P1 = 2C · Vdd2 ² · f (2).

On the other hand, in the power consumption P2 of the conventional level conversion circuit shown in FIG. 7, the output capacity of the inverter 44 is C44.
The output capacitance of the latch circuit 43 on the transistors M41 and M42 side is C43a, the output capacitance of the M43 and M44 side is C43b, and the output capacitance of the inverter 45 is C45.
If the output capacitance of the inverter 46 is C46, then P2 = (C44.1 / 3 + C43a + C43b + C45 + C46) Vdd2 ² .f (3). The output capacitance C44 of the inverter 44 is the power supply voltage V
Since it is dd1 (= 1V), its coefficient is "1/3".

Here, C44≈C43a≈C43b≈C
If approximated as 45≈C46 = C, the power consumption P2 of this conventional level conversion circuit is P2 = (4 + 1/3) C · Vdd2 ² · f (4)

From the above equations (2) and (4), it is understood that the level conversion circuit of this embodiment can reduce the power consumption during operation to 1/2 or less as compared with the conventional circuit.

When not operating, the pMOS transistor M2
Since 3 is non-conductive, even if a low threshold MOS transistor is used for the first-stage inverter 13, the leak current does not increase as in the first and second embodiments.

FIG. 5 shows the dependence of the consumption current (μA) of the level conversion circuit of the third embodiment on the operating frequency (MHz). Since the level conversion circuit of the third embodiment has a circuit configuration in which the signal amplitude is gradually increased, the current consumption can be reduced as compared with the level conversion circuit of the conventional example.
In particular, when the operating frequency is 10 MHz, it can be seen that the current consumption can be reduced to 1/2 or less as compared with the conventional level conversion circuit.

[Fourth Embodiment] FIG. 6 is a circuit diagram of a level conversion circuit according to a fourth embodiment. This level conversion circuit is a development example of the level conversion circuit of the third embodiment. Here, the CMOS inverter composed of the pMOS transistor M24 and the nMOS transistor M25 and the nMOS transistor M26 make the inverter 16 of the first stage a pMO.
A CMOS inverter composed of an S transistor M27 and an nMOS transistor M28, and an nMOS transistor M2
9, the second-stage inverter 17 is a CM including a pMOS transistor M30 and an nMOS transistor M31.
The OS inverter and the nMOS transistor M32 form a third
The inverter 18 of the stage is connected to the pMOS transistor M3.
3, a CMOS inverter composed of an nMOS transistor M34 and an nMOS transistor M35 to form a fourth-stage inverter 19, a pMOS transistor M36 and an nMO.
CMOS inverter composed of S-transistor M37 and p
5th stage inverter 2 with MOS transistor M38
0 respectively. The first to fifth inverters 16 to 20 are cascade-connected so that the output of the front stage is connected to the input of the rear stage.

The source of the nMOS transistor M35 is source-follower connected to the gate of the nMOS transistor 32 in the preceding stage, the source of the nMOS transistor M32 is source follower connected to the gate of the nMOS transistor 29 in the preceding stage, and the source of the nMOS transistor M29 is the nMOS of the preceding stage. A source follower is connected to the gate of the transistor 26, and nMOS transistors M26, M29, M3 are connected.
2, the drains of M35, the gate of the nMOS transistor M35, and the source of the pMOS transistor M36 are connected to the drain (pseudo power supply) of the pMOS transistor M38. This pMOS transistor M38
The power-down control signal CSB is applied to the gate of and the power supply voltage Vdd3 (= 5V) is applied to the source.

Here, the transistors M24, M25,
Low threshold voltage transistors are used for M27 and M28, and high threshold voltage transistors are used for the other transistors M26 and M29 to M38.

In this level conversion circuit, during operation, 4V appears at the source of the transistor M35, 3V appears at the source of the transistor M32, 2V appears at the source of the transistor M29, and 1V appears at the source of the transistor M26. Input signal input to terminal 11 is 1V
The amplitude, the 2V amplitude, the 3V amplitude, the 4V amplitude, and the 5V amplitude are sequentially converted and appear at the output terminal 12. The function and effect are similar to those of the level conversion circuit of the third embodiment.

In the above third and fourth embodiments, the source follower connected nMOS transistors M17 and M2 are used.
Although high threshold voltage transistors are used for 0, M26, M29, M32 and M35, low threshold voltage transistors may be used depending on how the power supply voltage is set. Further, here, 0.2 V is shown as an example of the low threshold voltage and 0.6 V is shown as an example of the high threshold voltage, but the present invention is not limited to this. Further, the transistors used are not limited to the two types of transistors having a low threshold voltage and transistors having a high threshold voltage, and it is also possible to use three or more types of transistors having different threshold voltages. Of course.

[0046]

As described above, according to the first aspect of the present invention, the CMOS inverter of the first inverter group has a low threshold voltage lower than the threshold voltage of the latch circuit or the CMOS inverter of the second inverter group. Since it is composed of, the high speed operation is possible, and the low threshold voltage MOS
Since a high threshold voltage MOSFET is connected in series to the FET, a leak current when not in operation can be effectively cut off and power consumption can be reduced. That is, the first invention uses MOSFETs having different threshold voltages and uses a low threshold voltage M.
High-speed operation is realized by OSFET and MO of high threshold voltage
The SFET achieves low power consumption.

According to the second invention, in addition to the effect of the first invention, a plurality of CMOs in which the output of the preceding stage is connected to the input of the following stage are provided.
Since the power supply voltage of the S inverter is gradually increased and the signal amplitude is gradually increased, there is an advantage that the current consumption can be reduced not only during non-operation but also during operation.

Therefore, a dry battery power source driven LSI and 3V
Alternatively, it is extremely suitable as a level conversion circuit with an LSI driven by a 5V power supply.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a level conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the power supply voltage dependency of the delay time of the level conversion circuit of the first embodiment.

FIG. 3 is a circuit diagram of a level conversion circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a level conversion circuit according to a third embodiment of the present invention.

FIG. 5 is a characteristic diagram showing frequency dependence of current consumption during operation of the level conversion circuit according to the third embodiment.

FIG. 6 is a circuit diagram of a level conversion circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional level conversion circuit.

[Explanation of symbols]

1: Input terminal, 2: Output terminal, 3, 4: Inverter,
5: Latch circuit, 6, 7: Inverter, CSB, CS:
Power-down control signal, 11: input terminal, 12: output terminal, 13-20: inverter, 41: input terminal, 42:
Output terminal, 43: latch circuit, 44-46: inverter.

Claims (3)

[Claims] 1. A first inverter group including two or more inverters to which a signal at an input terminal is input, a latch circuit for inputting complementary outputs obtained by the first inverter group, and an output of the latch circuit. One inverter for outputting a signal to an output terminal, or a second inverter group consisting of two or more inverters in which the output of the preceding stage is connected to the input of the latter stage, and the first inverter group is set to a low threshold value. Voltage MOSF
A plurality of CMOS inverters made of ET, the high-potential power source side is commonly connected, the low-potential power source side is commonly connected, and the output of the preceding stage is connected to the input of the following stage, and a high threshold value connected in series with the plurality of CMOS inverters. Voltage MOSFET
And a power-down control signal for reducing current consumption during non-operation is connected to the gate of the high threshold voltage MOSFET, and the latch circuit and the second inverter group are set to a high threshold value. A MOSFET having a value voltage, a first power supply voltage is supplied to the first inverter group, and a second power supply voltage larger than the first power supply voltage is supplied to the latch circuit and the second inverter group. A level conversion circuit characterized by being supplied. 2. A first CMOS inverter composed of a low threshold voltage MOSFET and a first high threshold voltage serially connected to the high potential power source side of the first CMOS inverter. And a second CMOS inverter composed of a low threshold voltage MOSFET and the second CMOS
A second inverter having a high threshold voltage second MOSFET connected in series to the lower power supply side of the inverter and having the output of the first inverter connected to the input;
2. The level conversion circuit according to claim 1, wherein the gates of the first and second MOSFETs are replaced with those configured by connecting a power down control signal for reducing current consumption during non-operation. . 3. A first CMOS inverter comprising a plurality of inverters connected in n stages so that an output of a front stage is connected to an input of a rear stage, the first stage inverter being a first CMOS inverter composed of a MOSFET of a low threshold voltage and a first CMOS inverter. Of MOSFETs connected in series, the drain of the first MOSFET is connected to the pseudo power supply line, and the i-th inverter of the second and subsequent stages is connected to the low threshold voltage or higher threshold voltage. I-th CMOS inverter composed of voltage MOSFET and i-th MO
The i-th MOSF is formed by connecting SFETs in series.
The drain of ET is connected to the pseudo power supply line and the source is connected to the gate of the (i-1) th MOSFET, and the final-stage inverter is composed of a MOSFET having a threshold voltage higher than the low threshold voltage. nth CMOS
Inverter and nth MOSFET are connected in series, the source of the nth MOSFET is connected to the first power supply, and the drain is connected to the gate of the n-1th MOSFET and the pseudo power supply line. The level conversion circuit is characterized in that the gate is connected to a power-down control signal for reducing current consumption when not operating.