JP2013162311A - Level shifter circuit, load drive device, liquid crystal display device and television - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shifter circuit that dispenses with high voltage elements.SOLUTION: The level shifter circuit keeps gate-source, gate-drain or source-drain potential differences of a transistor P5 and a transistor P6 at an input stage of a control signal and a transistor N5 and a transistor N6 at an output stage of a control signal, within a predetermined range by means of a transistor P7 and a transistor P8 at a bias stage. A negative potential VBIAS (for example, -4.2 V) is applied to the bias stage, and a potential difference applied to the input stage and the output stage is at most a potential difference (6 V) between a positive potential VDDL (for example, 1.8 V) and the negative potential VBIAS. This can dispense with high voltage elements to configure a level shifter circuit comprising middle voltage elements having a withstanding voltage of, for example, 6.5 V.

Description

  The present invention relates to a level shifter circuit, a load driving device (for example, a liquid crystal driving device) using the level shifter circuit, a liquid crystal display device, and a television.

  FIG. 4 is a circuit diagram showing a conventional example of a level shifter circuit. As shown in FIG. 4, the conventional level shifter circuit includes inverters INVa and INVb, P-channel MOS field effects Pa to Pd, and N-channel MOS field effect transistors Na to Nd. It had been. In the level shifter circuit configured as described above, the inverters INVa and INVb are connected between the application terminal of the positive potential VDDI (for example, 1.6 V) and the application terminal of the ground potential VSS (0 V), respectively. Pa, Pb, Na, and Nb are respectively connected between the application terminal of the positive potential VDDI and the application terminal of the negative potential MVDD (for example, −6.0 V), and the transistors Pc, Pd, Nc, and Nd are Each was connected between the application terminal of the ground potential VSS and the application terminal of the negative potential MVDD.

    As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2000-195284 A

  Certainly, in the case of the conventional level shifter circuit, an input signal IN pulse-driven between the ground potential VSS and the positive potential VDDI is used as an output signal OUT pulse-driven between the ground potential VSS and the negative potential MVDD. Can be output after being converted to.

  However, the conventional level shifter circuit is configured to receive the input signal IN pulse-driven between the ground potential VSS and the positive potential VDDI at the gates of the P-channel MOS field effect transistors Pa and Pb. In order to reliably turn on and off Pa and Pb, it is necessary to apply the positive potential VDDI instead of the ground potential VSS to the sources of the transistors Pa and Pb.

  As described above, in the conventional level shifter circuit in which the positive potential VDDI is applied to the sources of the transistors Pa and Pb, the gates and sources of the transistors Pa to Pc and the transistors Na to Nc, the gates and drains, Since a maximum potential difference (for example, 7.6 V) between the positive potential VDDI and the negative potential MVDD is applied between the drains, the transistors Pa to Pc and the transistors Na to Nc can withstand the above potential difference. The high voltage element to be obtained (for example, 28V breakdown voltage) had to be used.

  However, the high withstand voltage element has a larger gate capacity than a medium withstand voltage element (for example, 6.5V withstand voltage) or a low withstand voltage element (for example, 1.8V withstand voltage) having a lower withstand voltage, and a large amount of current is charged and discharged. As a result, the ON / OFF response speed is reduced and the through current is increased accordingly (as a result, the operating current consumed in the entire level shifter circuit is increased).

  In addition, the high breakdown voltage element has a layout area larger than that of the medium breakdown voltage element and the low breakdown voltage element, which has been a factor that hinders downsizing of the semiconductor device. In particular, when a large number of level shifter circuits have to be arranged within the width of the liquid crystal panel as in a liquid crystal driver IC, the level shifter circuit is enlarged in the width direction (long side direction) due to the PAD pitch limitation. Therefore, in order to secure the layout area, the level shifter circuit has to be enlarged in the vertical direction (short side direction), and it is difficult to meet the demand for a framed LCD panel. .

  In view of the above problems, the present invention provides a level shifter circuit capable of realizing reduction of power consumption, improvement of response speed, and reduction of layout area, without requiring a high-voltage element, and An object of the present invention is to provide a load driving device, a liquid crystal display device, and a television using the TV.

  To achieve the above object, a level shifter circuit according to the present invention receives an input signal that is pulse-driven between a ground potential and a first positive potential, and between the first positive potential and the first negative potential. A first level shifter circuit for generating a pulse-driven first output signal; and a first level shifter circuit that receives the first output signal and is pulse-driven between the ground potential and a second negative potential lower than the first negative potential. A second level shifter circuit that generates a two-output signal, wherein the second level shifter circuit is provided between the input stage of the first output signal and the output stage of the second output signal. In addition, a bias stage that receives the input of the first negative potential is included (first configuration).

  The level shifter circuit having the first configuration may have a configuration (second configuration) in which the first output signal and the second output signal are input and output in a differential format.

  Further, in the level shifter circuit having the second configuration, the second level shifter circuit is configured such that a source is connected to a ground potential application terminal and a gate is connected to a first differential input terminal of the first output signal. A channel-type first transistor, a P-channel type second transistor having a source connected to a ground potential application terminal and a gate connected to a second differential input terminal of the first output signal, and a source being the first A P-channel third transistor connected to the drain of one transistor, a gate connected to the first negative potential application terminal, a source connected to the drain of the second transistor, and a gate connected to the first negative potential; A P-channel fourth transistor connected to the application terminal of the second transistor, a drain connected to the drain of the third transistor, a source connected to the application terminal of the second negative potential, N-channel fifth transistor connected to the drain of the fourth transistor, the drain connected to the drain of the fourth transistor, the source connected to the application terminal of the second negative potential, and the gate A plurality of N-channel sixth transistors connected to the drain of the third transistor; and a voltage that appears at a connection node between the drain of the fourth transistor and the drain of the sixth transistor as the second output signal. An inverter may be used as a configuration (third configuration).

  Further, in the level shifter circuit having the third configuration, the plurality of transistors forming the second level shifter circuit have a higher withstand voltage than a high withstand voltage element that can withstand a potential difference between the first positive potential and the second negative potential. It is preferable to adopt a structure (fourth structure) characterized by being a low element.

  In the level shifter circuit having the fourth configuration, the first level shifter circuit inputs / outputs the input signal and the first output signal in a differential format (fifth configuration). Good.

  In the level shifter circuit having the fifth configuration, the first level shifter circuit has a source connected to the application terminal of the first positive potential and a gate connected to a first differential input terminal of the input signal. A P-channel seventh transistor, a P-channel eighth transistor having a source connected to the first positive potential application terminal and a gate connected to the second differential input terminal of the input signal; An N-channel ninth transistor having a drain connected to the first negative potential application terminal, a drain connected to the drain of the seventh transistor, a gate connected to the drain of the eighth transistor, and a source connected to the first transistor N-channel type tenth connected to the negative potential application end, drain connected to the drain of the eighth transistor, and gate connected to the drain of the seventh transistor. A voltage appearing between a drain of the seventh transistor and a drain of the ninth transistor, and a voltage appearing at a connection node between the drain of the eighth transistor and the drain of the tenth transistor. The first output signal may be output as a configuration (sixth configuration).

  The level shifter circuit having the sixth configuration receives a previous stage input signal pulse-driven between a ground potential and a second positive potential lower than the first positive potential, generates the input signal, and generates the input signal. A configuration (seventh configuration) may be provided which includes a pre-stage level shifter circuit for sending to the first level shifter circuit.

  The level shifter circuit having the seventh configuration may have a configuration (eighth configuration) in which the previous level shifter circuit inputs and outputs the previous stage input signal and the input signal in a differential format. .

  In the level shifter circuit having the eighth configuration, the previous level shifter circuit has an N-channel type in which a source is connected to a ground potential application terminal and a gate is connected to a first differential input terminal of the previous input signal. An N-channel twelfth transistor having a source connected to a ground potential application terminal and a gate connected to a second differential input terminal of the preceding input signal, and a source connected to the first positive potential. The thirteenth transistor whose drain is connected to the drain of the eleventh transistor, the gate is connected to the drain of the twelfth transistor, the source is connected to the positive potential application terminal, and the drain Is connected to the drain of the twelfth transistor, and the fourteenth transistor has a gate connected to the drain of the eleventh transistor. The voltage appearing at the connection node between the drain of the eleventh transistor and the drain of the thirteenth transistor and the voltage appearing at the connection node between the drain of the twelfth transistor and the drain of the fourteenth transistor are output as the input signal. It is good to use the structure (9th structure) characterized by doing.

  The load driving device according to the present invention includes m level shifter circuits that level-shift m input signals (m is an integer of 2 or more) to generate m output signals; A digital / analog conversion circuit that receives a signal as an m-bit digital signal, converts the signal into an analog signal, and outputs the analog signal; and an amplifier circuit that supplies the analog signal to the load as a load drive signal; An integer greater than or equal to 1) of the plurality of level shifter circuits, wherein an input signal that is pulse-driven between a ground potential and a positive potential is transmitted between the ground potential and the negative potential. The level shifter circuit for converting to a pulse-driven output signal is a level shifter circuit having any one of the first to ninth configurations (tenth configuration).

Further, the load driving device having the tenth configuration has a configuration (eleventh configuration) in which the load is a liquid crystal pixel.

  A liquid crystal display device according to the present invention includes a load driving device having an eleventh configuration and liquid crystal pixels driven by the load driving device (twelfth configuration). It is good to.

  The television according to the present invention includes a tuner unit that selects a broadcast signal of a desired channel from a received signal, a decoder unit that generates a video signal and an audio signal from the broadcast signal selected by the tuner, and the video signal. A display unit that outputs the image as a video, a speaker unit that outputs the audio signal as audio, an operation unit that receives a user operation, an interface unit that receives an external input signal, and a control that comprehensively controls the operation of each unit. And a power supply unit that supplies power to each of the above-described units, and the display unit is a liquid crystal display device having a twelfth configuration (13th configuration).

  According to the present invention, it is possible to realize reduction of power consumption, improvement of response speed, and reduction of layout area without requiring a high voltage element.

The block diagram which shows the level shifter circuit which concerns on this invention Circuit diagram showing a level shifter circuit according to the present invention Schematic diagram showing a configuration example of a liquid crystal display device using the level shifter circuit according to the present invention. Circuit diagram showing a conventional example of a level shifter circuit Block diagram showing one configuration example of a television equipped with a level shifter circuit Front view of a TV equipped with a level shifter circuit Side view of a TV with a level shifter circuit Rear view of a TV with a level shifter circuit

<Liquid crystal display device>
FIG. 3 is a schematic diagram showing a configuration example of a liquid crystal display device using the level shifter circuit according to the present invention. As shown in FIG. 3, the liquid crystal display device of this configuration example includes a glass substrate 100, an MPU [Micro-Processing Unit] 200, and a flexible cable 300.

  A liquid crystal pixel 110 is formed on the glass substrate 100, and a liquid crystal driving device 120 (liquid crystal driver IC) is directly mounted in a blank area (frame area) by a COG [Chip On Glass] method.

  The liquid crystal driving device 120 includes a source driver unit, a gate driver unit, a common driver unit, and the like as means for driving the liquid crystal pixels 110. In particular, the source driver unit of the liquid crystal driving device 120 is illustrated in FIG. As shown, it includes a level shifter circuit group 121, a digital / analog conversion circuit group 122, a source amplifier group 123, and a logic unit 124.

  More specifically, the source driver unit of the liquid crystal driving device 120 includes m level shifters for level-shifting m system input signals (where m is an integer of 2 or more) to generate m system output signals. Circuit (depicted as a single block element labeled “LS × m” in the example of FIG. 3) and m output signals as m-bit digital signals, which are converted into analog signals An output digital / analog conversion circuit (illustrated as a block element labeled “DAC” in the example of FIG. 3) and a source amplifier circuit (in the example of FIG. 3) that supplies an analog signal to the liquid crystal pixel 11 as a source signal. , Depicted as a block element labeled “AMP”), and n sets (where n is an integer of 1 or more).

  Here, it is desirable that the source signal supplied to the liquid crystal pixel 110 as the liquid crystal drive signal is inverted in polarity between every predetermined frame from the viewpoint of preventing the liquid crystal pixel 110 from being burned. Therefore, in the liquid crystal drive device 120 of the present embodiment, the first drive system (positive level shifter circuit, digital / analog conversion) that generates a positive source signal according to an input signal (video signal) from the logic unit 124. Circuit and source amplifier circuit) and a second drive system (negative level shifter circuit, digital / analog conversion circuit, and source amplifier circuit) for generating a negative polarity source signal are prepared separately. A configuration is adopted in which the liquid crystal pixels 110 are driven while alternately switching the. The level shifter circuit according to the present invention is suitably used as the above-described negative level shifter circuit, and the configuration thereof will be described later in detail.

  The MPU 200 is connected to the liquid crystal driving device 120 on the glass substrate 100 via the flexible cable 300, and receives control signals (source signal, gate signal, common signal, etc.) of the liquid crystal pixel 110 via the liquid crystal driving device 120. Output.

  The flexible cable 300 is a signal transmission path in which printed wiring is formed on a flexible thin film, and connectors for establishing electrical connection with the liquid crystal driving device 120 and the MPU 200 are provided at both ends thereof. Yes. In the example of FIG. 3, the configuration in which the liquid crystal driving device 120 is mounted on the glass substrate 100 by the COG method is described as an example. However, the configuration of the present invention is not limited to this, and the configuration is not limited to this. The liquid crystal driving device 120 may be mounted by a COF [Chip On Film] method.

<Level shifter circuit>
FIG. 1 is a circuit diagram showing a configuration example of a level shifter circuit according to an embodiment of the present invention.

  The level shifter circuit of this configuration example includes a previous level shifter circuit 10, a first level shifter circuit 20, a second level shifter circuit 30, a constant voltage source 40, an external terminal IN1, and an external terminal OUT1. The level shifter circuit has an application terminal for the positive potential VDDL, an application terminal for the ground potential GND, and an application terminal for the negative potential VDDM. The constant voltage source 40 may be externally connected to the level shifter circuit without being included in the level shifter circuit.

  The pre-stage level shifter circuit 10 receives a control signal S1 (pre-stage input signal) from the external terminal IN1. The control signal S1 is a digital signal generated by a logic circuit (not shown) and pulse-driven between the positive potential VDDI (second positive potential) and the ground potential GND.

  The pre-stage level shifter circuit 10 is applied with a ground potential GND and a positive potential VDDL (first positive potential). The pre-stage level shifter circuit 10 generates a control signal S2 (input signal) from the control signal S1 using the ground potential GND and the positive potential VDDL, and outputs the control signal S2 to the first level shifter circuit 20. The control signal S2 is a digital signal that is pulse-driven between the positive potential VDDL and the ground potential GND.

  The first level shifter circuit 20 is applied with the positive potential VDDL. A negative potential VBIAS (first negative potential) is applied from the constant voltage source 40. The first level shifter circuit 20 generates a control signal S3 (first output signal) from the control signal S2 using the positive potential VDDL and the negative potential VBIAS, and outputs the control signal S3 to the second level shifter circuit 30. The control signal S3 is a digital signal that is pulse-driven between the positive potential VDDL and the negative potential VBIAS.

  The second level shifter circuit 30 is applied with the ground potential GND, the negative potential VBIAS, and the negative potential VDDM (second negative potential). The second level shifter circuit 20 generates a control signal S4 (second output signal) from the control signal S3 using the ground potential GND and the negative potential VDDM, and outputs the control signal S4 to the external terminal OUT1. The control signal S4 is a digital signal that is pulse-driven between the ground potential GND and the negative potential VDDM. The second level shifter circuit 30 performs an operation (details will be described later) for controlling conduction between the input stage of the control signal S3 and the output stage of the control signal S4 using the negative potential VBIAS.

  The constant voltage source 40 generates a negative potential VBIAS, which is a negative constant potential, using an operational amplifier, a transistor, and the like (not shown), and sends them to the first level shifter circuit 20 and the second level shifter circuit 30.

  In this embodiment, as an example of each potential, the positive potential VDD is 1.2 V, the positive potential VDDL is 1.8 V, the ground potential is 0 V, the negative potential VBIAS is −4.2 V, and the negative potential VDDM is −6 V. The explanation will be given.

  Next, a detailed circuit configuration of the level shifter circuit configured as described above will be described. FIG. 2 is a circuit diagram showing a circuit configuration of a level shifter circuit according to an embodiment of the present invention.

  The front level shifter circuit 10 includes P-channel MOS field effect transistors P1 and P2 (hereinafter referred to as “transistors P1 and P2”) and N-channel MOS field effect transistors N1 and N2 (hereinafter referred to as “transistors N1 and N2”). And having. The above transistors are all low breakdown voltage elements.

  The first level shifter circuit 20 includes P-channel MOS field effect transistors P3 and P4 (hereinafter referred to as “transistors P3 and P4”) and N-channel MOS field effect transistors N3 and N4 (hereinafter referred to as “transistors N3 and N4”). And). The above transistors are all medium voltage devices.

  The second level shifter circuit 30 includes P-channel MOS field effect transistors P5, P6, P7 and P8 (hereinafter referred to as “transistors P5, P6, P7 and P8”) and N-channel MOS field effect transistors N5 and N6 (hereinafter referred to as “transistors P5, P6, P7 and P8”). , “Transistors N5 and N6”. The transistors P5 and P6 operate as a differential input stage for the control signal S3. Transistors P7 and P8 operate as a bias stage. The transistors N5 and N6 operate as a differential output stage of the control signal S4. The above transistors are all medium voltage devices.

  The second level shifter circuit 30 includes P-channel MOS field effect transistors P9 and P10 (hereinafter referred to as “transistors P9 and P10”) and N-channel MOS field effect transistors N7 and N8 (hereinafter referred to as “transistors N7 and N8”). And). The above transistors are all low breakdown voltage elements.

  The external terminal IN and the external terminal INB describe the external terminal IN1 in FIG. 1 in detail. The external terminal IN and the external terminal INB are input terminals for differentially inputting the control signal S1. The external terminal INB is an inverting input terminal of the external terminal IN.

  The external terminal OUT and the external terminal OUTB describe the external terminal OUT1 in FIG. 1 in detail. The external terminal OUT and the external terminal OUTB are output terminals for differentially outputting the control signal S4. The external terminal OUTB is an inverted output terminal of the external terminal OUT.

  A connection form of each component described above will be described. First, the front level shifter circuit 10 will be described. The gate of the transistor N1 (the eleventh transistor) is connected to the external terminal IN. The source of the transistor N1 is connected to the application terminal of the ground potential GND. The gate of the transistor N2 (the twelfth transistor) is connected to the external terminal INB. The source of the transistor N2 is connected to the application terminal of the ground potential GND.

  The drain of the transistor P1 (13th transistor) is connected to the drain of the transistor N1. The source of the transistor P1 is connected to the application terminal of the positive potential VDDL. The gate of the transistor P1 is connected to a connection node between the drain of the transistor P2 and the drain of the transistor N2.

  The drain of the transistor P2 (14th transistor) is connected to the drain of the transistor N2. The source of the transistor P2 is connected to the application terminal of the positive potential VDDL. The gate of the transistor P2 is connected to a connection node between the drain of the transistor P1 and the drain of the transistor N1.

  Next, the first level shifter circuit 20 will be described. The source of the transistor P3 (seventh transistor) is connected to the application terminal of the positive potential VDDL. The gate of the transistor P3 is connected to a connection node between the drain of the transistor P2 and the drain of the transistor N2.

  The source of the transistor P4 (eighth transistor) is connected to the application terminal for the positive potential VDDL. The gate of the transistor P4 is connected to a connection node between the drain of the transistor P1 and the drain of the transistor N1.

  The source of the transistor N3 (the ninth transistor) is connected to the application terminal for the negative potential VBIAS. The drain of the transistor N3 is connected to the drain of the transistor P3. The gate of the transistor P3 is connected to a connection node between the drain of the transistor P4 and the drain of the transistor N4.

  The source of the transistor N4 (tenth transistor) is connected to the application terminal of the negative potential VBIAS. The drain of the transistor N4 is connected to the drain of the transistor P4. The gate of the transistor P4 is connected to a connection node between the drain of the transistor P3 and the drain of the transistor N3.

  Next, the second level shifter circuit 30 will be described. The source of the transistor P5 (first transistor) is connected to the application terminal of the ground potential GND. The gate of the transistor P5 is connected to a connection node between the drain of the transistor P4 and the drain of the transistor N4.

  The source of the transistor P6 (second transistor) is connected to the application terminal of the ground potential GND. The gate of the transistor P6 is connected to a connection node between the drain of the transistor P3 and the drain of the transistor N3.

  The source of the transistor P7 (third transistor) is connected to the drain of the transistor P5. The gate of the transistor P7 is connected to the application terminal for the negative potential VBIAS. The source of the transistor P8 (fourth transistor) is connected to the drain of the transistor P6. The gate of the transistor P8 is connected to the application terminal for the negative potential VBIAS.

  The source of the transistor N5 (fifth transistor) is connected to the application terminal of the negative potential VDDM. The drain of the transistor N5 is connected to the drain of the transistor P7. The gate of the transistor N5 is connected to a connection node between the drain of the transistor P8 and the drain of the transistor N6.

  The source of the transistor N6 (sixth transistor) is connected to the application terminal for the negative potential VDDM. The drain of the transistor N6 is connected to the drain of the transistor P8. The gate of the transistor N6 is connected to a connection node between the drain of the transistor P7 and the drain of the transistor N5.

  The source of the transistor P9 is connected to the application terminal of the ground potential GND. The gate of the transistor P9 is connected to a connection node between the drain of the transistor P8 and the drain of the transistor N6.

  The drain of the transistor N7 is connected to the drain of the transistor P9. The gate of the transistor N7 is connected to a connection node between the drain of the transistor P8 and the drain of the transistor N6. The source of the transistor N7 is connected to the application terminal for the negative potential VDDM.

  The source of the transistor P10 is connected to the application terminal of the ground potential GND. The gate of the transistor P10 is connected to a connection node between the drain of the transistor P9 and the drain of the transistor N7.

  The drain of the transistor N8 is connected to the drain of the transistor P10. The gate of the transistor N8 is connected to a connection node between the drain of the transistor P9 and the drain of the transistor N7. The source of the transistor N8 is connected to the application terminal for the negative potential VDDM.

  The external terminal OUT is connected to a connection node between the drain of the transistor P10 and the drain of the transistor N8. The external terminal OUTB is connected to a connection node between the drain of the transistor P9 and the drain of the transistor N7.

  Next, the operation of the level shifter circuit configured as described above will be described in detail. In the following description, the voltage appearing at the connection node between the drain of the transistor P1 and the drain of the transistor N1 is V1, the voltage appearing at the connection node between the drain of the transistor P2 and the drain of the transistor N2 is V2, and the drain of the transistor P3 is The voltage appearing at the connection node between the drain of the transistor N3 is V3, the voltage appearing at the connection node between the drain of the transistor P4 and the drain of the transistor N4 is V4, and the voltage appearing at the connection node between the drain of the transistor P7 and the drain of the transistor N5. V5, the voltage appearing at the connection node between the drain of the transistor P8 and the drain of the transistor N6 is V6, the voltage appearing at the connection node between the drain of the transistor P9 and the drain of the transistor N7 is V7, and the drain of the transistor P10 The voltage appearing at the connection node between the drain of the transistor N8 and so V8, will be denoted by a reference sign on each part of the node voltage.

  First, the operation of the previous level shifter circuit 10 will be described. In the present embodiment, as an example, the operation when the logic level of the control signal S1 is High will be described. When the logic level of the control signal S1 is High, the positive potential VDD (1.2 V) is applied to the external terminal IN, and the ground potential GND (0 V) is applied to the external terminal INB.

  In this state, a potential difference exceeding the on-threshold voltage of the transistor N1 is generated between the source and the gate of the transistor N1, and the transistor N1 is turned on.

  As a result, the voltage V1 becomes equal to the ground potential GND, and the ground potential GND is applied to the gate of the transistor P2. Since the positive potential VDDL (1.8 V) is applied to the source of the transistor P2, a potential difference exceeding the on-threshold voltage of the transistor P2 is generated between the source and the gate of the transistor P2, and the transistor P2 is turned on.

  As a result, the voltage V2 becomes equal to the positive potential VDDL, and the positive potential VDDL is applied to the gate of the transistor P1. Since the positive potential VDDL is applied to the source of the transistor P1, there is no potential difference between the source and gate of the transistor P1, and the transistor P1 is turned off.

  On the other hand, since the ground potential GND is applied to both the source and the gate of the transistor N2, no potential difference occurs, and the transistor N2 is turned off.

  As described above, when the control signal S1 is High, the voltage V1 becomes the ground potential GND, and the voltage V2 becomes the positive potential VDDL. The reverse is true when the control signal S1 is Low. As a result, the voltage V1 and the voltage V2 are differentially output to the first level shifter circuit 20 as the control signal S2. That is, the control signal S2 is a digital signal that is pulse-driven between the positive potential VDDL and the ground potential GND.

  Next, the operation of the first level shifter circuit 20 will be described. In the above example, since the voltage V2 becomes the positive potential VDDL, no potential difference is generated between the source and the gate of the transistor P3, and the transistor P3 is turned off. On the other hand, since the voltage V1 becomes the ground potential GND, a potential difference exceeding the on-threshold voltage of the transistor P4 is generated between the source and the gate of the transistor P4, and the transistor P4 is turned on.

  As a result, the voltage V4 becomes the positive potential VDDL, and the positive potential VDDL is applied to the gate of the transistor N3. Since the negative potential VBIAS (−4.2 V) is applied to the source of the transistor N3, a potential difference exceeding the on-threshold voltage of the transistor N3 is generated between the source and gate of the transistor N3, and the transistor N3 is turned on. .

  Since the transistor P3 is off, the voltage V3 becomes a negative potential VBIAS, and the negative potential VBIAS is applied to the gate of the transistor N4. Since the negative potential VBIAS is applied to the source of the transistor N4, no potential difference occurs, and the transistor N4 is turned off.

  As described above, when the control signal S1 is High, the voltage V3 is the negative potential VBIAS and the voltage V4 is the positive potential VDDL. The reverse is true when the control signal S1 is Low. As a result, the voltage V3 and the voltage V4 are differentially output to the second level shifter circuit 30 as the control signal S3. That is, the control signal S3 is a digital signal that is pulse-driven between the positive potential VDDL and the negative potential VBIAS.

  Next, the operation of the second level shifter circuit 30 will be described. In the above example, since the voltage V4 becomes the positive potential VDDL, a potential difference exceeding the on-threshold voltage (for example, 2V) of the transistor P5 does not occur between the source and gate of the transistor P5, and the transistor P5 is turned off. On the other hand, since the voltage V3 is the negative potential VBIAS, a potential difference exceeding the on-threshold voltage of the transistor P6 is generated between the source and the gate of the transistor P6, and the transistor P6 is turned on.

  As a result, the ground potential GND is applied to the source of the transistor P8. Since the negative potential VBIAS is applied to the gate of the transistor P8, a potential difference exceeding the on-threshold voltage of the transistor P8 is generated between the source and the gate of the transistor P8, and the transistor P8 is turned on.

  At this time, since the transistor P5 is off, the voltage appearing between the drain of the transistor P5 and the source of the transistor P7 is indefinite. However, since the negative potential VBIAS is applied to the gate of the transistor P7, the voltage is not lower than the negative potential VBIAS due to the static characteristics of the transistor P7. For this reason, a voltage lower than the negative potential VBIAS is not applied to the drain of the transistor P5.

  Therefore, the maximum potential difference (6 V) between the positive potential VDDL (1.8 V) and the negative potential VBIAS (−4.2 V) with respect to the gate-source, the gate-drain, or the source-drain of the transistor P5. It is applied only up to. Therefore, a medium withstand voltage element (for example, 6.5V withstand voltage) can be used for the transistor P5.

  Note that when the control signal S1 is Low, the voltage appearing between the drain of the transistor P6 and the source of the transistor P8 is indefinite, but since the negative potential VBIAS is applied to the gate of the transistor P8, the same as above. In addition, a potential difference exceeding 6 V is not applied between the gate and source of the transistor P6, between the gate and drain, or between the source and drain.

  Returning to the description of the operation of the second level shifter circuit 30, when the transistor P6 is on, the voltage V6 becomes the ground potential GND, and the ground potential GND is applied to the gate of the transistor N5. Since the negative potential VDDM (−6 V) is applied to the source of the transistor N5, a potential difference exceeding the on-threshold voltage of the transistor N5 is generated, and the transistor N5 is turned on.

  When the transistor N5 is turned on, the voltage V5 becomes the negative potential VDDM, and the negative potential VDDM is applied to the gate of the transistor N6. Since the negative potential VDDM is applied to the source of the transistor N6, no potential difference occurs, and the transistor N6 is turned off. Note that when the control signal S1 is Low, the on / off state of the transistor N5 and the transistor N6 is inverted, so that the voltage V6 becomes the negative potential VDDM. Hereinafter, a case where the control signal S1 is High and the voltage V6 is the ground potential GND will be described as an example.

  The voltage V6 is applied to the gates of the transistor P9 and the transistor N7. Since the ground potential GND is applied to the source of the transistor P9, no potential difference is generated between the gate and the source of the transistor P9, and the transistor P9 is turned off.

  On the other hand, since the negative potential VDDM is applied to the source of the transistor N7, a potential difference exceeding the on-threshold voltage of the transistor N7 is generated between the source and gate of the transistor N7, and the transistor N7 is turned on.

  Since the transistor P9 is off and the transistor N7 is on, the voltage V7 has a negative potential VDDM, and the negative potential VDDM is applied to the gates of the transistors P10 and N8 and the external terminal OUTB. Since the ground potential GND is applied to the source of the transistor P10, a potential difference exceeding the on-threshold voltage of the transistor P10 is generated between the source and the gate of the transistor P10, and the transistor P10 is turned on.

  On the other hand, since the negative potential VDDM is applied to the source of the transistor N8, no potential difference is generated between the source and the gate of the transistor N8, and the transistor N8 is turned off. As a result, the voltage V8 becomes the ground potential GND, and the ground potential GND is applied to the external terminal OUT. Contrary to the above example, when the control signal S1 is Low and the voltage V6 is the negative potential VDDM, the voltage V7 is the ground potential GND and the voltage V8 is the negative potential VDDM. Thus, the transistor P9, the transistor P10, the transistor N7, and the transistor N8 operate as an inverter.

  With the above operation, the control signal S4 is differentially output with the voltage V8 as the external terminal OUT and the voltage V7 as the external terminal OUTB. That is, the control signal S4 is a digital signal that is pulse-driven between the ground potential GND and the negative potential VDDM.

  According to the level shifter circuit of the present embodiment described above, between the gate and source of the transistor P5 and the transistor P6 (hereinafter referred to as “input stage”), the transistor N5 and the transistor N6 (hereinafter referred to as “output stage”), A potential difference generated between the gate and the drain or between the source and the drain is within a predetermined range (in the above, 6 V) using the transistor P7 and the transistor P8 (hereinafter referred to as “bias stage”) connected to the negative potential VBIAS. Can be suppressed.

  If no bias stage is provided, the potential difference applied to each of the above transistors is a maximum potential difference (7.8 V) between the positive potential VDDL (1.8 V) and the negative potential VDDM (−6 V). It breaks in the medium voltage element with .5V breakdown voltage. Therefore, conventionally, for example, a high withstand voltage element having a withstand voltage of 28 V is used for the input stage and the output stage. However, according to the present embodiment, by providing the above-described bias stage, it is possible to configure a level shifter circuit with only a medium withstand voltage element.

  Further, according to the level shifter circuit of the present embodiment, it is possible to reduce the through current generated in the second level shifter circuit 30 when the logic level of the control signal S1 changes. More specifically, when the state of each transistor changes due to a change in logic level, an intermediate potential is applied in the middle of the transition, and a current flows temporarily. When this current flows into the constant voltage source 40 and exceeds the limit of current drawing of the constant voltage source 40, the negative potential VBIAS increases. As a result, the bias stage is turned off, and the current from the input stage to the output stage of the second level shifter circuit 30 is cut off. When the state transition is completed, the current flowing into the constant voltage source 40 is reduced, and the negative potential VBIAS can be maintained at the predetermined voltage (−4.2 V) again. Through the above operation, it is possible to reduce the through current when the logic level changes, and to reduce power consumption.

<Application to TV>
FIG. 5 is a block diagram showing a configuration example of a television equipped with the level shifter circuit of the present invention. 6 to 8 are a front view, a side view, and a rear view, respectively, of a television equipped with a level shifter circuit. The television X of this configuration example includes a tuner unit X1, a decoder unit X2, a display unit X3, a speaker unit X4, an operation unit X5, an interface unit X6, a control unit X7, and a power supply unit X8. Have.

  The tuner unit X1 selects a broadcast signal of a desired channel from a reception signal received by an antenna X0 externally connected to the television X.

  The decoder unit X2 generates a video signal and an audio signal from the broadcast signal selected by the tuner X1. The decoder unit X2 also has a function of generating a video signal and an audio signal based on an external input signal from the interface unit X6.

  The display unit X3 outputs the video signal generated by the decoder unit X2 as a video. As the display portion X3, a liquid crystal display panel, a plasma display panel, or the like can be used. As the display unit X3, the above-described level shifter circuit can be suitably used.

  The speaker unit X4 outputs the audio signal generated by the decoder unit as audio.

  The operation unit X5 is one of human interfaces that accept user operations. As the operation unit X5, a button, a switch, a remote controller, or the like can be used.

  The interface unit X6 is a front end that receives an external input signal from an external device (such as an optical disk player or a hard disk drive).

  The control unit X7 comprehensively controls the operations of the respective units X1 to X6. As the control unit X7, a CPU (central processing unit) or the like can be used.

  The power supply unit X8 supplies power to the units X1 to X7.

<Other variations>
The configuration of the present invention can be variously modified in addition to the above embodiment without departing from the spirit of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as restrictive. The technical scope of the present invention is not a description of the above-described embodiment, but a utility model registration request. It is to be understood that all the modifications that are indicated by the scope and are within the meaning and scope equivalent to the scope of the utility model registration request are included.

  For example, in the above embodiment, −4.2 V is exemplified as the negative potential VBIAS, but this value can be appropriately changed according to the design requirement. However, if the negative potential VBIAS is excessively increased (for example, −1 V), a potential difference necessary for turning on / off the transistors included in the bias stage may not be obtained. Therefore, a value considering this may be set. desirable.

  The present invention is a technique useful in reducing the number of high-voltage elements that form a level shifter circuit, and is suitable for a liquid crystal driving device in which a number of level shifter circuits must be arranged within the width of a liquid crystal panel, for example. Technology.

DESCRIPTION OF SYMBOLS 10 Previous level shifter circuit 20 1st level shifter circuit 30 2nd level shifter circuit 40 Constant voltage circuit 100 Glass substrate 110 Liquid crystal pixel 120 Liquid crystal drive device 121 Level shifter circuit group 122 Digital / analog conversion circuit group 123 Source amplifier circuit group 124 Logic part 200 MPU
X television X0 antenna X1 tuner unit X2 decoder unit X3 display unit X4 speaker unit X5 operation unit X6 interface unit X7 control unit X8 power supply unit S1 to S4 control signal N1, N2 N-channel MOS field effect transistor (low-voltage element)
N3-N6 N-channel MOS field effect transistor (medium voltage device)
N7, N8 N-channel MOS field effect transistor (low-voltage element)
P1, P2 P-channel MOS field effect transistor (low voltage element)
P3-P8 P-channel MOS field effect transistor (medium voltage device)
P9, P10 N-channel MOS field effect transistor (low voltage element)
V1 to V8 Voltage VDD Positive potential (second positive potential)
VDDL positive potential (first positive potential)
VBIAS negative potential (first negative potential)
VDDM Negative potential (second negative potential)
IN External terminal INB External terminal OUT External terminal OUTB External terminal

Claims (13)

A first level shifter circuit for receiving an input signal pulsed between a ground potential and a first positive potential and generating a first output signal pulsed between the first positive potential and a first negative potential; ,
A second level shifter circuit that receives the first output signal and generates a second output signal that is pulse-driven between the ground potential and a second negative potential lower than the first negative potential. A level shifter circuit,
The level shifter circuit, wherein the second level shifter circuit includes a bias stage that receives the input of the first negative potential between the input stage of the first output signal and the output stage of the second output signal. The level shifter circuit according to claim 1, wherein the second level shifter circuit inputs and outputs the first output signal and the second output signal in a differential format. The second level shifter circuit includes:
A P-channel first transistor having a source connected to a ground potential application terminal and a gate connected to a first differential input terminal of the first output signal;
A P-channel type second transistor having a source connected to a ground potential application terminal and a gate connected to a second differential input terminal of the first output signal;
A P-channel third transistor having a source connected to the drain of the first transistor and a gate connected to the application terminal of the first negative potential;
A P-channel fourth transistor having a source connected to the drain of the second transistor and a gate connected to the application terminal of the first negative potential;
An N-channel fifth transistor having a drain connected to the drain of the third transistor, a source connected to the application terminal of the second negative potential, and a gate connected to the drain of the fourth transistor;
An N-channel sixth transistor having a drain connected to the drain of the fourth transistor, a source connected to the application terminal of the second negative potential, and a gate connected to the drain of the third transistor;
The level shifter circuit according to claim 2, further comprising: a plurality of inverters that output, as the second output signal, a voltage appearing at a connection node between the drain of the fourth transistor and the drain of the sixth transistor. 4. The plurality of transistors forming the second level shifter circuit are elements having a lower withstand voltage than a high withstand voltage element that can withstand a potential difference between the first positive potential and the second negative potential. The level shifter circuit described in 1. The level shifter circuit according to claim 4, wherein the first level shifter circuit inputs and outputs the input signal and the first output signal in a differential format. The first level shifter circuit includes:
A P-channel seventh transistor having a source connected to the first positive potential application terminal and a gate connected to the first differential input terminal of the input signal;
A P-channel type eighth transistor having a source connected to the application terminal of the first positive potential and a gate connected to a second differential input terminal of the input signal;
An N-channel ninth transistor having a source connected to the first negative potential application terminal, a drain connected to the drain of the seventh transistor, and a gate connected to the drain of the eighth transistor;
An N-channel tenth transistor having a source connected to the first negative potential application end, a drain connected to the drain of the eighth transistor, and a gate connected to the drain of the seventh transistor; ,
The voltage appearing at the connection node between the drain of the seventh transistor and the drain of the ninth transistor and the voltage appearing at the connection node between the drain of the eighth transistor and the drain of the tenth transistor are output as the first output signal. The level shifter circuit according to claim 5, wherein: A pre-stage level shifter circuit that receives a pre-stage input signal that is pulse-driven between a ground potential and a second positive potential lower than the first positive potential, generates the input signal, and sends the input signal to the first level shifter circuit; The level shifter circuit according to claim 6. The level shifter circuit according to claim 7, wherein the front level shifter circuit inputs and outputs the front stage input signal and the input signal in a differential format. The preceding level shifter circuit is
An N-channel eleventh transistor having a source connected to a ground potential application terminal and a gate connected to the first differential input terminal of the preceding input signal;
An N-channel twelfth transistor having a source connected to a ground potential application terminal and a gate connected to the second differential input terminal of the preceding input signal;
The thirteenth transistor having a source connected to the application terminal of the first positive potential, a drain connected to the drain of the eleventh transistor, and a gate connected to the drain of the twelfth transistor;
A fourteenth transistor having a source connected to the first positive potential application end, a drain connected to the drain of the twelfth transistor, and a gate connected to the drain of the eleventh transistor;
Outputting the voltage appearing at the connection node between the drain of the eleventh transistor and the drain of the thirteenth transistor and the voltage appearing at the connection node between the drain of the twelfth transistor and the drain of the fourteenth transistor as the input signal. The level shifter circuit according to claim 8. m level shifter circuits that level-shift m input signals (m is an integer of 2 or more) to generate m output signals;
A digital / analog conversion circuit that receives the m output signals as m-bit digital signals, converts them into analog signals, and outputs them;
An amplifier circuit for supplying the analog signal to the load as a load drive signal;
And n sets (n is an integer equal to or greater than 1),
The level shifter circuit that converts an input signal pulse-driven between a ground potential and a positive potential into an output signal pulse-driven between the ground potential and a negative potential among the plurality of level shifter circuits. A load driving device characterized by being a level shifter circuit according to any one of? The load driving device according to claim 10, wherein the load is a liquid crystal pixel. 12. A liquid crystal display device comprising: the load driving device according to claim 11; and a liquid crystal pixel driven by the load driving device. A tuner unit that selects a broadcast signal of a desired channel from a received signal;
A decoder for generating a video signal and an audio signal from the broadcast signal selected by the tuner;
A display unit for outputting the video signal as a video;
A speaker unit for outputting the audio signal as audio;
An operation unit for accepting user operations;
An interface for receiving external input signals;
A control unit that comprehensively controls the operation of each of the above units;
A power supply unit for supplying power to each of the above units,
The display unit is the liquid crystal display device according to claim 12;
TV characterized by.

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