JP2002344301A - Semiconductor output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor output circuit which can output a high- speed signal with a preferred duty ratio even when a low-potential power supply Vdd is extremely low relative to the voltage of a high-potential power supply VddO. SOLUTION: A first level conversion circuit is provided for inputting a normal signal and an inverted signal produced by an inverted signal producing circuit, and an output stage circuit having a PMOS transistor and an NMOS transistor connected in series is provided. Of transistors constituting the output stage circuit, the output terminal of the first level conversion circuit is connected to the gate of the PMOS transistor connected to the power supply, and a normal signal and an inverted signal produced by the inverted signal producing circuit are level-converted by a second level conversion circuit. Of the transistors constituting the output stage circuit, the output terminal of the second level conversion circuit is connected to the gate of the lowest-stage NMOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS output stage circuit, and more particularly to a CMOS output stage circuit which operates at high speed even when an internal circuit of the chip operates at a very low power supply voltage as compared with the output signal voltage level of the chip. The present invention relates to a semiconductor output circuit.

[0002]

FIG. 4 shows a conventional semiconductor output circuit SC11.
FIG.

A conventional semiconductor output circuit SC11 comprises a driving circuit 10, an inversion signal generation circuit 20, and a level conversion circuit 3.
0 and an output stage circuit 40.

(Reference: A Fully Depleted CMOS / SIMO
X LSI Scheme Using a LVTTL-Compatible and Over-1
0000-VESD-Hardness I / O Circuit for Reduction in Ac
tiveand Static Power Consumption, Yusuke Ohtomo e
t.al., IEICE Trans. Electron.VOL.E80-C, p.458 Fi
g. 5, March 1997).

The input terminal of the drive circuit 10 is the input terminal of the conventional semiconductor output circuit SC11. The output terminal of the drive circuit 10 is connected to the input terminal of the inverted signal generation circuit 20. The non-inversion output terminal of the inversion signal generation circuit 20 is connected to a first input terminal of the level conversion circuit 30. The inversion output terminal of the inversion signal generation circuit 20 has a second input terminal of the level conversion circuit 30 and an output terminal. It is connected to the gate of the lowermost NMOS transistor of the stage circuit 40.

The output terminal of the level conversion circuit 30 is connected to the gate of a PMOS transistor located at the uppermost part of the output stage circuit 40. The output terminal of the output stage circuit 40 is
This is an output terminal of the conventional semiconductor output circuit SC11.

Further, the conventional semiconductor output circuit SC11 comprises:
A low-potential power supply Vdd and a high-potential power supply VddO are used.

The power supplies of the drive circuit 10 and the inverted signal generation circuit 20 are connected to a low potential power supply Vdd, and the ground terminals are connected to the ground terminal of the conventional semiconductor output circuit SC11. The power supply terminal of the level conversion circuit 30 is connected to the high potential power supply VddO, the level fixing terminal is connected to the low potential power supply Vdd, and the ground terminal is connected to the ground terminal of the conventional semiconductor output circuit SC11.

The power supply terminal of the output stage circuit 40 is connected to a high potential power supply VddO, and the level fixing terminal is connected to the low potential power supply VddO.
dd, and the ground terminal is connected to the ground terminal of the conventional semiconductor output circuit SC11.

Next, the operation of the conventional semiconductor output circuit SC11 will be described.

In the conventional semiconductor output circuit SC11, a signal of an internal circuit operating with a low potential power supply Vdd (eg, 1.8 V), that is, a high level is a low potential power supply Vdd (eg, 1.8 V) and a low level is 0 V Is a signal
The high level is a high potential power supply VddO (eg, 3.3 V)
And amplifies to a large amplitude signal whose low level is 0V,
This is the output circuit. From the small amplitude signal of the internal circuit, the normal signal and the inverted signal are generated by the inverted signal generation circuit 20 via the drive circuit 10.

These signals are input to the gates of the differential NMOS transistors of the level conversion circuit 30, respectively. The level conversion circuit 30 has a high level of a low potential power supply V
The signal which is dd and whose low level is 0 V is converted into a signal whose high level is the high potential power supply VddO and whose low level is the low potential power supply Vdd.

The drain of the differential NMOS transistor of the level conversion circuit 30 is connected to the NMOS transistor and the PMOS.
The transistor is connected to the source of the NMOS transistor in the cascade connection circuit in which the transistors are cascade-connected, and the gate of the NMOS transistor and the P
A low potential power supply Vdd is applied to the gate of the MOS transistor.

Thus, the voltage applied between the source and the drain of the transistor constituting the level conversion circuit 30 is divided and reduced. NM connected in tandem
P in OS transistor and PMOS transistor
The drain of a cross-coupled PMOS transistor is connected to the source of the MOS transistor. The source of the cross-coupled PMOS transistor is connected to the power supply high-potential power supply VddO.

When the cross-coupled PMOS transistor is completely turned on, the high level of the output terminal becomes the high-potential power supply VddO, and when the cross-coupled PMOS transistor is almost off, the low level (low level) determined by the driving force of the driving NMOS transistor. (Designed as the potential power supply Vdd).

In the output stage circuit 40, the uppermost PMOS transistor and the lowermost NMOS transistor drive the output terminal Y. In the output stage circuit 40, the PMOS transistor and the NMOS transistor whose gates are connected to the low-potential power supply Vdd have their sources connected to the low-potential power supply Vdd.
dd + Vth (Vth is the threshold value of the transistor), thus dividing the voltage applied between the source / drain of the cascaded transistors,
Reduce.

Thus, even if the source / drain breakdown voltage of the transistor constituting the output stage circuit 40 is lower than the voltage of the power supply high potential power supply VddO, the output stage circuit 40
And a signal whose high level is the high potential power supply VddO is output while reducing the voltage applied to the transistor in the level conversion circuit 30.

[0018]

In the conventional semiconductor output circuit SC11, for example, the high potential power supply VddO is used.
Is 3.3 V, and the voltage of the low potential power supply Vdd is 1.
When used at a voltage lower than 0 V, there is a problem that the current driving force of the output stage circuit 40 is remarkably reduced, a duty ratio of a signal is deteriorated, and a problem is that a high-speed signal cannot be output.

FIG. 5 shows a conventional semiconductor output circuit SC11 in which an NMOS transistor and a PM of an output stage circuit 40 are connected.
FIG. 10 is a diagram showing a drive current with an OS transistor using a voltage of an internal power supply low potential power supply Vdd as a parameter.

FIG. 5 shows that in the conventional semiconductor output circuit SC11, when the low potential power supply Vdd of the internal circuit is low, the current drivability on the NMOS transistor side is significantly reduced.

That is, when the voltage of the internal power supply low-potential power supply Vdd becomes less than 1.0 V, the current driving force of the NMOS transistor becomes one fifth or less of the current driving force of the PMOS transistor. As a result, the falling transition time is increased about five times as much as the rising transition time of the output signal, and the duty ratio of the output signal is significantly increased. Then, a high-speed signal cannot be output due to the increased descent transition time.

As a method of compensating for this, there is a method of increasing the transistor channel width of the NMOS transistor by a factor of five or more.

However, there is a new problem that the area of the output stage circuit 40 is greatly increased. Also, the low-potential power supply V
If the dd voltage is further reduced and used at around 0.5 V, the current driving force of the NMOS transistor becomes 1/70 of the current driving force of the PMOS transistor. It becomes impossible to cope with a general area.

That is, the conventional semiconductor output circuit SC11
Corresponds to the voltage of the high-potential power supply VddO,
When the voltage dd is extremely low, the current driving force of the output stage circuit 40 is significantly reduced, the duty ratio of the signal is deteriorated, and a high-speed signal cannot be output.

According to the present invention, even when the voltage of the low potential power supply Vdd is extremely lower than the voltage of the high potential power supply VddO,
It is an object of the present invention to provide a semiconductor output circuit having a good duty ratio and capable of outputting a high-speed signal.

[0026]

SUMMARY OF THE INVENTION The present invention comprises a driving circuit,
An inversion signal generation circuit for inverting an output signal of the drive circuit, a first level conversion circuit for inputting a non-inversion signal and an inversion signal generated by the inversion signal generation circuit, a PMOS transistor and an NMOS transistor are connected in cascade. Output stage circuit, wherein the output terminal of the first level conversion circuit is connected to the gate of a PMOS transistor connected to a power supply among the transistors constituting the output stage circuit. A second level conversion circuit for inputting a non-inversion signal and an inversion signal generated by the inversion signal generation circuit, wherein a gate of a lowermost NMOS transistor among transistors forming the output stage circuit , A semiconductor output circuit to which the output terminal of the second level conversion circuit is connected.

According to the present invention, there is provided a third level conversion circuit having an input terminal connected to a second output terminal of the first level conversion circuit. A semiconductor output circuit in which the output terminal of the third level conversion circuit is connected to the gate of a PMOS transistor connected to the output terminal of the semiconductor output circuit.

Further, according to the present invention, there is provided the third level conversion circuit wherein the input terminal is connected to the second output terminal.
The output terminal of the third level conversion circuit is connected to the gate of the NMOS transistor connected to the output terminal of the semiconductor output circuit among the transistors constituting the output stage circuit. Semiconductor output circuit.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing a semiconductor output circuit SC1 according to a first embodiment of the present invention.

The semiconductor output circuit SC1 includes a driving circuit 10
, An inverted signal generation circuit 50, and a first level conversion circuit 6
1, a second level conversion circuit 62, and an output stage circuit 40.

The input terminal of the drive circuit 10 is the input terminal of the semiconductor output circuit SC1. The output terminal of the drive circuit 10 is connected to the input terminal of the inverted signal generation circuit 50.

The non-inversion output terminal of the inversion signal generation circuit 50
The first input terminal of the first level conversion circuit 61 is connected to the first input terminal of the second level conversion circuit 62, and the inverted output terminal is connected to the second input terminal of the first level conversion circuit 61. Terminal and a second input terminal of the second level conversion circuit 62.

The output terminal of the first level conversion circuit 61
It is connected to the gate of the PMOS transistor located at the top of the output stage circuit 40. Second level conversion circuit 6
2 is connected to the N terminal located at the bottom of the output stage circuit 40.
It is connected to the gate of the MOS transistor.

The output terminal of the output stage circuit 40 is the output terminal of the semiconductor output circuit SC1.

The semiconductor output circuit SC1 uses a low potential power supply Vdd and a high potential power supply VddO. The power supplies of the drive circuit 10 and the inverted signal generation circuit 50 are connected to the low potential power supply Vdd, and the ground terminals are connected to the ground terminal of the semiconductor output circuit SC1. The power supply terminals of the first level conversion circuit 61 and the second level conversion circuit 62 are connected to the high potential power supply VddO, the level fixed terminal is connected to the low potential power supply Vdd, and the ground terminal is connected to the semiconductor output circuit SC1. Connected to the ground terminal.

The power supply terminal of the output stage circuit 40 is connected to the high potential power supply VddO, and the level fixed terminal is connected to the low potential power supply VddO.
dd, and the ground terminal is connected to the semiconductor output circuit SC.
1 ground terminal. However, the voltage applied to the level fixing terminal is not limited to the voltage of the low-potential power supply Vdd, and may be high depending on the withstand voltage of the transistor.
, And a voltage higher than the low-potential power supply Vdd may be applied.

Next, the operation of the semiconductor output circuit SC1 will be described.

The semiconductor output circuit SC1 has a low potential power supply Vd
d (for example, 0.5 V), that is, a high-level low-potential power supply Vdd (for example, 0.5 V).
V), a circuit that amplifies a low-level 0V signal into a large-amplitude signal whose high level is a high-potential power supply VddO (for example, 3.3 V) and whose low level is 0 V, and outputs the amplified signal.

The small-amplitude signal of the internal circuit is input to the inversion signal generation circuit 50 via the drive circuit 10, and the inversion signal generation circuit 50 generates a normal signal and an inversion signal.

The generated normal signal and inverted signal are:
The gate of the differential NMOS transistor of the first level conversion circuit 61 and the differential NMOS transistor of the second level conversion circuit 62
The voltage is applied to the gate of the transistor.

A signal whose high level is the low-potential power supply Vdd and whose low level is 0 V is supplied to the first level conversion circuit 6.
1 is converted into a signal whose high level is the high potential power supply VddO and whose low level is the low potential power supply Vdd. The drain of the differential NMOS transistor of the first level conversion circuit 61 is connected to the NMOS transistor connected in cascade by P
The low-potential power supply Vdd (or the low-potential power supply Vdd and the high-potential power supply Vdd) are connected to the gates of the NMOS transistor and the PMOS transistor which are connected to the source of the NMOS transistor among the MOS transistors and are connected in cascade.
ddO).

As a result, the level conversion circuits 61 and 62
Divides and reduces the voltage applied between the source and the drain of the transistor that constitutes.

The drain of a cross-coupled PMOS transistor is connected to the source of the PMOS transistor of the cascade-connected NMOS and PMOS transistors. The source of the cross-coupled PMOS transistor is connected to the power supply high-potential power supply VddO.

When the cross-coupled PMOS transistor is completely turned on, the high level of the output terminal becomes the high potential power supply VddO.
When the transistor is almost off, a low level (low potential power supply Vdd) determined by the driving force of the driving NMOS transistor
Is output.

On the other hand, the second level conversion circuit 62
Performs the same operation as the above-described operation in the level conversion circuit 61, but the second level conversion circuit 62 has a different output signal level because the output signal extraction node is different. That is, when the NMOS transistor on the output node side of the differential NMOS transistor is turned on, it outputs a low level of 0 V, and when the NMOS transistor is turned off, it depends on the size of the PMOS transistor and the NMOS transistor cascaded to the drain. It outputs a high level which is an intermediate potential between the determined low potential power supply Vdd and high potential power supply VddO.

In the output stage circuit 40, the uppermost PMOS transistor and the lowermost NMOS transistor drive the output terminal Y. PMOS transistor and NMOS whose gates are connected to low potential power supply Vdd (or a voltage intermediate between low potential power supply Vdd and high potential power supply VddO)
A transistor is such that each source is connected to a low potential power supply Vdd + Vt.
The voltage applied between the source and the drain of the cascade-connected transistors is divided and reduced by clamping to the potential of h (Vth is the threshold value of the transistor).

Thus, even if the source / drain breakdown voltage of the transistor constituting the output stage circuit 40 is lower than the voltage of the power supply high potential power supply VddO, the output stage circuit 40
While the voltage applied to the transistor in the first level conversion circuit 61 and the first level conversion circuit 61 is reduced, the high level
A signal that is ddO is output.

That is, the semiconductor output circuit SC1 has a driving circuit, an inverted signal generating circuit for inverting an output signal of the driving circuit, and a first input for receiving a normal signal and an inverted signal generated by the inverted signal generating circuit. Level conversion circuit and PMO
An output stage circuit in which an S transistor and an NMOS transistor are connected in cascade, and among the transistors constituting the output stage circuit, a PM connected to a power supply is provided.
In a semiconductor output circuit in which an output terminal of the first level conversion circuit is connected to a gate of an OS transistor,
A second level conversion circuit for inputting a non-inversion signal and an inversion signal generated by the inversion signal generation circuit, and a gate of a lowermost NMOS transistor among the transistors forming the output stage circuit; 2 is an example of a semiconductor output circuit to which output terminals of a second level conversion circuit are connected.

FIG. 2 shows a condition that the voltage applied between the source / drain, the gate / source, and the drain / gate becomes lower than the breakdown voltage Vb of the transistor in all the transistors constituting the output stage circuit 40 in the above embodiment. FIG.

When the output voltage of the output stage circuit 40 is 0 V, the high potential power supply Vd
dO (= 3.3 V) is applied. The gate of the PMOS transistor connected to the output terminal has the following (1)
It is necessary to apply the low potential power supply Vddc limited by the equation.

3.3−Vb <low-potential power supply Vddc <Vb Expression (1) At this time, the gate potentials Van1 and Van2 of the NMOS transistor that draws current from the output terminal Y are equal to the breakdown voltage Vb.
It is important for the NMOS transistor to obtain a high current drivability in a value smaller than the above value and as large as possible.

On the other hand, when the output voltage of the output stage circuit 40 is the high potential power supply VddO (= 3.3 V), the high potential power supply VddO (= 3.
3V) is applied. NM connected to output terminal Y
In the gate of the OS transistor, the equation (1)
And the voltage applied to each NMOS transistor is reduced to less than the breakdown voltage Vb.

Then, at this time, the gate potentials Vap1 and Va1 of the PMOS transistor which causes a current to flow to the output terminal Y.
p2 is a value in which the high-potential power supply VddO-Vap1 and the high-potential power supply VddO-Vap2 are smaller than the withstand voltage Vb. This is important for obtaining high current driving power in a transistor.

In the second level conversion circuit 62, the gate potential Van1 has a value smaller than the breakdown voltage Vb.
It is possible to apply as large a voltage as possible. In the conventional example, the gate potential of the NMOS transistor is limited to the low potential power supply Vdd. If the low potential power supply Vdd is a very low voltage such as 0.5 V, the NMOS transistor
While the driving power of the transistor is significantly reduced, the driving power of the NMOS transistor of the output stage circuit 40 can be increased by the second level conversion circuit 62 in the first embodiment. For example, when the high level of the output signal of the second level conversion circuit 62 is set to 10 V, the current drivability of the PMOS transistor and the NMOS transistor of the output stage circuit 40 becomes (PMOS transistor and NMO).
(In addition to adjusting the channel width of the S transistor).

That is, according to the semiconductor output circuit SC1,
A high voltage can be applied to the gate of the NMOS transistor of the output stage circuit 40, and the low potential power supply Vd of the internal circuit can be applied.
Even when d is a very low voltage such as 0.5 V, the driving power of the NMOS transistor of the output stage circuit 40 can be increased. This makes it possible to make the current driving capability of the PMOS transistor and the NMOS transistor of the output stage circuit 40 equal, and the duty ratio of the output signal becomes 5
0%, and a high-speed signal can be output.

FIG. 3 is a diagram showing a semiconductor output circuit SC2 according to a second embodiment of the present invention.

The semiconductor output circuit SC2 is basically the same as the semiconductor output circuit SC1.
1 is different from the semiconductor output circuit SC1 in that a third level conversion circuit 63 is added.

That is, the semiconductor output circuit SC2 includes the drive circuit 10, the inversion signal generation circuit 50, the first level conversion circuit 61, the second level conversion circuit 62, and the third level conversion circuit 63. And an output stage circuit 40.

Next, the differences between the semiconductor output circuit SC2 and the semiconductor output circuit SC1 will be described.

In the semiconductor output circuit SC2, the input terminal of the third level conversion circuit 63 is connected to the second output terminal of the first level conversion circuit 61, and the drain is connected to the output terminal Y of the output stage circuit 40. The output terminal of the third level conversion circuit 63 is connected to the gate of the PMOS transistor. The first power supply terminal of the third level conversion circuit 63 is connected to the low-potential power supply Vdd, and the second power supply terminal of the third level conversion circuit 63 is
It is connected to a high potential power supply VddO. The ground terminals are respectively connected to the ground terminals of the semiconductor output circuit SC2.

Next, the operation of the semiconductor output circuit SC2 will be described.

Drive circuit 1 in semiconductor output circuit SC2
The operations of 0, the inverted signal generation circuit 50, the first level conversion circuit 61, and the second level conversion circuit 62 are the same as those of the semiconductor output circuit SC1, and the description thereof is omitted. .

The third level conversion circuit 63 receives the second output signal of the first level conversion circuit 61. The input signal is a signal of a high-level low-potential power supply Vdd (for example, the low-potential power supply Vdd is 0.5 V) and a low-level 0 V signal. Further, the third level conversion circuit 63 converts the input signal of the high-level low-potential power supply Vdd and the low-level 0 V into a high-level 3.3 V and a low-level 1.2 V and outputs the converted signal.

The second level conversion circuit 62 is the output stage circuit 4
The third level conversion circuit 63 increases the driving force of the PMOS transistor connected to the output terminal Y in the output stage circuit 40, while increasing the driving force of the NMOS transistor 0.

When the semiconductor output circuit SC2 outputs a high-level high-potential power supply VddO (= 3.3 V),
Since the third level conversion circuit 63 outputs 0 V, a lower voltage is applied to the gate of the PMOS transistor in the output stage circuit 40 as compared with the case where the voltage is fixed to the low voltage power supply Vdd in the semiconductor output circuit SC1. Can be given. Therefore, the PMOS transistor in the output stage circuit 40 obtains a larger current driving force with the same channel width. As a result, the semiconductor output circuit SC2 can operate at a higher speed than the semiconductor output circuit SC1.

That is, according to the semiconductor output circuit SC2,
By applying a potential lower than the low potential power supply Vdd to the gate of the PMOS transistor connected to the output terminal of the output stage circuit 40, the driving power of the NMOS transistor of the output stage circuit 40 can be enhanced. The current driving force can be increased, and thereby, a signal that is faster than the semiconductor output circuit SC1 can be output.

In the above embodiment, the two-stage PMO
The output stage circuit 40 is constituted by a cascade connection of S transistors and two NMOS transistors. If the breakdown voltage of the PMOS transistor and the NMOS transistor is higher than that of the high potential power supply VddO, PM
The level conversion circuits 61, 62, and 63 may be configured by using one stage of the OS transistor and one stage of the NMOS transistor.

That is, the semiconductor output circuit SC2 has a third level conversion circuit in which the input terminal is connected to the second output terminal of the first level conversion circuit in the semiconductor output circuit SC1. Is an example of a semiconductor output circuit in which the output terminal of the third level conversion circuit is connected to the gate of a PMOS transistor connected to the output terminal of the semiconductor circuit among the transistors constituting the above.

The remaining N constituting output stage circuit 40
The output terminal of the third level conversion circuit 63 may be connected to the gate of the MOS transistor.

That is, in the semiconductor output circuit SC1,
An output terminal of the semiconductor circuit includes a third level conversion circuit having an input terminal connected to a second output terminal of the first level conversion circuit. A semiconductor output circuit in which the output terminal of the third level conversion circuit is connected to the gate of the connected NMOS transistor.

In each of the above embodiments, the inverted signal generating circuit 20 of the conventional example may be used instead of the inverted signal generating circuit 50. Even in this case, the voltage of the low-potential power source VddO is
Even when the voltage dd is extremely low, a high-speed signal can be output to some extent with a good duty ratio.

As described above, when the inversion signal generation circuit 20 of the conventional example is used instead of the inversion signal generation circuit 50, the time difference between the normal signal and the inversion signal in the inversion signal generation circuit 50 becomes Since the time difference between the normal signal and the inverted signal in the circuit 20 is smaller, the output signal at the output terminal Y in each of the above embodiments is faster when the inverted signal generation circuit 50 is used in each of the above embodiments. Signal.

[0073]

According to the present invention, it is possible to output a high-speed signal with a good duty ratio even when the voltage of the low-potential power supply Vdd is extremely low with respect to the voltage of the high-potential power supply VddO. It works.

[Brief description of the drawings]

FIG. 1 shows a semiconductor output circuit S according to a first embodiment of the present invention.
It is a circuit diagram which shows C1.

FIG. 2 summarizes the conditions in which the voltage applied between the source / drain, the gate / source, and the drain / gate is less than the withstand voltage Vb of the transistor in all the transistors constituting the output stage circuit 40 in the above embodiment. FIG.

FIG. 3 shows a semiconductor output circuit S according to a second embodiment of the present invention;
It is a figure showing C2.

FIG. 4 is a circuit diagram showing a conventional semiconductor output circuit SC11.

FIG. 5 is a diagram showing a drive current for an NMOS transistor and a PMOS transistor of an output stage circuit 40 in a conventional semiconductor output circuit SC11, using a voltage of an internal power supply low potential power supply Vdd as a parameter.

[Description of Signs] SC1, SC2: semiconductor output circuit, Vdd: low-potential power supply, VddO: high-potential power supply, 10: drive circuit, 40: output stage circuit, 50: inverted signal generation circuit, 61: first level conversion Circuit, 62: a second level conversion circuit, 63: a third level conversion circuit.

Claims (3)

[Claims] 1. A driving circuit for driving an input signal, an inverted signal generating circuit for inverting an output signal of the driving circuit, and a first input for receiving a normal signal and an inverted signal generated by the inverted signal generating circuit. A level conversion circuit, and an output stage circuit in which a PMOS transistor and an NMOS transistor are cascade-connected. Of the transistors constituting the output stage circuit, the gate of the PMOS transistor connected to the power supply is connected to the gate of the PMOS transistor. 1. A semiconductor output circuit to which an output terminal of a first level conversion circuit is connected, comprising: a second level conversion circuit for inputting a non-inversion signal and an inversion signal generated by the inversion signal generation circuit; Out of the transistors constituting the second level conversion circuit, the output terminal of the second level conversion circuit is connected to the gate of the lowermost NMOS transistor. Semiconductor output circuit to be. 2. The transistor according to claim 1, further comprising a third level conversion circuit having an input terminal connected to a second output terminal of the first level conversion circuit, and A semiconductor output circuit, wherein an output terminal of the third level conversion circuit is connected to a gate of a PMOS transistor connected to an output terminal of the semiconductor output circuit. 3. The transistor according to claim 1, further comprising a third level conversion circuit having an input terminal connected to a second output terminal of the first level conversion circuit, and A semiconductor output circuit, wherein an output terminal of the third level conversion circuit is connected to a gate of an NMOS transistor connected to an output terminal of the semiconductor output circuit.