JPH0722916Y2 - Broadcast receiver - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application This invention relates to frequency control for automatically fine-tuning the reception frequency of a broadcast receiver, and in particular to satellite broadcast reception for detecting and controlling a synchronization signal of a PCM audio signal. The present invention relates to a broadcast receiving apparatus suitable for a machine.

(B) Problems to be solved by the conventional technology and device Conventionally, for example, a block diagram relating to PCM audio signal synchronization of a satellite broadcast receiver is shown in FIG.

In the figure, 10 is a receiving antenna, 11 is an RF amplifier circuit that amplifies and selects an RF received signal, 12 is a mixer circuit, 13 is a demodulation circuit that demodulates a modulated wave, and 14 is a signal obtained by extracting a video signal from the demodulated signal. Video signal processing circuit for processing, 15 is a video signal output terminal, 16 is a PCM audio signal processing circuit for extracting and processing the PCM audio signal from the output signal of the demodulation circuit 13, 17 is a digital signal subjected to PCM audio signal processing Is a D / A conversion circuit for converting the analog signal into an analog signal, 18 is a low-pass filter, and 19 is an audio signal output terminal.

20 is a sync signal detection circuit that detects the sync signal of the PCM audio signal from the PCM audio signal processing circuit 16, and 21 is a sync signal detection circuit 20.
, A PLL circuit having an I / N frequency dividing circuit controlled by a program of the microcomputer 21, and a DC voltage detecting circuit for detecting a DC output signal of the demodulation circuit 13. .

The receiver that has received the satellite broadcast is demodulated by the demodulation circuit 13 via the RF amplification circuit 11 and the mixer circuit 12. Mixer circuit 12
Are mixed at the local oscillation frequency of the PLL circuit 22 and converted into an intermediate frequency.

From the signals demodulated by the demodulation circuit 13, the video signal is taken out from the video output terminal 15 via the video signal processing circuit 14. On the other hand, the PCM audio signal is supplied to the PCM audio signal processing circuit 16, converted into an analog signal by the D / A conversion circuit 17, and output from the audio output terminal 19 via the low pass filter 18.

As the PCM audio signal processing circuit 16, a dedicated commercially available LSI is generally used. The synchronization signal detection circuit of this LSI outputs a frame out-of-frame flag output (NSYNC), which is supplied to the input port of the microcomputer 21.

Further, when the demodulation output DC voltage of the demodulation circuit 13 is detected by the DC voltage detection circuit 23 and the DC voltage value is equal to or lower than the set DC level, the frequency up request signal (AFT1 signal) is supplied to the microcomputer 21. . When the detected DC voltage value is equal to or higher than the set DC level, the frequency down request signal (AFT2 signal) is sent to the microcomputer 21.
Is supplied to.

The microcomputer 21 determines whether it is in the synchronous state or the asynchronous state based on the synchronous signal from the synchronous signal detection circuit 20, and in the case of the asynchronous state, depending on the DC level of the demodulated signal from the DC voltage detection circuit 23, a frequency up or down request signal. Is supplied to the microcomputer 21 to control the local oscillator of the PLL circuit 22 to raise or lower the oscillation frequency of the local oscillator in a certain step so that the optimum synchronization frequency can be obtained.

The PLL circuit 22 is composed of an I / N frequency dividing circuit controlled by the microcomputer 21, a local oscillation circuit, a reference oscillator and a phase comparator.

In this way, the PCM audio signal synchronization of the broadcast receiver operates the microcomputer 21 by the demodulation DC voltage and synchronization signal detection circuit 20 and controls the local oscillation circuit of the PLL circuit 22 to obtain the optimum synchronization frequency. ing.

However, in the conventional broadcast receiving apparatus described above, the demodulation circuit 13
The DC voltage detection circuit 23 is required, and the microcomputer 21 is controlled by the AFT1 signal or the AFT2 signal from the DC voltage detection circuit 23, so that the circuit configuration becomes complicated and the cost is increased. .

The present invention has been made in view of the above points, and the purpose thereof is to eliminate the drawbacks of the conventional example, and by the frame synchronization signal from the synchronization signal detection circuit 20, the synchronization upper limit frequency and the synchronization lower limit frequency of the synchronization state. There is provided a broadcast receiving apparatus which detects the signal and obtains the optimum synchronization frequency.

(C) Means for Solving the Problem FIG. 1 is a functional block diagram showing the configuration of the present invention.
The broadcast receiving device of this invention has a detection circuit for detecting a synchronization signal of the PCM audio signal from a PCM audio signal processing circuit of the broadcast receiver, and an I / N frequency dividing circuit which constitutes a local oscillator of the broadcast receiver. According to the synchronous / asynchronous state detection output from the PLL circuit and the detection circuit that detects the synchronous signal, the I / N
A broadcast receiving apparatus comprising: a control circuit for initializing control of a PLL circuit having a frequency dividing circuit, wherein the control circuit is such that an output from a detection circuit for detecting the synchronization signal is asynchronous with a synchronization state detection output. A means for changing the output frequency of the PLL circuit in the first direction until a state detection output is obtained, and a detection circuit for detecting the synchronization signal upon receiving a transition from the synchronization state detection output to the asynchronous state detection output. Means for changing the output frequency of the PLL circuit in a second direction opposite to the first direction until the output changes from the synchronous state detection output to the asynchronous state detection output again; Means for storing a first frequency and a second frequency, which are output frequencies of the PLL circuit at the time of transition to the state detection output, and an optimum synchronization frequency is calculated from the stored first and second frequencies. And the step, in which the division ratio of the PLL circuit based on the output of the calculating means and means for initializing control.

(D) Operation The operation of this invention will be described based on the functional blocks of FIG.

The PCM audio signal received by the broadcast reception of the PCM audio signal and demodulated by the demodulation circuit 1 is signal-processed by the PCM audio signal processing circuit 4, but it is necessary to stably and correctly synchronize the PCM audio signal.

Therefore, in order to detect the synchronous state or the asynchronous state and obtain the optimum synchronous frequency, the local oscillation circuit 1a is controlled to change the oscillation frequency in the direction of FIG. 1 (for example, step up) to change the synchronous state to the asynchronous state. The first frequency (for example, the synchronization upper limit frequency) is detected. Next, the oscillation frequency is changed in a second direction (eg, step-down) opposite to the first direction to detect a second frequency (eg, sync lower limit frequency) from the synchronous state to the asynchronous state. .
The optimum synchronization frequency is calculated from the first and second (for example, the synchronization upper and lower limits) frequencies thus obtained. The optimum synchronization frequency can also be obtained by, for example, the arithmetic mean of the first and second (for example, the synchronization upper and lower limits) frequencies.

In this way, the I / N divider of the PLL circuit is controlled so that the optimum synchronization signal frequency obtained by the calculation means is obtained, and the local oscillation circuit 1a
Initializes the oscillation frequency of and operates so that stable PCM audio signal synchronization can be obtained.

(E) Embodiment An embodiment of the broadcast receiving apparatus according to the present invention is shown in FIGS.
It will be described with reference to the drawings.

The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a functional block diagram showing the configuration of the present invention, FIG. 2 is a block diagram of a circuit, and FIG. 3 is a flowchart showing an operation of PCM audio signal synchronization.

In the figure, 1 is a block including an RF receiving and demodulating circuit of a broadcast receiver, 2 is a video signal processing circuit into which a demodulated signal is input, 3 is a video output, and 4 is a PCM audio signal taken out from the demodulated signal. , PCM audio signal processing circuit for signal processing,
5 is a voice output, 6 is a sync signal of a PCM voice signal,
Synchronous upper limit frequency detecting means for stepping up the local oscillation frequency and detecting the frequency from the synchronous state to the asynchronous state,
Contrary to 6, 7 is a sync lower limit frequency detecting means for stepping down the local oscillation frequency to detect the frequency at which the sync signal changes from the synchronous state to the asynchronous state, and 8 is the optimum synchronous frequency calculated from the synchronous upper limit and lower limit frequencies. Calculation means, 9 is 8
The local oscillation frequency of the PLL circuit is initialized by the control means that controls the I / N frequency divider of the PLL circuit based on the output of.

FIG. 2 is a circuit block diagram of an actual broadcast receiver for the functional blocks of FIG. 1, in which the DC voltage detection circuit from the demodulation circuit 13 of the conventional example is deleted. Therefore, the microcomputer is not controlled by the frequency up or down request signal controlled by the DC voltage, but the synchronization upper limit frequency and the lower limit frequency are detected by the synchronization signal detection.

The operation will be described with reference to the flowchart of FIG. When the reception channel is operated to switch the reception frequency, for example, a frame out-of-sync flag is output from the synchronization signal detection circuit 20 and is input to the input port of the microcomputer 21, and the microcomputer 21 changes the frequency in, for example, 62.5 KHZ steps. The frequency is stepped up and switched in the direction of increasing (step S1).

Every time the frequency is switched, the synchronization state of the synchronization signal input from the synchronization signal detection circuit 20 is checked.

The frequency step-up operation is executed until the synchronization signal becomes out of synchronization, the synchronization upper limit frequency is detected, and the frequency is written in the memory of the microcomputer 21 (step S2).

When the sync upper limit frequency is detected, the microcomputer 21
Reversely steps down the frequency (step S3). While checking the sync signal of the sync signal detection circuit 20, the step goes down to obtain the sync lower limit frequency out of sync (step S4).

When the intermediate point between the synchronization upper and lower limit frequencies thus obtained is determined as the optimum synchronization frequency, an arithmetic average of the synchronization upper and lower frequencies is calculated and calculated, and the arithmetically averaged frequency is set as the optimum synchronization frequency. The optimum synchronization frequency may be set based on another calculation criterion (step S5).

The I / N divider (not shown) of the PLL circuit 22 having the local oscillator is controlled so that the calculated optimum synchronization frequency is obtained, and the oscillation frequency of the local oscillator is set (step S6 ).

When playing back PCM audio signals, the PCM audio signals of the broadcast receiver operating at the optimum sync frequency above are stable and good PCM.
Can play audio signals.

(Effect of device) As described above, the broadcast receiving device according to the present invention detects the upper and lower frequencies of synchronization from the PCM audio signal processing circuit,
Since the local oscillation frequency is controlled, the DC voltage detection circuit from the demodulation circuit is not required unlike the conventional example. Further, there is an effect that the two AFT signal input ports for frequency up or down depending on the DC voltage level are unnecessary in the microcomputer. Moreover, it has an excellent feature that it has a simple structure and can be constructed at a low cost, and thus is easy to implement.

[Brief description of drawings]

1 to 3 show an embodiment of a broadcast receiving apparatus according to the present invention, FIG. 1 is a functional block diagram showing the configuration of the present invention, FIG. 2 is a circuit block diagram, and FIG. 3 is PCM audio. It is a flowchart which shows operation | movement of signal synchronization. FIG. 4 is a block diagram of a conventional circuit. Description of main codes 1: Block including RF reception and demodulation circuit 2: Video signal processing circuit 4: PCM audio signal processing circuit 6: Synchronization upper limit frequency detection means 7: Synchronization lower limit frequency detection means 8: Optimal synchronization frequency calculation Means 9: PLL divider control means

Claims (1)

[Scope of utility model registration request] 1. A PCM from a PCM audio signal processing circuit of a broadcast receiver.
Detecting circuit for detecting sync signal of audio signal, PLL circuit having 1 / N frequency dividing circuit constituting the local oscillator of the broadcast receiver, and detecting sync / asynchronous state from detecting circuit for detecting the sync signal PLL with the 1 / N divider circuit according to the output
A broadcast receiving apparatus comprising: a control circuit for initializing control of a circuit, wherein the control circuit is configured to operate until the output from the detection circuit for detecting the synchronization signal changes from a synchronous state detection output to an asynchronous state detection output. A means for changing the output frequency of the PLL circuit in the first direction, and an output from the detection circuit that detects the synchronization signal upon receiving the transition from the synchronization state detection output to the asynchronous state detection output is again the synchronization state detection output. Means for changing the output frequency of the PLL circuit in a second direction opposite to the first direction until the output becomes an asynchronous state detection output, and at the time of transition from the synchronous state detection output to the asynchronous state detection output. The output frequency of the PLL circuit in the first
Means for storing the frequency and the second frequency, means for calculating the optimum synchronizing frequency from the stored first and second frequencies, and the frequency division ratio of the PLL circuit is initialized based on the output of the calculating means. A broadcast receiving apparatus, comprising: means for setting control.