JPH052484U - Video intermediate frequency signal processing circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] AGC operation for signal amplification is performed well even if an abnormality occurs in the PLL for the carrier of the video intermediate frequency signal.
Always perform stable signal processing. [Structure] To detect an image intermediate frequency signal by the phase detection circuit 54, a phase detection circuit 18, a low-pass filter 20,
The PLL by the VCO 22 and the phase shift circuit 24 is used.
This PLL operates based on only the signal during the blanking period by the output of the synchronization signal separation circuit 28. On the other hand, the AGC in the intermediate frequency amplifier circuit 12 is performed by the intermediate frequency AGC circuit 50 independently of the PLL and is performed based on the output of the envelope detection circuit 52.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a video intermediate frequency signal processing circuit in a television receiver or the like, and particularly to improvement of AGC (automatic gain control) for the video intermediate frequency signal.

[0002]

[Prior Art]

 A conventional video intermediate frequency signal processing circuit is shown in FIG. This is due to the phase detection method disclosed in Japanese Patent Application No. 63-331348. In the figure, the video intermediate frequency signal output from the tuner (not shown) and input to the input terminal 10 is amplified by the intermediate frequency amplifying circuit 12, and then the phase detecting circuit 14 and the envelope detecting circuit 16 respectively. Is entered. The phase detection circuit 14 is connected to another phase detection circuit 18, a low-pass filter 20, a VCO (voltage controlled oscillator) 22, and a PLL (phased lock loop) including a phase shift circuit 24.

To explain the operation of this PLL, the phase detection circuit 18 detects the phase difference between the input signals. This detection output is input to the low pass filter 20 and converted into a direct current. This DC-converted signal has a level corresponding to the phase difference between the output signals of the phase detection circuit 14 and the phase shift circuit 24. If there is no phase difference between the output signals, the "0" level, the phase difference In some cases, the level depends on the phase difference. This direct current signal is input to the VCO 22 as an oscillation control signal.

The VCO 22 controls the oscillation frequency corresponding to the input DC signal level, thereby controlling the frequency of the output signal supplied to the phase shift circuit 24. By such an operation, the oscillation frequency of the VCO 22 is fixed to the carrier frequency of the input video intermediate frequency signal.

The oscillation signal of the VCO 22 whose oscillation frequency is fixed is appropriately phase-shifted by the phase-shift circuit 24, and then supplied to the phase detection circuit 14, and the phase detection of the video intermediate frequency signal is performed based on this signal. .. As a result, the video intermediate frequency signal is converted into a baseband video signal, which is output from the output terminal 26. It should be noted that the phase detection circuit 18 is performed based on the output of the synchronization signal separation circuit 28 only based on the signal during the blanking period. This prevents the fixed signal phase of the PLL from affecting the video content, as disclosed in Japanese Patent Application No. 63-331348.

The envelope detection circuit 16, the synchronization signal separation circuit 28, and the intermediate frequency AGC circuit 30 are detection units for obtaining a signal portion in which the image content does not change. The amplification factor of the intermediate frequency amplification circuit 12 is under gain control by the intermediate frequency AGC circuit 30, and the synchronization signal separation circuit 28 separates the synchronization signal based on the detection output of the envelope detection circuit 16. It is like this.

[0007]

[Problems to be solved by the device]

 However, in the conventional technique as described above, the operation of the intermediate frequency AGC circuit 30 is performed by using the detection output from the phase detection circuit 14. Therefore, if some abnormality occurs in the PLL, the detection output of the phase detection circuit 14 is affected, and the operation of the intermediate frequency AGC circuit 30 is also affected. As a result, the abnormality of the PLL leads to the abnormality of the AGC, and the operation as the video intermediate frequency signal processing circuit becomes unstable.

The present invention focuses on this point, and provides an image intermediate frequency signal processing circuit that can perform stable signal processing by performing good AGC operation even if an abnormality occurs in the internal PLL. The purpose is to provide.

[0009]

[Means for Solving the Problems]

 The present invention relates to a video intermediate frequency signal processing circuit having a first detection circuit for controlling the operation of a PLL for a carrier of a video intermediate frequency signal based only on a portion of the video intermediate frequency signal where the video content does not change. A second detection circuit that detects the video intermediate frequency signal independently of the first detection circuit, and an intermediate frequency AGC circuit that performs AGC of the video intermediate frequency signal based on the detection signal thereby obtained. It is a feature.

[0010]

[Action]

 According to the present invention, the detection of the video intermediate frequency signal is performed by using the PLL for the carrier wave. However, the AGC for amplifying the video intermediate frequency signal is performed based on the output of the detection circuit provided separately.

[0011]

【Example】

 An embodiment of a video intermediate frequency signal processing circuit according to the present invention will be described below with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components as those of the above-described conventional example.

FIG. 1 shows the configuration of this embodiment. In the figure, the detection output side of the envelope detection circuit 52 is connected to the input side of the intermediate frequency AGC circuit 50, and the detection output side of the phase detection circuit 54 is not connected. That is, the AGC for the intermediate frequency amplifier circuit 12 is performed by a loop including the envelope detection circuit 52 and the intermediate frequency AGC circuit 50, which is independent of the PLL loop for the video intermediate frequency signal carrier. Has become.

Next, the operation of this embodiment will be described. The video intermediate frequency signal input from the tuner (not shown) to the input terminal 10 is amplified by the intermediate frequency amplifier circuit 12, and then supplied to the envelope detection circuit 52 and the phase detection circuit 54. In the phase detection circuit 54, phase detection by the PLL is performed in the same manner as in the above-mentioned conventional technique, and the signal after detection is output from the output terminal 26.

At this time, the envelope detection circuit 52 performs envelope detection on the input video intermediate frequency signal and outputs the detection signal to the synchronization signal separation circuit 28. The sync signal separation circuit 28 separates the sync signal from the input signal and outputs it to the phase detection circuit 18. The phase detection circuit 18 uses the input synchronization signal to perform phase detection using only the signal during the blanking period.

By the way, in the present embodiment, the intermediate frequency AGC circuit 50 operates based on the detection output of the envelope detection circuit 52, that is, the signal obtained by detecting the peak value of the signal. Therefore, the AGC operation is performed without being affected by the PLL by the phase detection circuit 18, the low-pass filter 20, the VCO 22, and the phase shift circuit 24. Therefore, even if an abnormality occurs in the PLL due to an external noise or the like, the AGC loop operates stably and satisfactorily, and the circuit can return to a stable state satisfactorily. It should be noted that the present invention is not limited to the above-described embodiments at all, and various design changes are possible so as to achieve the same operation, and these are also included.

[0016]

[Effect of the device]

 As described above, according to the video intermediate frequency signal processing circuit of the present invention, the AGC operation of the video intermediate frequency signal is performed based on the output of the detection circuit independent of the phase detection PLL. Even if it occurs, there is an effect that the AGC operation can be satisfactorily performed and stable signal processing can be always performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video intermediate frequency signal processing circuit according to the present invention.

FIG. 2 is a configuration diagram showing a conventional example of a video intermediate frequency signal processing circuit.

[Explanation of symbols]

10 ... Input terminal, 12 ... Intermediate frequency amplifier circuit, 14, 1
8, 54 ... Phase detection circuit (first detection circuit), 16, 5
2 ... Envelope detection circuit (second detection circuit), 20 ... Low-pass filter, 22 ... VCO, 24 ... Phase shift circuit, 26 ... Output terminal, 28 ... Sync signal separation circuit, 30, 50 ... Intermediate frequency AGC circuit.

Claims (1)

Claims for utility model registration: 1. A first detection circuit for controlling the operation of a PLL for a carrier wave of a video intermediate frequency signal based only on a portion of the video intermediate frequency signal where the video content does not change. In the video intermediate frequency signal processing circuit which has, the 2nd detection circuit which detects a video intermediate frequency signal independently of the said 1st detection circuit, and performs AGC of a video intermediate frequency signal based on the detection signal by this. An image intermediate frequency signal processing circuit comprising an intermediate frequency AGC circuit.