JP2827581B2 - Digital receiver - Google Patents

Digital receiver

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Publication number
JP2827581B2
JP2827581B2 JP3145497A JP14549791A JP2827581B2 JP 2827581 B2 JP2827581 B2 JP 2827581B2 JP 3145497 A JP3145497 A JP 3145497A JP 14549791 A JP14549791 A JP 14549791A JP 2827581 B2 JP2827581 B2 JP 2827581B2
Authority
JP
Japan
Prior art keywords
frequency
signal
electric field
input
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3145497A
Other languages
Japanese (ja)
Other versions
JPH04343547A (en
Inventor
秀樹 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3145497A priority Critical patent/JP2827581B2/en
Publication of JPH04343547A publication Critical patent/JPH04343547A/en
Application granted granted Critical
Publication of JP2827581B2 publication Critical patent/JP2827581B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、四相位相変調方式のデ
ィジタル受信機に利用する。特に、振幅情報により復調
時のタイミング抽出を行う受信機に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a four-phase phase modulation type digital receiver. In particular, the present invention relates to a receiver that extracts timing at the time of demodulation based on amplitude information.

【0002】[0002]

【従来の技術】従来の振幅情報によるタイミング抽出を
行うディジタル受信機は、図4に示すように、高周波信
号を中間周波信号に変換して出力する高周波受信部1
と、中間周波信号からディジタル信号を出力する復調部
2と、この中間周波信号から振幅変動成分を検出して復
調部2にディジタル信号を抽出するボー・タイミングを
与える振幅情報検出部4とを有する。
2. Description of the Related Art As shown in FIG. 4, a conventional digital receiver for performing timing extraction based on amplitude information converts a high frequency signal into an intermediate frequency signal and outputs the intermediate frequency signal.
A demodulator 2 for outputting a digital signal from the intermediate frequency signal; and an amplitude information detector 4 for detecting an amplitude fluctuation component from the intermediate frequency signal and providing the demodulator 2 with baud timing for extracting the digital signal. .

【0003】[0003]

【発明が解決しようとする課題】この従来例では、強電
界が入力されると、高周波受信部内部の高周波増幅器お
よび周波数変換ミキサの利得の影響でその出力信号が飽
和して振幅変動成分が失われるので、振幅情報検出部で
のタイミング抽出が困難になり、復調部へボー・タイミ
ングを与えることができなくなる欠点があった。
In this conventional example, when a strong electric field is input, the output signal is saturated due to the influence of the gain of the high-frequency amplifier and the frequency conversion mixer inside the high-frequency receiving unit, and the amplitude fluctuation component is lost. Therefore, it is difficult to extract the timing in the amplitude information detection unit, and there is a disadvantage that the baud timing cannot be given to the demodulation unit.

【0004】本発明は、このような欠点を除去するもの
で、常に振幅成分を検出できるディジタル受信機を提供
することを目的とする。
An object of the present invention is to eliminate such a disadvantage and to provide a digital receiver which can always detect an amplitude component.

【0005】[0005]

【課題を解決するための手段】本発明は、四相位相変調
された高周波受信信号を入力して中間周波信号を出力す
る高周波受信部と、上記高周波受信部から中間周波信号
を入力して与えられたボー・タイミングに応じてディジ
タル信号を抽出して出力する復調部と、上記高周波受信
部から中間周波信号を入力してその振幅変動成分を検出
し、上記復調部にボー・タイミングを与える振幅情報検
出部とを備えたディジタル受信機において、上記高周波
受信部から中間周波信号を入力してその電界強度成分を
検出し、この検出結果に応じて上記高周波受信部の利得
を制御する電界情報検出部を備えたことを特徴とする。
According to the present invention, there is provided a high-frequency receiving section for inputting a high-frequency receiving signal subjected to four-phase modulation and outputting an intermediate-frequency signal, and inputting and providing an intermediate-frequency signal from the high-frequency receiving section. A demodulator for extracting and outputting a digital signal in accordance with the baud timing obtained, an intermediate frequency signal being input from the high frequency receiver, detecting an amplitude variation component thereof, and providing an amplitude for giving the baud timing to the demodulator. A digital receiver provided with an information detecting section, an intermediate frequency signal is input from the high frequency receiving section to detect an electric field intensity component thereof, and electric field information detecting section controls a gain of the high frequency receiving section in accordance with a result of the detection. It is characterized by having a part.

【0006】ここで、上記電界情報検出部は、上記高周
波受信部から入力した中間周波信号の電界強度成分を上
記振幅情報検出部で得られたボー・タイミングごとに検
出する構成であることが望ましい。
Here, it is desirable that the electric field information detecting section detects the electric field intensity component of the intermediate frequency signal input from the high frequency receiving section for each baud timing obtained by the amplitude information detecting section. .

【0007】[0007]

【作用】入力信号の電界強度を検出し、強電界入力時に
高周波受信部の利得を下げて同部出力が飽和しないよう
に制御する。これにより、強電界入力時でもボー・タイ
ミングを抽出して復調時に振幅成分を常に検出できる。
The electric field strength of the input signal is detected, and the gain of the high-frequency receiving unit is reduced so that the output of the high-frequency receiving unit is not saturated when a strong electric field is input. As a result, even when a strong electric field is input, the baud timing is extracted and the amplitude component can always be detected during demodulation.

【0008】[0008]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1はこの実施例のブロック図である。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment.

【0009】この実施例は、図1に示すように、四相位
相変調された高周波受信信号を入力して中間周波信号を
出力する高周波受信部1と、高周波受信部1から中間周
波信号を入力して与えられたボー・タイミングに応じて
ディジタル信号を抽出して出力する復調部2と、高周波
受信部1から中間周波信号を入力してその振幅変動成分
を検出し、復調部2にボー・タイミングを与える振幅情
報検出部4とを備え、さらに、本発明の特徴とする手段
として、高周波受信部1から入力した中間周波信号の電
界強度成分を振幅情報検出部4で得られたボー・タイミ
ングごとに検出し、この検出結果に応じて高周波受信部
1の利得を制御する電界情報検出部3を備える。
In this embodiment, as shown in FIG. 1, a high-frequency receiving unit 1 for inputting a four-phase modulated high-frequency receiving signal and outputting an intermediate-frequency signal, and an intermediate-frequency signal input from the high-frequency receiving unit 1 A demodulation unit 2 that extracts and outputs a digital signal in accordance with the given baud timing, and an intermediate frequency signal that is input from the high frequency receiving unit 1 to detect an amplitude fluctuation component thereof. And an amplitude information detecting unit 4 for giving a timing. Further, as a characteristic feature of the present invention, a baud timing obtained by the amplitude information detecting unit 4 is used to obtain an electric field intensity component of the intermediate frequency signal input from the high frequency receiving unit 1. And an electric field information detector 3 for controlling the gain of the high frequency receiver 1 according to the detection result.

【0010】次に、この実施例の動作を説明する。高周
波受信部1に入力された四相位相変調信号は中間周波信
号に変換されて出力され、復調部2で復調されてディジ
タル信号として出力される。ここで、復調部2でディジ
タル信号を抽出するボー・タイミングは、上述の中間周
波信号から振幅変動成分を検出してタイミングを抽出す
る振幅情報検出部4から与えられる。同時に、電界情報
検出部3では、中間周波信号から電界の強度をボー・タ
イミングごとに監視している。ここで、強電界の四相位
相変調信号が入力された場合に高周波受信部1内部のト
ランジスタ等の能動素子の飽和作用によりその振幅の中
間周波信号が飽和するが、このときに電界情報検出部3
が強電界状態を検出して高周波受信部1の利得を下げ、
中間周波信号の飽和を回避する。また、電界検出をボー
・タイミングごとに行っているのは、四相位相変調信号
による振幅変動のためにボー・タイミングでしか正確な
情報が得られないためである。
Next, the operation of this embodiment will be described. The four-phase modulated signal input to the high-frequency receiver 1 is converted into an intermediate-frequency signal and output, demodulated by the demodulator 2 and output as a digital signal. Here, the baud timing at which the demodulation unit 2 extracts a digital signal is given from the amplitude information detection unit 4 that detects an amplitude fluctuation component from the above-mentioned intermediate frequency signal and extracts the timing. At the same time, the electric field information detector 3 monitors the electric field strength from the intermediate frequency signal at each baud timing. Here, when a four-phase phase modulation signal of a strong electric field is input, the intermediate frequency signal of the amplitude is saturated due to the saturation action of an active element such as a transistor inside the high-frequency receiving unit 1; 3
Detects a strong electric field condition and lowers the gain of the high-frequency receiver 1,
Avoid saturation of the intermediate frequency signal. The reason why the electric field detection is performed at each baud timing is that accurate information can be obtained only at the baud timing due to amplitude fluctuations due to the four-phase modulation signal.

【0011】また、図2は他実施例のブロック図であ
る。ここでは、ディジタル受信機としてダブルスパーヘ
テロダイン型のものを用い、かつ振幅および電界情報の
検出をRSSI(Recieved Signal S
trength Indicator)信号で共用して
いる。また図3は入力電界に対するRSSI信号の出力
特性である。ここで、アンテナ5に入力された四相位相
変調信号は第一ミキサ10で第一中間波信号に変換さ
れ、さらに第二ミキサ13で第二中間波信号に変換され
る。そして、中間波アンプ16を介してディジタル検波
部17でディジタル信号として検出され、データ端子2
1からディジタルデータが出力され、またクロック端子
22からそのクロック成分が出力される。また、ビット
同期部19は中間波アンプ16から出力されるRSSI
信号から振幅変動成分を検出し、ディジタル検波部17
にディジタル信号を検出するときのボー・タイミングを
与える。ここで、コンパレータ18は基準電圧Vref す
なわち図3に示された電圧V1に設定され、コンパレー
トするタイミングとして上記のボー・タイミングが与え
られている。すなわち、V1 はRSSI出力が飽和状態
となる直前の入力電界Aのときの出力電圧である。ま
た、スイッチ9は、通常オン状態で高周波アンプ7に電
圧を供給している。この状態で、アンテナ5に入力され
た四相位相変調信号の電界が上がると、RSSI出力電
圧も同時に上昇する。このときに入力電界がA点を超え
ると、コンパレータ18の出力が反転してスイッチ9が
オフ状態になり、高周波アンプ7に電圧が供給されなく
なるので、そこでの利得が低減される。その結果として
見かけ上の入力電界が減り、RSSIの出力電圧が低下
する。この実施例では、高周波アンプ7の電源をコント
ロールしているが、必要に応じて第一ミキサおよび第二
ミキサの電源もコントロールすることも可能である。
FIG. 2 is a block diagram of another embodiment. Here, a double-spar heterodyne type digital receiver is used, and the detection of amplitude and electric field information is performed by RSSI (Received Signal S).
(Trainth Indicator) signal. FIG. 3 shows the output characteristics of the RSSI signal with respect to the input electric field. Here, the four-phase modulated signal input to the antenna 5 is converted into a first intermediate signal by the first mixer 10 and further converted to a second intermediate signal by the second mixer 13. Then, the signal is detected as a digital signal by the digital detector 17 via the intermediate wave amplifier 16 and the data terminal 2
1 outputs digital data, and the clock terminal 22 outputs its clock component. Further, the bit synchronization unit 19 is configured to output the RSSI output from the intermediate wave amplifier 16.
The amplitude fluctuation component is detected from the signal,
Gives the baud timing for detecting the digital signal. Here, the comparator 18 is set to the reference voltage Vref, that is, the voltage V1 shown in FIG. 3, and the above-mentioned baud timing is given as a comparison timing. That is, V1 is the output voltage at the time of the input electric field A immediately before the RSSI output becomes saturated. The switch 9 supplies a voltage to the high-frequency amplifier 7 in the normal ON state. In this state, when the electric field of the four-phase modulation signal input to the antenna 5 increases, the RSSI output voltage also increases. At this time, if the input electric field exceeds the point A, the output of the comparator 18 is inverted and the switch 9 is turned off, so that no voltage is supplied to the high frequency amplifier 7, so that the gain there is reduced. As a result, the apparent input electric field decreases, and the output voltage of the RSSI decreases. In this embodiment, the power supply of the high-frequency amplifier 7 is controlled, but it is also possible to control the power supplies of the first mixer and the second mixer as needed.

【0012】[0012]

【発明の効果】本発明は、以上説明したように、強電界
が入力した場合に受信機の利得を低下させて受信機が飽
和状態になることを回避するので、振幅変動成分を常に
良好に検出でき、安定したボー・タイミングを与えるこ
とができる効果がある。
As described above, according to the present invention, when a strong electric field is input, the gain of the receiver is reduced to prevent the receiver from becoming saturated, so that the amplitude fluctuation component can always be improved. This has the effect of being able to detect and provide stable baud timing.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明第一実施例の構成を示すブロック構成
図。
FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

【図2】本発明第二実施例の構成を示すブロック構成
図。
FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention.

【図3】本発明第二実施例での電界強度情報の特性を示
す図。
FIG. 3 is a diagram showing characteristics of electric field intensity information in a second embodiment of the present invention.

【図4】従来例の構成を示すブロック構成図。FIG. 4 is a block diagram showing a configuration of a conventional example.

【符号の説明】[Explanation of symbols]

1 高周波受信部 2 復調部 3 電界情報検出部 4 振幅情報検出部 5 アンテナ 6 アンテナフィルタ 7 高周波アンプ 8 段間フィルタ 9 スイッチ 10 第一ミキサ 11 第一局部発振器 12 第一中間波フィルタ 13 第二ミキサ 14 第二局部発振器 15 第二中間波フィルタ 16 中間波アンプ 17 ディジタル検波部 18 コンパレータ(COMP) 19 ビット同期部 20 電源端子 21 データ端子 22 クロック端子 23 基準電圧端子 DESCRIPTION OF SYMBOLS 1 High frequency reception part 2 Demodulation part 3 Electric field information detection part 4 Amplitude information detection part 5 Antenna 6 Antenna filter 7 High frequency amplifier 8 Interstage filter 9 Switch 10 First mixer 11 First local oscillator 12 First intermediate wave filter 13 Second mixer 14 Second Local Oscillator 15 Second Intermediate Wave Filter 16 Intermediate Wave Amplifier 17 Digital Detector 18 Comparator (COMP) 19 Bit Synchronizer 20 Power Supply Terminal 21 Data Terminal 22 Clock Terminal 23 Reference Voltage Terminal

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 四相位相変調された高周波受信信号を入
力して中間周波信号を出力する高周波受信部と、 上記高周波受信部から中間周波信号を入力して与えられ
たボー・タイミングに応じてディジタル信号を抽出して
出力する復調部と、 上記高周波受信部から中間周波信号を入力してその振幅
変動成分を検出し、上記復調部にボー・タイミングを与
える振幅情報検出部とを備えたディジタル受信機におい
て、 上記高周波受信部から中間周波信号を入力してその電界
強度成分を検出し、この検出結果に応じて上記高周波受
信部の利得を制御する電界情報検出部を備え 上記電界情報検出部は、上記高周波受信部から入力した
中間周波信号の電界強度成分を上記振幅情報検出部で得
られたボー・タイミングごとに検出する構成である を備
えたことを特徴とするディジタル受信機。
1. A high-frequency reception signal modulated by four-phase modulation is input.
A high-frequency receiving unit for outputting an intermediate-frequency signal by inputting an intermediate-frequency signal from the high-frequency receiving unit.
Digital signal according to the baud timing
An output demodulation unit, and an intermediate frequency signal input from the high frequency reception unit and its amplitude
Detects fluctuation components and gives baud timing to the demodulation unit.
Digital receiver equipped with an amplitude information detector
Input the intermediate frequency signal from the high frequency
The intensity component is detected, and the high-frequency reception is performed according to the detection result.
Equipped with an electric field information detector that controls the gain of the, The electric field information detection unit is input from the high frequency reception unit
The electric field strength component of the intermediate frequency signal is obtained by the amplitude information detector.
It is a configuration that detects each set baud timing Be prepared
A digital receiver characterized by the following.
JP3145497A 1991-05-20 1991-05-20 Digital receiver Expired - Fee Related JP2827581B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3145497A JP2827581B2 (en) 1991-05-20 1991-05-20 Digital receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3145497A JP2827581B2 (en) 1991-05-20 1991-05-20 Digital receiver

Publications (2)

Publication Number Publication Date
JPH04343547A JPH04343547A (en) 1992-11-30
JP2827581B2 true JP2827581B2 (en) 1998-11-25

Family

ID=15386630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3145497A Expired - Fee Related JP2827581B2 (en) 1991-05-20 1991-05-20 Digital receiver

Country Status (1)

Country Link
JP (1) JP2827581B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2885267B2 (en) 1994-07-15 1999-04-19 日本電気株式会社 Digitally modulated signal receiver

Also Published As

Publication number Publication date
JPH04343547A (en) 1992-11-30

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