JPS61166231A - Radio receiver - Google Patents

Abstract

PURPOSE:To improve the operability and to prevent fading distortion by providing a switching circuit of filter time constant and providing a detection circuit whether or not the tuning operation is executed so as to use a detection output of the said detection thereby switching the filter time constant. CONSTITUTION:A signal Sw is formed based on signals Se, Sg and outputs of switches S1-Sn, when the signal Se or an output of the switches S1-Sn are obtained, the level of Sw is logical '1' and when the signal Sg is not obtained either, the level of Sw is logical '1', and when the signal Se and the output of the switch S1-Sn are not obtained but the signal Sg is obtained, the level of Sw is logical '0'. Since the signal Se or the output of the switches S1-Sn, the level of Sw is logical '1' and a switch 4 is turned on. Then when a broadcast is received, the signal Se and the output of the switches S1-Sn are not obtained but the signal Sg is obtained, the level of Sw is logical '0'.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a radio receiver.

[Conventional technology]

A radio receiver that performs synchronous detection using a PLL can be configured as shown in FIG. 2, for example.

That is, in the same figure, a received signal received by an antenna (1) is supplied to a bandpass filter (2), and a signal of a desired band to be received, for example, a frequency of 530kHz is supplied.
A signal of z~10MHz is extracted and this signal is supplied to the mixer circuit (3), and a local oscillation signal So of a predetermined frequency is sent from the local oscillation circuit (4) to the mixer circuit (3).
Only the signal of the desired frequency to be received is frequency-converted into an intermediate frequency signal Si with a frequency of 450 kHz, and this signal St is supplied to a multiplier circuit for synchronous detection (6) through an intermediate frequency amplifier (5). , phase comparator circuit (
11).

This comparison circuit (11) constitutes a PLL (10) together with a low-pass filter (12) and a VCO (13), and an oscillation signal Sv whose free running frequency is equal to the intermediate frequency is taken out from the VCO (13). , this signal Sv is supplied to a comparison circuit (11) and compared in phase with the signal St, and the comparison output is sent to the VCO through a low-pass filter (12).
(13) as its control voltage, the signal Sv is synchronized with the signal St.

This signal Sv is then supplied to a phase shift circuit (20) and phase-shifted to a signal Ss having the same phase as the signal Si.
is supplied to the multiplication circuit (6) and multiplied by the signal Si, and the multiplication output is supplied to the low-pass filter (7) to extract the audio signal Sa, which is sent to the speaker (9) through the amplifier (8). ).

Further, a part of the signal Si is supplied to a forming circuit (22) to form an AGC signal S, and this signal Sg is supplied to an intermediate frequency amplifier (5) to perform AGC.

In this case, the local oscillator circuit (4) is constituted by PLL, and the control signal Sc is supplied to the local oscillator circuit (4), and the local oscillator signal So is transmitted in predetermined frequency steps, for example, in 9 kHz steps in the medium wave band, and short wave. In the band, it is changed in 5kHz steps. Therefore, the receiving frequency is 9kllz steps in the medium wave band and 5kHz in the short wave band, corresponding to the signal Sc.
It will change in steps.

Furthermore, (30) is a control circuit for controlling the receiving frequency, which is composed of, for example, a 4-bit processing microcomputer, and includes a normally open, non-locking type tuning switch 81.
~Sn and a preset switch Sp are connected.

Further, (42) is a rotary encoder, and its input shaft (controlled axis) is provided with a knob (41) for manual operation, and the encoder (42) indicates the direction and amount of rotation of the knob (41). The output signal Se is taken out,
This signal Se is supplied to the microcomputer (30).

Therefore, without turning the knob (41), the signal Sc is changed based on the signal Se, and thereby the signal S.

changes, and the receiving frequency changes by one step. In other words, when the knob (41) is turned clockwise, the receiving frequency changes by one step.
It will be raised one step at a time, and lowered one step at a time when counterclockwise. Therefore, the receiving frequency can be changed or set using the knob (41).

Furthermore, when receiving an arbitrary receiving frequency f, if any switch Sj (1≦j≦n) among the switches 81 to Sn is turned on while turning on the switch Sp, the data of that frequency f□ is is the address A corresponding to the switch Sj among the addresses of the memory of the microcomputer (30).
Stored in j. Therefore, arbitrary frequencies can be preset to the switches 81 to Sn.

Then, any switch ′ of the switches 81 to Sn
When the switch sj is turned on, the frequency f is changed from the address Aj.
The data of t is retrieved and based on this data the signal SC
is formed, the signal So is controlled, and the reception state of the frequency ri is established. Therefore, if the switch switches 81 to 81 to Sn are turned on, the receiving state is established at the frequency preset to the switch.

Then, in any reception state, the signal Si is
Based on the signal Sv of (10), it is demodulated into a signal Sa by synchronous detection.

In this way, in this receiver, the PLL performs synchronous detection and demodulates the audio signal (Reference: Utility Model Publication No. 53
-10821 publication).

[Problem that the invention seeks to solve]

However, in this case, the natural frequency ω□ of PLL (10)
However, the following contradictory problems arise. That is, 1. During the m operation (tuning operation), the intermediate frequency (carrier frequency) changes in accordance with the m operation. If the natural frequency ωn is low, the oscillation frequency of ■Co(13) will not be able to follow the change in the intermediate frequency during the tuning operation, and even if it can do so, there will be a delay, and this will cause the tuning to the positive tuning point. Even if this happens, it is difficult to understand, making it difficult to synchronize. Therefore, it is better for the natural frequency ωn to be high during the tuning operation.

ii. During broadcast reception, when the carrier component becomes lower level than the sideband component due to selective pressure fading,
In the comparison circuit (11), the sideband component and the signal SO are compared in phase, and as a result, the signal S
Since the frequency or phase of O varies, the signal Sa becomes highly distorted. Therefore, during reception, it is better to have a longer hold time, and for this purpose, it is better to have a lower natural frequency ωn.

In this way, the PLL (10) requires contradictory conditions or operations.

For this reason, in the past, the natural frequency ωn was determined based on the balance between ease of tuning and reduction of distortion during selective facing. In other words, ease of synchronization and selection +! The performance was not sufficient in terms of distortion during fading.

This invention attempts to solve these problems.

[Means for solving problems]

Therefore, in the present invention, a circuit for switching the time constant of the filter (12) is provided, and a detection circuit for detecting whether or not the same fJl operation is being performed is provided, and the detection output of this detection circuit is used to determine the time constant of the filter (12). The constants are changed to satisfy the above-mentioned terms i and 11.

[Effect]

Therefore, during synchronization operation, the operability is improved (, moreover,
In the receiving state, distortion due to selective fading can be reduced.

〔Example〕

That is, in FIG. 1, transistor Qt.

C2 is configured with a Darlington connection and its emitter is grounded, and a resistor R1 is connected between the output terminal of the comparator circuit (11) and the base of the transistor Q1.
A series circuit of a switch circuit (14) and a resistor R2 is connected in parallel, and a resistor R3 and a capacitor C1 are connected between the base of the transistor Q1 and the collector of the transistor Q2.
A series circuit is connected to constitute a low-pass filter (11). Note that R1>>R2.

Further, it is supplied to the microcomputer (30) as a detection signal for sending the AGC signal S, and a control signal Sw is formed in the microcomputer (30), and this signal Sw is supplied to the switch circuit (14). In this case, the signal Sw is formed based on the signal S e + S g and the outputs of the switches 81 to Sn, and is formed based on the signal Se or the outputs of the switches 81 to Sn.
When the output of Sn is obtained, Sw=“1”, and when it is not obtained and also when the signal Sg is not obtained, Sw-“1”, the signal Se and the switches 81 to Sn
When the output is not obtained and the signal sg is obtained, Sw-“θ” is set.

Further, when the signal Se or the outputs of the switches 31 to Sn change from a state where they are obtained to a state where they are not obtained, that is, the signal sc changes and the signal s changes.

Even when the frequency of the signal So changes, Sw is set to "1" for, for example, 0.1 to 0.5 seconds after the frequency of the signal So stops changing.

Further, the switch circuit II (14) is constituted by a transfer gate, etc., and is turned off when Sw="0", and is turned off when 511
-1'', it is turned on.

In such a configuration, during the channel selection operation using the knob (41) or switches 81 to Sn, the signal Se or the output of the switches 81 to Sn is obtained.
-1'', and the switch circuit (14) is on. Therefore, in this state, resistor R2 is connected in parallel to resistor R1, and the time constant of the filter (11) is small, that is, the PLL (10) The natural frequency ω and the damping coefficient ζ are alfi−(K/(R2C1)) v2′,
'R1>>R2 ζ=-ωnR3C1: becomes a loop gain, and by selecting the value of element R21C1 in advance, the natural frequency ω is set. can be made higher.

In addition, even if you can receive the broadcast by selecting the channel, it will be 0.1 to 0.
Since Sw remains at "l" for 5 seconds, the natural frequency ω. remains high.

Therefore, it is possible to achieve the i term, and when operating the channel selection, especially when
During the channel selection operation according to 1), it becomes easier to open the channel.

Then, in the state where broadcasting is being received, the signal Se and the output of the switch 5i=Sn are not obtained, and the signal Sg is obtained, so 5ty - "0" and the switch circuit (
14) is off. Therefore, in this state, the time constant of the filter (11) is large, that is, the PLL (10)
The natural frequency ω□ and damping coefficient ζ are ω. -(K/(Rx Ct)) 1'ζ=-ωn
R3C1, and by selecting the values of elements R1 and C1 in advance, the natural frequency ω□ can be made sufficiently low. Therefore,
11 can be achieved, and distortion due to selective fading can be reduced.

In addition, when the standby mode is in a state where no broadcast is being made even if the same side is set to a certain frequency, such as during reception, Sw=“1” and the switch circuit (14) is on. Therefore, in this state, the natural frequency ω. Since the signal Si is high, when a broadcast is received, the PLL (10) immediately locks onto the signal Si and enters the receiving state.

In this way, according to the present invention, the time constant of the filter (11) is switched between during channel selection operation and during reception, and thereby the PL
Since the '+fi term is achieved by changing the natural frequency ωn of L(10), the feeling is good during tuning operation, and distortion due to selective fading is reduced during reception. Furthermore, if the standby is broadcast even when receiving,
You can immediately enter the receiving state.

In addition, when an envelope detection circuit is also provided, when switching from the envelope detection to the above-mentioned synchronous detection, the switch circuit (14) is similarly turned on temporarily to detect the natural frequency ω. It is better to make it higher.

〔Effect of the invention〕

According to this invention, the filter (
11), thereby switching the time constant of PLL (10).
natural frequency ω. Since the f+I1 term is achieved by changing the channel, the feeling is good during the channel selection operation, and distortion due to selective fading is reduced during reception. Furthermore, even during reception, if a broadcast is made, the standby mode can immediately enter the reception state.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the same. (10) is a PLL.

Claims (1)

[Claims] In a radio receiver that supplies an intermediate frequency signal to a PLL and performs synchronous detection of the intermediate frequency signal using the output signal of this PLL, when changing the reception frequency, the natural frequency ωn of the PLL is increased, and the A radio receiver that lowers the natural frequency ωn while receiving a broadcast.