JPH0722291B2 - Demodulator for frequency modulated signal - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a demodulator for a frequency modulation signal that demodulates an FSK signal (a signal in which a carrier wave is frequency-modulated by a pulse) or an analog frequency modulation signal.

<Prior Art> Conventionally, as a FSK demodulator using a PLL, a demodulator as shown in the block diagram of FIG. 3 is generally used in data communication and the like.

This demodulator is provided with two low-pass filters 23 on the output side of a PLL circuit including a phase comparator 21 for inputting an FSK signal, a low-pass filter 22, a DC amplifier 24, and a voltage controlled oscillator (VCO) 25. It is configured by connecting comparators 26 and 27. Two comparators 2
Reference numerals 6 and 27 are provided so as to stably output the output signal against DC drift in the circuit.
Operates to supply an intermediate level signal as a reference value to the reference input side of the upper comparator 26 so that each of the high level signal and the low level signal can be correctly determined.
The reference value of the comparator 26 is corrected for DC drift so that an accurate pulsed demodulated signal can be obtained.

<Problems to be Solved by the Invention> However, in this FSK demodulator, the comparator 27 for producing the reference value operates like an integrator, and the high level and low level of the pulse signal sent from the low-pass filter 23. Since it operates so as to supply a reference signal having an intermediate level of the level to the reference input side of the upper comparator 26, there is no problem as long as it is a data signal in which marks and spaces are repeated. If it continues for a certain period of time, the level of the reference signal drops to near the low level, while if the mark signal continues for a certain period of time, the level of the reference signal rises to near the high level. Therefore, there is almost no difference between the reference value and the high level or low level of the signal in the comparator 26, and the correct demodulated signal cannot be obtained from the comparator 26. For this reason, in a conventional data communication device using this type of demodulator, a signal that repeats marks and spaces is transmitted for a certain period of time before sending data, and data is input following this signal for input processing. ing.

<Means for Solving Problems> The present invention has been made in consideration of the above points, and is “0”.
Further, the present invention provides a demodulator for a frequency modulation signal, which can stably and accurately demodulate even when an FSK signal or a frequency modulation signal in which "1" continues is input,
It is configured as follows.

That is, the demodulator for frequency modulation signal of the present invention inputs an oscillator for outputting a fundamental frequency signal, a frequency modulation signal and a fundamental frequency signal, and alternately selects and outputs the two signals at a constant cycle. At least during the period when the second data selector described below outputs the fundamental frequency signal, the first data selector that outputs the frequency modulation signal and the frequency modulation signal and the fundamental frequency signal are input, and the first data selector is about half a cycle. The second signal that outputs the frequency-modulated signal at least while the fundamental frequency signal is being output by the first data selector while the two signals are alternately selected and output
A data selector, a first FM demodulator that demodulates the frequency signal output from the first data selector and outputs a voltage signal, and a second FM demodulator that demodulates the frequency signal output from the second data selector and outputs a voltage signal In the voltage signal output from the first FM demodulator, a portion corresponding to the fundamental frequency signal in the voltage signal output from the first FM demodulator is sample-held and the voltage is output as a reference value, and in the voltage signal output from the second FM demodulator. The second sample and hold circuit that samples and holds the part corresponding to the fundamental frequency signal and outputs the voltage as a reference value, and the voltage signal from the first FM demodulator and the reference value from the first sample and hold circuit 5 are input and compared. Alternatively, the first comparator or the first subtractor for subtraction, the voltage signal from the second FM demodulator, and the reference value from the second sample and hold circuit are input and compared. Or enter the second comparator or a second subtractor for subtracting the signal output from the first comparator or the first subtractor and the second comparator and the second subtractor,
A data selector that alternately selects both signals so as to extract a portion corresponding to the frequency-modulated signal included in both signals and outputs a demodulated signal.

<Example> Hereinafter, an example of the present invention is described based on a drawing.

-Structure of Embodiment- FIG. 1 is a block diagram of a frequency modulation signal demodulator for inputting and demodulating an FSK signal, and the first data selector for inputting and selectively outputting the FSK signal at the first stage on the input side. 1
And a second data selector 2 are provided. These first and second
The data selectors 1 and 2 are composed of gate circuits, and have first and second select signals a, which are applied from a control circuit 11 described later.
The input FSK signal is selected and output while b is at a high level, and the fundamental frequency signal Sfo sent from the oscillator 10 is selectively output during a low level. The frequency fo of the fundamental frequency signal Sfo output from the oscillator 10 is determined to be an intermediate frequency between the mark frequency fe and the space frequency fh in the FSK signal. For example, the mark frequency fe = 1070 Hz, the space frequency fh When = 1270 Hz, the frequency fo of the basic frequency signal Sfo is 1170 Hz.

A first FM demodulator 3 is connected to the output side of the first data selector 1. The first FM demodulator 3 is, for example, a general demodulator that uses a PLL (phase locked loop), and is composed of a phase comparator, a voltage controlled oscillator, a low-pass filter, etc., and outputs a frequency modulation signal to a voltage level corresponding to the modulation frequency. It outputs as a voltage signal of. A second FM demodulator 4 having a similar configuration is also connected to the output side of the second data selector 2. In addition,
The first select signal a applied from the control circuit 11 to the first data selector 1 is a square wave signal of about 40% duty having a cycle substantially the same as the pulse cycle of the input FSK signal, and the second select signal b is It is a square wave signal having the same period as the first select signal a and having a phase shifted by about 180 degrees,
At high level, the first and second data selectors 1 and 2 select the basic frequency signal Sfo. That is, the first data selector 1 outputs the frequency modulation signal at least during the period when the second data selector 2 outputs the fundamental frequency signal,
The second data selector 2 outputs the frequency modulation signal at least while the basic frequency signal is being output by the first data selector.

The output side of the first FM demodulator 3 is connected to the first sample and hold circuit 5 and the first comparator 7, and the output side of the second FM demodulator 4 is connected to the second sample and hold circuit 6 and the second comparator 8. To be done. The first sample and hold circuit 5 receives the sampling signal c from the control circuit 11 and outputs the signal c
When is high level, the input voltage signal g is sampled and held and output. The sampling signal c is generated when the first select signal a is at a high level, that is, within the time when the basic frequency signal Sfo is selected in the first data selector 1.
On the other hand, similarly, the second sample hold circuit 6 also inputs the sampling signal d from the control circuit 11, and when this signal is at a high level, samples and holds the input voltage signal h and outputs it. The sampling signal d is generated when the second select signal b is at a high level, that is, within the time when the basic frequency signal Sfo is selected in the second data selector 2.

The output side of the first sample and hold circuit 5 is connected to the reference value input side of the first comparator 7, and the first comparator 7 outputs the voltage signal g sent from the first FM demodulator 3 and the first sample and hold circuit 5. The signals of 1 and 2 are compared, and when the voltage signal g is higher, the high level signal i is output. On the other hand, the output side of the second sample hold circuit 5 is connected to the reference value input side of the second comparator 8, and the second comparator 8 receives the voltage signal h sent from the second FM demodulator 4 and the second sample hold circuit. The signals from 6 are compared, and when the voltage signal h is higher, the high level signal j is output.

The output sides of the first comparator 7 and the second comparator 8 are connected to the data selector 9, respectively. The data selector 9 is composed of a gate circuit, receives the select signal e applied from the control circuit 11, and when the select signal e is at a high level, selects and outputs the signal i output from the first comparator 7. When e is low level, the signal j output from the second comparator 8 is selected and output. The select signal e sent from the control circuit 11 is synchronized with the signals a and b so that it falls at the timing when the first select signal a rises and rises at the timing when the second select signal b rises. It is a square wave signal with 50% duty.

The control circuit 11 has a structure for generating the above-described first select signal a, second select signal b, sampling signals c, d, and select signal e at a predetermined timing.

Operation of Embodiment Next, the operation of the demodulator for frequency-modulated signals having the above-described configuration will be described below.
A description will be given with reference to the timing chart in the figure.

The input FSK signal is a signal in which, for example, a mark of frequency fe and a space of frequency fh are repeated in a random cycle as shown in the upper part of FIG. First data selector 1 and second
This FSK signal is input to the data selector 2, and at the same time, the oscillator 10 outputs the fundamental frequency signal Sfo (frequency f between the fe and fh).
signal having o) is input to the first and second data selectors 1 and 2. Then, the first select signal a is applied from the control circuit 11 to the first data selector 1, and the first data selector 1 selects the basic frequency signal Sfo when this signal a is at high level and the FSK signal when it is at low level. The output of the first data selector becomes a signal in which the basic frequency signal Sfo of the frequency fo is inserted while the frequencies fe and fh are repeated as shown in FIG. On the other hand, the second select signal b is applied to the second data selector 2, and when the signal b is at a high level, the basic frequency signal Sfo is selected, and when the signal b is at a low level, the FSK signal is selected. Similarly to the above, the output of the 2-data selector 2 is a signal in which the basic frequency signal Sfo of the frequency fo is inserted while the frequencies fh and fe are repeated. The fundamental frequency portions in the output signals of the first data selector 1 and the second data selector 2 are out of phase by about 180 degrees. Then, the outputs of the first data selector and the second data selectors 1 and 2 are sent to the first and second FM demodulators 3 and 4, respectively, where they are demodulated to generate voltage signals having a voltage level according to the frequency. g and the voltage signal h are output. This voltage signal h is sent to the first sample and hold circuit 5, and sampling is performed at the timing of the sampling signal c in the first sample and hold circuit 5, and the intermediate voltage of the portion of the voltage signal g at the fundamental frequency fo is compared by the first comparison. It is input to the container 7 as a reference value. On the other hand, the voltage signal h is sent to the second sample and hold circuit 6, and sampling is performed at the timing of the sampling signal d in the second sample and hold circuit 6, so that the intermediate voltage of the portion of the basic frequency fo in the voltage signal h becomes the second value. It is input to the comparator 8 as a reference value. Then, in the first comparator 7, the input voltage signal g is compared with the reference value of the sampled intermediate voltage, and when the voltage signal g is higher, it is at high level, and when it is lower, it is at low level. Is output from the first comparator 7. In the portion corresponding to the fundamental frequency fo in this signal i (exactly, the portion excluding the transitional period when the frequency shifts from another frequency region to the fundamental frequency region), the two voltages input to the first comparator 7 are substantially the same. Therefore, it becomes a signal area in which high and low are repeated (hatched portion in FIG. 2). Further, the signal i shows a portion that rises at the end of the mark of frequency fe and falls at the end of the space of frequency fh. On the other hand, in the second comparator 8, the input voltage signal h is compared with the reference value of the sampled intermediate voltage, and when the voltage signal h is higher, it is at high level, and when it is lower, it is at low level. Is output from the second comparator 8. In the portion corresponding to the fundamental frequency fo in this signal j (exactly, the portion excluding the transitional period when shifting from another frequency region to the fundamental frequency region), the two voltages input to the second comparator 8 are almost the same. Therefore, it becomes a signal area in which high and low are repeated (hatched portion in FIG. 2). Also, the signal j appears at the end of the space of the frequency fh, that is, at the beginning of the mark of the frequency fe.

Both the signal i and the signal j are input to the data selector 9, and the data selector 9 periodically and alternately selects and outputs the signals i and j based on the select signal e sent from the control circuit 11. That is, when the select signal e is high level, the signal i is selected, when it is low level, the signal j is selected, and the select signal e falls in synchronization with the rising of the first select signal a and the second select signal b. Since it is a square wave signal of 50% duty that rises in synchronization with the rising edge of, the demodulated output signal that becomes a low level “0” at the mark part of the frequency fe and a high level “1” at the space part of the frequency fh is the data. Obtained from the selector 9.

In this way, a part of the voltage signal obtained by demodulating the intermediate frequency signal between the mark and the space is sampled and held as the reference value of the comparator, so that stable operation can be performed against temperature changes. Accurate demodulation can be performed even when signals are continuously input or mark signals are continuously input.

Although the circuit for demodulating the FSK signal has been described in the above embodiment, if the first comparator 7 and the second comparator 8 are replaced by subtractors and the data selector 9 is a data selector for analog signals, It is also possible to demodulate a general frequency modulation signal in which a carrier wave is frequency-modulated with an analog signal.

<Effects of the Invention> As described above, according to the demodulator for frequency-modulated signal of the present invention, a part of the voltage signal obtained by demodulating the fundamental frequency signal is sample-held and the reference of the comparator or subtractor is obtained. Since the value is set, accurate demodulation is possible even when an FSK signal that continues to be "0" or "1" is input, as in the conventional FSK demodulator, and it is relatively easy even with temperature changes. The circuit can be stably operated, and adjustments due to variations in the characteristics of each circuit component are facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart of input / output signals of each block diagram, and FIG. 3 is a block diagram of a conventional FSK demodulator. 1 ... 1st data selector, 2 ... 2nd data selector, 3
... 1st FM demodulator, 4 ... 2nd FM demodulator, 5 ... 1st sample hold circuit, 6 ... 2nd sample hold circuit, 7 ... 1st
Comparator, 8 ... Second comparator, 9 ... Data selector, 10 ... Oscillator.

Claims (2)

[Claims] 1. An oscillator for oscillating and outputting a fundamental frequency signal, a frequency modulation signal and the fundamental frequency signal are input, and the two signals are alternately selected and output at a constant cycle, and at least a second data selector described later. During the period in which the fundamental frequency signal is output at, the first data selector that outputs the frequency modulation signal, the frequency modulation signal and the fundamental frequency signal are input, and the first data selector deviates from the first data selector by about a half cycle. Two signals are alternately selected and output, and at least during the period when the basic frequency signal is being output by the first data selector, a second data selector that outputs the frequency modulated signal; and a first data selector A first FM demodulator that demodulates the output frequency signal and outputs a voltage signal, and a frequency signal that demodulates the frequency signal output from the second data selector and outputs a voltage signal. A second FM demodulator, a first sample-hold circuit that samples and holds a portion of the voltage signal output from the first FM demodulator, the portion corresponding to the fundamental frequency signal, and outputs the voltage as a reference value, the second FM A second sample and hold circuit for sampling and holding a portion of the voltage signal output from the demodulator corresponding to the fundamental frequency signal, and outputting the voltage as a reference value; a voltage signal from the first FM demodulator and the first sample A first comparator for inputting and comparing a reference value from a hold circuit; a second comparator for inputting and comparing a voltage signal from the second FM demodulator and a reference value from the second sample and hold circuit; The signals output from the first comparator and the second comparator are input, and both signals are alternately selected so as to extract a portion corresponding to the frequency modulation signal included in both signals. Frequency-modulated signal demodulator comprising and a data selector for outputting a demodulated signal by. 2. An oscillator for oscillating and outputting a fundamental frequency signal, a frequency modulation signal and the fundamental frequency signal are input, and the two signals are alternately selected and output at a constant cycle, and at least a second data selector described later. During the period in which the fundamental frequency signal is output at, the first data selector that outputs the frequency modulation signal, the frequency modulation signal and the fundamental frequency signal are input, and the first data selector is deviated by about a half cycle Two signals are alternately selected and output, and at least during the period when the basic frequency signal is being output by the first data selector, a second data selector that outputs the frequency modulated signal; and a first data selector A first FM demodulator that demodulates the output frequency signal and outputs a voltage signal, and a frequency signal that demodulates the frequency signal output from the second data selector and outputs a voltage signal. A second FM demodulator, a first sample-hold circuit that samples and holds a portion of the voltage signal output from the first FM demodulator, the portion corresponding to the fundamental frequency signal, and outputs the voltage as a reference value, the second FM A second sample and hold circuit for sampling and holding a portion of the voltage signal output from the demodulator corresponding to the fundamental frequency signal, and outputting the voltage as a reference value; a voltage signal from the first FM demodulator and the first sample A first subtractor that inputs and subtracts a reference value from a hold circuit; a second subtractor that inputs and subtracts the voltage signal from the second FM demodulator and the reference value from the second sample and hold circuit; The signals output from the first subtractor and the second subtractor are input, and both signals are alternately selected so as to extract a portion corresponding to the frequency modulation signal included in both signals. Frequency-modulated signal demodulator comprising and a data selector for outputting a demodulated signal by.