JPH07288552A - Demodulator for frequency shift keying signal - Google Patents

Abstract

PURPOSE:To improve a bit error rate with simple circuit configuration by using a comparator of a variable threshold level system even when inter-code interference is in existence in the FSK signal demodulator. CONSTITUTION:A sample-and-hold circuit 13 samples and holds a detection signal from a primary PLL circuit 12 based on a final preceding bit time, the demodulator is provided with a coefficient device generating a constant value determined definitely by the cutoff frequency of the primary PLL circuit 12 and a data bit rate, and a value multiplying the constant value with the final value is used for a comparison reference value of a comparator 16 to improve a bit error rate of demodulated data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency shift keying signal (hereinafter referred to as FSK signal) demodulation device, and more particularly to a demodulation device which is strong against intersymbol interference.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional FSK signal demodulating device. An FSK signal to be demodulated which is input to an input terminal 1 is integrated through a bandpass filter 2 and a sampling signal. It is input to a well-known primary PLL circuit 6 including a phase comparator 3 having a negative action and a variable oscillator 5. Primary PL
The L circuit 6 detects the input FSK signal into the base band signal 4 whose amplitude changes according to the frequency.

This baseband signal 4 is applied to a comparator 7 and compared with a predetermined constant threshold value Th from a threshold value generating circuit 8. If it is larger than the threshold value Th, it is a high level signal. When it is smaller, the signal (hereinafter referred to as H signal) is configured to output a low level signal (hereinafter referred to as L signal) to the output terminal 9.

[0004]

However, in the conventional FSK signal demodulation device, the detection signal from the primary PLL circuit 6 is binary-coded by the comparator 7 by using a preset fixed threshold level. However, in order to improve the bit error rate of the demodulation data, 1
When the cutoff frequency of the next PLL circuit 6 is reduced, intersymbol interference increases, and the improvement amount is limited.

This state is schematically shown in FIG. Waveform a in FIG. 4 shows binary original data to be transmitted, and b is a baseband detection signal after frequency-discriminating by transmitting the original data by FSK modulation. That is, it shows the detection signal 4 of the primary PLL circuit 6 of FIG. 3, and shows a state in which ideal transmission is performed without intersymbol interference. In this case, the primary PLL circuit 6 always corresponds to the binary original signal.
The maximum value and the minimum value of the detection signal from are fixed to a constant value ± V, and the threshold value Th may be fixed and set to an intermediate value of the amplitude of the detection signal output 4 from the primary PLL circuit 6.

Reference numeral c indicates the detection signal 4 of the first-order PLL circuit 6 when there is intersymbol interference. The maximum and minimum values of the detection output do not become constant values, and n >> 1 due to intersymbol interference. , The amplitude changes greatly. That is, if the threshold value Th is fixed, a good bit error rate cannot be obtained.

The present invention solves the above-mentioned problems of the prior art. Even if there is intersymbol interference, the demodulation data of the FSK modulated signal is obtained.
It is an object of the present invention to provide an FSK signal demodulating device capable of improving the bit error rate of the data.

[0008]

To achieve the above object, the FSK signal demodulating device of the present invention detects the FSK signal by the frequency discriminating means and continuously detects the comparator signal in accordance with the detected signal output level. It is characterized in that the threshold level is varied to obtain a demodulated signal of the FSK modulated signal with a good bit error rate even in the presence of intersymbol interference.

[0009]

According to this structure, when the band of the frequency discriminating means is narrowed, intersymbol interference increases. However, the detection signal from the frequency discriminating means is sampled and held at the timing synchronized with the bit CK, Since the hold value is multiplied by a constant value uniquely determined by the cutoff frequency of the primary PLL circuit and the data bit time, the threshold value of the comparator is continuously varied. Even if the amplitude of the detection output changes due to intersymbol interference, the threshold changes following the change, so that the bit error rate can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the FSK signal demodulating device of the present invention will be described below with reference to the drawings. FIG. 1 shows the FSK of the present invention.
It is a block diagram which shows one Example of the demodulation device of a signal. In FIG. 1, the FSK modulated signal input to the input terminal 10 is band-limited by the BPF 11 and input to the primary PLL circuit 12 having the same configuration as the conventional example. The FSK modulated signal is frequency discriminated by the primary PLL circuit 12 and output to the signal line 4 as a base band detection signal. The detection signal on the signal line 4 is input to the comparator 16 and also to the sample and hold circuit 13. The sample / hold circuit 13 measures the final value of the bit time of the previous data with the CK signal synchronized with the transmission bit CK signal from the CK generation circuit 14 to sample-hold, and -Output the field value to the coefficient unit 15. A coefficient value that is uniquely determined by the cutoff frequency of the primary PLL circuit 12 and the data bit time is set by the coefficient multiplier 15, and the coefficient value is set to the sample hold value which is the final value of the bit time. The result is multiplied and output to the comparator 16 as a threshold Th to be used as the reference level of the comparator 16. COMPARE
The detector 16 compares the detected signal 4 with a threshold Th set for each bit time. If the detected signal 4 is larger than the threshold Th, the H signal is output. If the detected signal 4 is smaller than the threshold Th, the L signal is output. Output as data.

FIG. 2 is a diagram showing a variable threshold setting method according to the present invention when there is intersymbol interference. In FIG. 2, φ
(T) is the phase difference of the primary PLL circuit, Δω is the frequency deviation from the center frequency of the carrier wave, ωd is the cutoff frequency of the primary PLL circuit, and Tb is the bit time of the data. Since the initial value φ (0) of the phase difference φ (t) has intersymbol interference, it changes between the steady value + Δω / ωd and −Δω / ωd. When the data following this initial value φ (0) is 1, the primary PL
The output of the L circuit becomes the x point (φ1 (Tb)) and the y point (φ0 (Tb)) when the data is 0. The z point, which is the midpoint between the x point and the y point, can be set as the threshold value. For example, the distance from the threshold is the largest.

That is, this threshold Th is given by Th = {(φ1 (Tb)) + (φ0 (Tb))} / 2 = φ (0) × exp (−ωd · Tb), and the threshold Th is a first order It becomes proportional to a constant coefficient value determined by the cutoff frequency ωd of the PLL circuit and the data bit time Tb. Therefore, the primary PLL circuit 12
The coefficient value uniquely determined by the cut-off frequency and the data bit time of the above is set in the coefficient unit 15, and the coefficient value is multiplied by the sample hold value which is the final value of the bit time to obtain the threshold value. Th is output to the comparator 16 as the reference level of the comparator 16. By making the threshold variable in this way, the bit error rate can be improved even when there is intersymbol interference.

In the waveform c of FIG. 4, assuming that the point 2a is the sample value of the current time slot, the point 1a is the sample hold value of the final value of the previous bit time, and the point 1a is the initial value φ (0), When the data is 1, the point is 2b, and when the data is 0, the point is 2a. The point 2z is the midpoint between the points 2b and 2a.
Is used as a threshold value, and thereafter, the threshold values of 3z to 9z are similarly determined.
By making the threshold variable continuously in this way, the distance from the threshold can be made larger and the bit error rate can be improved compared to the case where the threshold is fixed at Th.

[0014]

As described above, according to the present invention, in the FSK signal demodulation device, by using the comparator having the variable threshold value even when there is intersymbol interference, the bit error can be improved as compared with the conventional fixed threshold value method. The rate can be improved. ,

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an FSK signal demodulation device of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operating principle of the embodiment.

FIG. 3 is a block diagram showing a conventional FSK signal demodulation device.

FIG. 4 is a conventional FSK signal demodulation device and F of the present invention.
Signal waveform diagram for explaining the operation of the demodulator of the SK signal

[Explanation of symbols]

 12 1st-order PLL 13 Sample-and-hold circuit 14 CK generation circuit 15 Coefficient multiplier 16 Comparator

Claims (1)

[Claims] 1. A frequency shift keying signal, in which a binary data signal having a predetermined bit interval is frequency shift keyed, whose amplitude is changed by frequency discriminating means. Of the frequency shift keying signal which is converted into a detection signal, is compared with a predetermined threshold value, and is converted into an original binary data signal according to the magnitude relation with the threshold value. In the demodulator, the detected signal,
A frequency shift keying signal demodulation device, wherein sample hold is sequentially performed at the bit intervals, and the threshold value is sequentially changed according to the sample hold value.