JPH07221451A - Manufacture of multilayer wiring board with viahole - Google Patents

Manufacture of multilayer wiring board with viahole

Info

Publication number
JPH07221451A
JPH07221451A JP1017894A JP1017894A JPH07221451A JP H07221451 A JPH07221451 A JP H07221451A JP 1017894 A JP1017894 A JP 1017894A JP 1017894 A JP1017894 A JP 1017894A JP H07221451 A JPH07221451 A JP H07221451A
Authority
JP
Japan
Prior art keywords
wiring board
sheet
viahole
polyethylene sheet
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1017894A
Other languages
Japanese (ja)
Inventor
Yoshihiro Tamura
義広 田村
Kunio Kawaguchi
邦雄 川口
Kazuji Yamagishi
一次 山岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP1017894A priority Critical patent/JPH07221451A/en
Publication of JPH07221451A publication Critical patent/JPH07221451A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To enable manufacture of a multilayer wiring board with a viahole of high surface smoothness and little surface resin remainder by using a polyethylene sheet for making a pressure applied to a wiring board uniform during lamination bonding. CONSTITUTION:A desired circuit pattern is formed by boring an inner layer board 1 and by applying plating. Then, a bonding sheet 2 is held between a plurality of inner boards 1 wherein a circuit is formed. In the process, a mold release sheet 3, a polyethylene sheet 4 and a mold release sheet 3 are arranged one by one in an outside. They are held by a mirror plate, and are heated and pressurized for lamination bonding. In the process, the polyethylene sheet 4 melts. Therefore, a wiring board surface formed by the molten polyethylene sheet 4 is uniformly pressurized. It is thereby possible to stop resin from effusing to a viahole uniformly, to improve surface smoothness and to reduce surface resin remainder.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子計算機、無線機器、
電送機器等に用いられる多層配線板の製造方法に関する
ものである。
BACKGROUND OF THE INVENTION The present invention relates to an electronic computer, a wireless device,
The present invention relates to a method for manufacturing a multilayer wiring board used for electric transmission equipment and the like.

【0002】[0002]

【従来の技術】一般に、部品を挿入しないで電気的層間
接続の役割を果たすバイアホール付き多層配線板は、あ
らかじめ所望の位置に穴あけを行った内層板をめっき
し、回路形成を行い、接着シートを介して前記内層板を
複数重ね合わせ加熱、加圧し、積層接着して形成され
る。
2. Description of the Related Art Generally, a multilayer wiring board with via holes which plays a role of electrical interlayer connection without inserting parts is plated with an inner layer board which is pre-drilled at a desired position to form a circuit, and an adhesive sheet. It is formed by stacking a plurality of the above-mentioned inner layer plates through the above, heating, pressurizing, and laminating and adhering.

【0003】この積層接着を行う際、接着シートからし
みだした樹脂が先に穴あけた穴からしみだしてくる。こ
の樹脂のしみだしを防止することが品質上、また製造歩
留り上特に重要である。この樹脂のしみだしを防止する
ために重ね合わせする際、配線板の外側に離型シートを
配し加熱、加圧する方法が広く用いられている。
When carrying out this laminated adhesion, the resin exuding from the adhesive sheet exudes from the previously drilled holes. It is particularly important in terms of quality and production yield to prevent the resin from seeping out. A method of placing a release sheet on the outer side of a wiring board and heating and pressurizing the resin is widely used when superposed to prevent the resin from oozing out.

【0004】[0004]

【発明が解決しようとする課題】広く用いられている方
法では、穴からしみだした樹脂が離型シートを変形させ
る。そのため成形された配線板表面がでこぼこになり著
しく表面平滑性を低下させる。また、しみだした樹脂が
表面に付着し外層回路形成を著しく阻害するという重大
な課題を有している。本発明は、表面平滑性が高く、表
面樹脂残りの少ないバイアホール付き多層配線板の製造
方法を供給するものである。
In a widely used method, the resin exuding through the holes deforms the release sheet. Therefore, the surface of the molded wiring board becomes uneven and remarkably deteriorates the surface smoothness. Further, there is a serious problem that the exuded resin adheres to the surface and remarkably hinders the outer layer circuit formation. The present invention provides a method for manufacturing a multilayer wiring board with via holes, which has high surface smoothness and less surface resin residue.

【0005】[0005]

【課題を解決するための手段】従来工法で積層接着する
際、バイアホールへの接着シートの樹脂しみだしが大き
い原因を検討したところ、バイアホール部で離型シート
が変形し、樹脂しみだしが大きくなり、成形した配線板
の表面が平滑にならないことがわかった。さらにこの離
型シートが変形する原因を究明したところ、接着シート
からしみだした樹脂が離型シートを押し出すことが原因
であることをつきとめた。さらにこれにより、配線板表
面に加わる圧力の不均一化がおきていることがわかっ
た。したがって、樹脂しみだしを低減し表面平滑性を高
めるには、加わる圧力を均一にし、離型シートの変形を
低減することが重要であることがわかった。本発明はこ
の積層接着する際、配線板に加わる圧力を均一にするた
め、ポリエチレンシートを使用することを特徴とする。
[Means for Solving the Problems] When laminating and adhering by the conventional method, the cause of the resin exudation of the adhesive sheet to the via hole was considered to be large. It was found that the size became large and the surface of the molded wiring board was not smooth. Further, when the cause of the deformation of the release sheet was investigated, it was found that the resin exuding from the adhesive sheet extruded the release sheet. Furthermore, it was found that the pressure applied to the surface of the wiring board was non-uniform. Therefore, it was found that it is important to make the applied pressure uniform and reduce the deformation of the release sheet in order to reduce the resin oozing and enhance the surface smoothness. The present invention is characterized in that a polyethylene sheet is used in order to make the pressure applied to the wiring board uniform during the lamination and adhesion.

【0006】本発明を図2を用いて説明する。図2
(a)に示す様に内層板を準備する。次に図2(b)に
示す様に内層板に穴あけを行う。次に、図2(c)に示
す様、めっきを行う。さらに、図2(d)に示す様、内
層板に、所望の回路パターンを形成する。
The present invention will be described with reference to FIG. Figure 2
An inner layer plate is prepared as shown in (a). Next, as shown in FIG. 2B, the inner layer plate is perforated. Next, as shown in FIG. 2C, plating is performed. Further, as shown in FIG. 2D, a desired circuit pattern is formed on the inner layer plate.

【0007】次に、図2(e)に示す様に接着シートを
回路形成した複数枚の内層板で挟み込む。この時さら
に、外側に離型シート、ポリエチレンシート、離型シー
トを順に配する。これを鏡板で挟み加熱、加圧すること
で積層接着する。加熱、加圧する手段、条件は従来と同
じ方法が使用できる。これによりバイアホール付き多層
配線板を製造することができる。
Next, as shown in FIG. 2 (e), the adhesive sheet is sandwiched between a plurality of circuit-formed inner layer plates. At this time, further, a release sheet, a polyethylene sheet, and a release sheet are sequentially arranged on the outside. This is sandwiched between end plates and heated and pressed to laminate and adhere. The heating and pressurizing means and conditions can be the same as in the conventional method. As a result, a multilayer wiring board with via holes can be manufactured.

【0008】[0008]

【作用】本発明によって、加熱、加圧し、積層接着する
際、ポリエチレンシートが溶融する。そのため、この溶
融したポリエチレンシートによって成形される配線板表
面を均一に加圧する。したがってバイアホールへのしみ
だそうとする樹脂を均一に押さえ込み、表面平滑性を高
め、表面樹脂残りを少なくすることができる。
According to the present invention, the polyethylene sheet is melted when heating, pressurizing and laminating and adhering. Therefore, the surface of the wiring board formed by the melted polyethylene sheet is uniformly pressed. Therefore, it is possible to uniformly press the resin that is about to seep into the via hole, improve the surface smoothness, and reduce the surface resin residue.

【0009】[0009]

【実施例】厚さ0.2mmりのガラス布エポキシ樹脂銅
張り積層板MCL−E−67(日立化成工業株式会社
製、商品名)にドリル穴あけを行った。この穴あけした
内層板にめっきを行い、さらに回路形成を行った。さら
に、回路形成を行った別の内層板との間に接着シートで
ある0.1mmのガラス布エポキシ樹脂プリプレグGE
−67N(日立化成工業株式会社製、商品名)を挟み込
んだ。次にこの内層板の両外側に離型シートである厚さ
28μmテドラシート100SM30SR(ソマール株
式会社製、商品名)、厚さ40μmポリエチレンシート
(東信化学株式会社製、商品名)、28μmテドラシー
トを順次に配した。これを成形温度170℃、形成圧力
3.9MPaで90分熱圧着し、板厚0.5mmの4層
バイアホール付き配線板を得た。本発明による実施例で
の表面平滑性を従来の方法と比較して表1に示す。
EXAMPLE A glass cloth epoxy resin copper-clad laminate MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 0.2 mm was drilled. The perforated inner layer plate was plated to further form a circuit. Furthermore, a 0.1 mm glass cloth epoxy resin prepreg GE which is an adhesive sheet between the inner layer plate and another inner layer plate on which a circuit is formed.
-67N (trade name, manufactured by Hitachi Chemical Co., Ltd.) was inserted. Next, a release sheet having a thickness of 28 μm Tedra sheet 100SM30SR (manufactured by Somal Co., Ltd., trade name), a thickness of 40 μm polyethylene sheet (produced by Toshin Chemical Co., Ltd., trade name), and a 28 μm tedra sheet are sequentially provided on both outer sides of the inner layer plate. I arranged it. This was thermocompression bonded for 90 minutes at a molding temperature of 170 ° C. and a forming pressure of 3.9 MPa to obtain a wiring board with a 4-layer via hole having a board thickness of 0.5 mm. The surface smoothness of the examples according to the present invention is shown in Table 1 in comparison with the conventional method.

【0010】[0010]

【表1】 [Table 1]

【0011】[0011]

【発明の効果】本発明の方法を用いると表面の平滑性が
高い結果が得られた。
When the method of the present invention is used, high smoothness of the surface is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(e)は、本発明の製造過程を示す断
面図である。
1A to 1E are cross-sectional views showing a manufacturing process of the present invention.

【図2】(a)〜(e)は、従来例の製造工程を示す断
面図である。
2A to 2E are cross-sectional views showing a manufacturing process of a conventional example.

【符号の説明】[Explanation of symbols]

1 内層板 2 接着シート 3 離型シート 4 ポリエチレンシート 1 Inner layer board 2 Adhesive sheet 3 Release sheet 4 Polyethylene sheet

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】あらかじめスルーホール穴あけを行い、め
っき、回路形成を行った複数枚の内層板を接着シートを
介して重ね合わせ積層接着することからなるバイアホー
ル付き多層配線板の製造方法において、前記内層板を重
ね合わせする際、ポリエチレンシートを使用することを
特徴とするバイアホール付き多層配線板の製造方法。
1. A method for manufacturing a multilayer wiring board with a via hole, which comprises laminating a plurality of inner layer boards, which have been through-hole drilled in advance, plated, and formed a circuit, via an adhesive sheet, and laminated and bonded. A method for manufacturing a multilayer wiring board with a via hole, which comprises using a polyethylene sheet when stacking inner layer boards.
JP1017894A 1994-02-01 1994-02-01 Manufacture of multilayer wiring board with viahole Pending JPH07221451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1017894A JPH07221451A (en) 1994-02-01 1994-02-01 Manufacture of multilayer wiring board with viahole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1017894A JPH07221451A (en) 1994-02-01 1994-02-01 Manufacture of multilayer wiring board with viahole

Publications (1)

Publication Number Publication Date
JPH07221451A true JPH07221451A (en) 1995-08-18

Family

ID=11743039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1017894A Pending JPH07221451A (en) 1994-02-01 1994-02-01 Manufacture of multilayer wiring board with viahole

Country Status (1)

Country Link
JP (1) JPH07221451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100904630B1 (en) * 2006-11-21 2009-06-25 조현귀 Circuit board punched pattern and manufacturing method thereof
US7914898B2 (en) * 2003-12-09 2011-03-29 Kabushiki Kaisha Kobe Seiko Sho Resin-coated metal plate for use in perforating printed-wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7914898B2 (en) * 2003-12-09 2011-03-29 Kabushiki Kaisha Kobe Seiko Sho Resin-coated metal plate for use in perforating printed-wiring board
KR100904630B1 (en) * 2006-11-21 2009-06-25 조현귀 Circuit board punched pattern and manufacturing method thereof

Similar Documents

Publication Publication Date Title
KR101116079B1 (en) Method for manufacturing multilayer printed circuit board and multilayer printed circuit board
KR100737057B1 (en) Method of manufacturing circuit board
CN102548255B (en) Manufacturing method for multilayer printed wiring board
JP2006253328A (en) Manufacturing method of multilayer wiring board
JPH07221451A (en) Manufacture of multilayer wiring board with viahole
JP3705370B2 (en) Manufacturing method of multilayer printed wiring board
JPH11233946A (en) Substrate for forming high-density wiring, its manufacture, and manufacture of high-density wiring board
JP2012243829A (en) Multilayered printed wiring board and method of manufacturing the same
JP3583241B2 (en) Manufacturing method of metal foil clad laminate and manufacturing method of printed wiring board
JP2762604B2 (en) Method of laminating multilayer printed wiring board
JPH05167250A (en) Method of manufacturing multilayer printed wiring board
JP3058045B2 (en) Manufacturing method of multilayer printed wiring board
JP3594765B2 (en) Manufacturing method of multilayer printed wiring board
JP3855670B2 (en) Multilayer circuit board manufacturing method
JPH0923063A (en) Manufacture of multilayered wiring circuit board
JPH03112656A (en) Manufacture of one side copper-spread laminated board and manufacture of one side printed-wiring board employing laminated board thereof
JPH10313177A (en) Manufacture of multilayered printed wiring board
JP3840953B2 (en) Circuit board and manufacturing method thereof
JP2864276B2 (en) Manufacturing method of printed wiring board
JPS63285997A (en) Method and device for manufacturing multi-layer substrate
JPH0832235A (en) Production of multilayer printed wiring board
JP3251712B2 (en) Method for producing multilayer copper-clad laminate
JP2004066702A (en) Method for sticking copper foil on resin film and method for manufacturing printed wiring board
JP2000031648A (en) Manufacture of multilayer printed wiring board
JP2000196236A (en) Double-sided flash printed wiring board and manufacture thereof