JPH07219514A - Image display controller - Google Patents

Abstract

PURPOSE:To effectively perform the expansion of character pattern data into an image storage means, to enable performing the display of an image at high speed and also to enable reducing the load on a software processing with this expansion. CONSTITUTION:At the time of expanding KANJI (Chinese character) patterns stored in a KANJI ROM 2 into a VRAM 3, an MPU 1 simply performs increments of KANJI addresses to be given to the KANJI ROM 2 and VRAM addresses to be given to the VRAM 3. At this time, a VRAM address is transformed into a VRAM address corresponding to a storage area in which dot data outputted from the KANJI ROM 2 in accordance with a KANJI address being outputted by the MPU 1 in an address transforming circuit 6 and supplied to the VRAM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a digital PB.
The present invention relates to an image display control device which is applied to X and causes an image such as a message to be displayed on a display device such as an LCD.

[0002]

2. Description of the Related Art In a digital PBX, a display device such as an LCD may be provided to display various messages to the user. FIG. 9 is a functional block diagram showing a conventional configuration example of an image display control device for displaying such a message. In this image display control device, under the control of the MPU 1, any one of a large number of kanji patterns registered in the kanji ROM 2 can be video RA.
By expanding to any position of M (VRAM) 3,
Image data showing a message is created on the VRAM 3. Then, the LCD controller 4 drives the LCD 5 based on the image data stored in the VRAM 3, so that an image showing a message is displayed on the screen of the LCD 5.

By the way, the Kanji ROM 2 generally stores bit image information (for example, 16 × 16 dot structure / 32 bytes) of each Kanji pattern at an address as shown in FIG. And, normally, the addresses A0 to A5 of the MPU 1 are
But the addresses A0-A3, A15, A1 of the Kanji ROM2
Each is given as 6. Ie Kanji ROM
In 2, when the MPU 1 simply increments the address, reading is performed in the row increasing direction.

On the other hand, as the VRAM 4, for example, an SRAM having a storage area of 64 bytes × 256 as shown in FIG. 11 is used. Then, of the 64 bytes × 256 storage area, a 40 bytes × 240 storage area corresponding to the number of pixels of the LCD 5 (for example, 320 × 240) is used to display the LCD.
One dot of 5 stores one bit of data. The address of this VRAM4 is MPU1
When it is arranged in the address space of, it is arranged in the column increasing direction.

As described above, the Kanji ROM 2 and the VRAM 3 are different from each other in the address arrangement direction. Therefore, the MPU 1 uses a certain kanji pattern for each line 1 of the VRAM 3.
When expanding to a column, first, upper addresses A _{n to} A ₅ for identifying the type of Kanji are obtained, and then lower addresses A _{4 to} A for designating each bit of the Kanji pattern.
While incrementing the range of ₀ to _{"00 H" ~ "1F H} ", writing to VRAM3 following correspondence.

Kanji pattern address “00 _H ” → VRAM address “000 _H ” Kanji pattern address “01 _H ” → VRAM address “040 _H ” Kanji pattern address “02 _H ” → VRAM address “080 _H ” :: Kanji pattern address “0F _H ” → VRAM address “3C0 _H ” Kanji pattern address “10 _H ” → VRAM address “001 _H ”: Kanji pattern address “1F _H ” → VRAM address “3C1 _H ” Therefore, MPU1 has one Kanji pattern (1) Register BC ← Kanji ROM pattern left side start address [LD BC, nn] (2) HL register ← VRAM address [LD HL, 4000
_H ] (3) DE register ← Increase address 40 _H [LD DE, 40 _H ] (4) ・ A register ← Kanji ROM address indicated by BC register [LD A, (BC)] ・ VRAM area indicated by HL register ← A Kanji pattern data at the address indicated by the register [LD (HL), a] · Kanji ROM updating the address (+1) [INC BC] · VRAM address set to the next address _{(4040 H) [ADD HL,} DE] · ( Return to the beginning of 4) and repeat this 16 times (writing the left side of the kanji pattern) (5) ・ HL register ← VRAM address [LD HL, 4001
_H ] ・ It is necessary to perform the processing in the sequence of repeating the same sequence as (4) 16 times (writing the right side of the Chinese character pattern). That is, a total of 32 times of address calculation and transfer processing must be performed. For this reason, a lot of time is required for the expansion processing, the screen display speed is reduced, and a heavy load is imposed on the software processing.

[0007]

As described above, in the conventional image display control device, since the address calculation and the transfer process must be performed many times in order to display one character, the screen display speed decreases. At the same time, there is a problem that it imposes a heavy burden on software processing.

The present invention has been made in consideration of such circumstances, and an object of the present invention is to efficiently develop character pattern data in an image storage means, which enables high speed operation. An object of the present invention is to provide an image display control device capable of displaying an image and reducing the load on software processing.

[0009]

In order to achieve the above object, the present invention provides a first address (kanji address) designated by pre-storing character pattern data such as a kanji pattern formed of an array of a large number of dot data. Character data storage means for outputting dot data corresponding to, for example, a kanji ROM, and a large number of storage areas for storing a large number of dot data constituting image data, and designated dot data to be given. An image storage means such as a video RAM which is stored in a storage area corresponding to two addresses (VRAM address), and a character stored in the character storage means while changing the first address and the second address in a predetermined order. For sequentially transferring dot data of data to the image storage means, such as MPU The transfer control means and the second address generated by the transfer control means are stored in a storage area for storing the dot data output from the character storage means in accordance with the first address generated by the transfer control means. It is provided with an address conversion unit such as an address conversion circuit composed of, for example, four selectors for converting the corresponding third address (VRAM address) and giving it to the image storage unit.

[0010]

By taking such means, the transfer control means changes the first address and the second address in a predetermined order in order to transfer the character data stored in the character storage means to the image storage means. The address conversion means converts the second address into a third address corresponding to a storage area in which the dot data output from the character storage means is to be stored according to the first address and is supplied to the image storage means.

Therefore, in the transfer control means, the character data stored in the character storage means is transferred to the image storage means by simply incrementing the first address and the second address, and in a desired state. It is expanded in the image storage means.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing the configuration of an image display device configured by applying the image display control device according to the present embodiment. The same parts as those in FIG. 9 are designated by the same reference numerals, and detailed description thereof will be omitted.

This image display device includes an MPU 1 and a Chinese character RO.
It is composed of an M2, a video RAM (VRAM) 3, an LCD controller 4, an LCD 5 and an address conversion circuit 6.

2 to 5 are circuit diagrams showing a concrete structure, FIG. 2 is a circuit diagram showing the whole structure, and FIG. 3 is an enlarged view showing a portion of the Kanji ROM 2 in FIG. 4 is an enlarged view of the VRAM 3 and LCD controller 4 in FIG. 2, and FIG. 5 is an enlarged view of the LCD controller 4 and address conversion circuit 6 in FIG.

As shown in these figures, a ready-made Z80 (trade name: Zylog Co.) is applied to the MPU 1.
The kanji ROM2, VRAM3, and LCD controller 4 are provided with ready-made integrated circuits (IC10, IC2, respectively).
7, IC26) is applied. And MPU1
The Chinese character ROM 2, VRAM 3, program ROM (not shown) and data stuff RAM (not shown) are managed by addresses as shown in FIG.

As shown in FIGS. 2 and 5, the address conversion circuit 6 includes four ready-made integrated circuits (IC22, IC23, IC24, IC2) which respectively function as selectors.
5) is the main constituent. And MPU1 is V
Bits A0 to A15 of the VRAM address (16-bit parallel) output to the RAM 3 are input to the ICs 22 to 25 as follows.

Bit A0: Input terminal 1A of IC25 and input terminal 3B of IC24 Bit A1: Input terminal 2A and IC24 of IC25
Input terminal 4B of A25: input terminal 3A of IC25 and IC23
Input terminal 1B of A3: Input terminal 4A of IC25 and IC23
Input terminal 2B of A24: Input terminal 1A of IC24 and IC23
Input terminal 3B of IC A2: Input terminal 2A of IC24 and IC23
Input terminal 4B of IC 24: Bit A6: Input terminal 3A of IC24 and IC22
Input terminal 1B of A24: Input terminal 4A of IC24 and IC22
Input terminal 2B of A23: input terminal 1A of IC23 and IC25
Input terminal 1B of IC A2: Input terminal 2A of IC23 and IC25
Input terminal 2B of A23: input terminal 3A of IC23 and IC25
Input terminal 3B of bit A11: Input terminal 4A of IC23 and IC25
Input terminal 4B of bit A12: Input terminal 1A of IC22 and IC24
Input terminal 1B of IC A2: Input terminal 2A of IC22 and IC24
Input terminal 2B of A22: input terminal 3A of IC22 and IC22
Input terminal 3B of A22: Input terminal 4A of IC22 and IC22
The input terminal 4B of the IC 22 to the select signal input terminal S of each of the ICs 22 to 25 is a signal obtained by inverting the logic of the signal LCDADCHG output from the register arranged on the I / O address of the MPU 1 by the NOR gate 36a in the IC 36. NO in IC36 that takes the NOR of the signal output from / MPU1 and MRQ
The output of the R gate 36b is given.

The output terminals of each of the ICs 22 to 25 have the following correspondence relationship with the LCD controller 4
It is connected to the input terminal of (IC26). Output terminal 1Y of IC25: Input terminal AB0 of IC26 Output terminal 2Y of IC25: Input terminal AB1 of IC26 Output terminal 3Y of IC25 3Y: Input terminal AB2 of IC26 Output terminal 4Y of IC25 4Y: Input terminal AB3 of IC26 Output terminal 1Y of IC24: Input terminal AB4 of IC26 Output terminal 2Y of IC24: Input terminal AB5 of IC26 Output terminal 3Y of IC24 3Y: Input terminal AB6 of IC26 Output terminal 4Y of IC24 4Y: Input terminal AB7 of IC26 Output terminal 1Y of IC23: Input terminal AB8 of IC26 IC23 Output terminal 2Y: input terminal AB9 of IC26 output terminal 3Y of IC23: input terminal AB10 of IC26 output terminal 4Y of IC23 4Y: input terminal AB11 of IC26 output terminal 1Y of IC22: input terminal AB12 of IC26 output terminal 2Y of IC22: IC 26 input terminal AB13 output terminal 3Y of IC22: input terminal AB14 of IC26 output terminal 4Y of IC22: input terminal AB15 of IC26 Next, the operation of the image display device configured as described above will be described.

First, the address conversion processing in the address conversion circuit 6 will be described. The output signal of the NOR gate 36b is commonly input to the select signal input terminal S of each of the ICs 22 to 25. Therefore, IC22-2
Reference numeral 5 denotes input terminals 1A to 4A on the A side (NOR gate 36b
Output signal of "L" level) or B side input terminals 1B to 4B (the output signal of NOR gate 36b is "H")
Level) is selected at the same time.

Now, when each of the ICs 22 to 25 selects the A side, the correspondence between the bits A0 to A15 of the VRAM address output by the MPU 1 and the input terminals 1A to 4A on the A side of each of the ICs 22 to 25. And IC22-25
The output terminals 1Y to 4Y and the input terminals AB0 to AB15 of the LCD controller 4 (IC26) correspond to each other as described above. Therefore, the LCD controller 4 (IC26) has the VRAM address output by the MPU1. It is given as it is through the address conversion circuit 6.
That is, at this time, the address conversion circuit 6 operates in the VRAM.
Does not translate the address.

On the other hand, when each of the ICs 22 to 25 selects the B side, the correspondence between the bits A0 to A15 of the VRAM address output by the MPU 1 and the B side input terminals 1B to 4B of the ICs 22 to 25, respectively. And IC22-25
Since the correspondence between the output terminals 1Y to 4Y of each of the above and the input terminals AB0 to AB15 of the LCD controller 4 (IC26) is as described above, the LCD controller 4 (IC26) has the address conversion shown in FIG. The VRAM address after being converted according to the rule is given from the address conversion circuit 6. That is, at this time, the address conversion circuit 6 converts the VRAM address.

FIG. 8 is a diagram showing a correspondence relationship between an input address (VRAM address output by the MPU 1) and an output address (VRAM address given to the LCD controller 4 (IC 26)) when performing address conversion. In this figure, the area surrounded by a thick line is an area for storing image data. Each cell is 1 byte (8 bits)
Minute, that is, data for 8 pixels (1 bit is 1 for black / white)
(Indicates a pixel). The numbers shown in the squares represent VRAM addresses, the left side of the slanted line represents the input address, and the upper side of the slanted line represents the output address when the address conversion is executed. The output address when the address conversion is not performed is the same as the input address, and therefore is shown on the left side of the diagonal line.

Next, the operation of expanding the Kanji pattern actually stored in the Kanji ROM 2 into the VRAM 3 will be described. In this case, the MPU1 first sets the signal LCDADCHG to "L".
Therefore, the output of the corresponding I / O register is set to "L". At this time, since the output of the NOR gate 36b is constantly "L", the inputs on the A side are selected in the ICs 22 to 25, and the VRAM address output by the MPU 1 to the LCD controller 4 and the VRAM 3 (see FIG. 8). The address on the left side of the diagonal line in each cell) is supplied.

From this state, when the MPU 1 sets the output of the corresponding I / O register to "H" in order to set the signal LCDADCHG to "H", one input of the NOR gate 36b becomes "L".
Therefore, the output of the NOR gate 36b changes from "L" to "H" every time the MPU 1 accesses the memory. Therefore, at the time of memory access, the inputs on the B side are selected in the ICs 22 to 25, and the VRAM address output from the MPU 1 to the LCD controller 4 and the VRAM 3 is converted to the VRAM address (according to the address conversion rule shown in FIG. 7). Addresses on the upper side of the diagonal line in each square in FIG. 8 are supplied.

Thus, as the MPU 1 increments the VRAM address to be output, the area to be accessed in the VRAM 3 changes in the column changing direction within the thick line in FIG. On the other hand, in the Kanji ROM 2, the Kanji address is incremented to read in the column changing direction, and this is supplied to the VRAM 3 via the LCD controller 4.

Therefore, if both the Kanji address and the VRAM address given to the Kanji ROM 2 and the VRAM 3 are incremented, the Kanji pattern is developed in the VRAM 3 in the same state as that stored in the Kanji ROM 2.

In this embodiment, the MPU 1 is Z80.
Is used. This Z80 has a block transfer instruction, but in the present embodiment, the Kanji ROM 2 is used as described above.
Since both the Kanji address and the VRAM address given to the VRAM 3 and the VRAM 3 need only be incremented, they can be processed in the following sequence using a block transfer instruction.

That is, when displaying a kanji pattern in one row and one column, for example, the kanji address of the desired kanji pattern is calculated in advance, and then the bank address (00 to 15) of the kanji ROM shown in FIG. 6 is set. Along with M
In the HL register, the DE register and the BC register of PU1, the HL register ← the start address on the left side of the kanji pattern DE register ← the start of the 1st row and 1st column of VRAM3 40
00 _H BC register ← 0 _{F H} indicating the number of transfers is set, and then the MPU 1 executes the LDIR instruction. Then, the MPU 1 automatically increments both the Kanji address for the Kanji ROM 2 and the VRAM address for the VRAM 3 and transfers the left 16 bytes of the Kanji pattern onto the VRAM 3. At this time, in the address conversion circuit 6, 40
Receive VRAM address incremented from 00 _H , 4000 _H , 4040 _H , 4080 _H ..., 7B
C0 _H , 4001 _H , 4041 _H , 4081 _H ..., 7B
C1 _H ..., 4027 _H , 4067 _H , 40A7 _H ..., 7
Since it is converted into a VRAM address BE7 _H and given to the LCD controller 4 and the VRAM 3, the kanji pattern is written in the VRAM 3 in the line changing direction.

Next, the HL register remains as it is: DE register ← 41 at the beginning of the first row and second column of VRAM3.
00 _H BC register ← later set respectively 0F _H indicating the number of transfers, to execute the LDIR instruction MPU 1. Then, the MPU 1 automatically performs the process of transferring the right 16 bytes of the Kanji pattern to the VRAM 3 in the same manner as above.

In the LCD controller 4, the LCD 5 is driven by a well-known procedure based on the image data created in the VRAM 3 as described above.
An image corresponding to the image data is displayed on D5.

As described above, according to this embodiment, the Chinese character RO
When the Kanji pattern stored in M2 is expanded in the VRAM3, the address conversion circuit 6 converts the incremented VRAM address into a VRAM address in which the writing area in the VRAM3 changes in the column changing direction, and then the VRAM3. Given to. As a result, the MPU 1 can expand the Kanji pattern stored in the Kanji ROM 2 into the VRAM 3 by incrementing both the Kanji address and the VRAM address. Therefore, the process related to the expansion of the Chinese character pattern is simplified, the time required for the process is shortened, and the image display can be performed at high speed. Moreover, since the block transfer instruction of the MPU 1 can be used, the software can be simplified.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the image display control device of the present invention is applied to an image display device having an LCD and displaying an arbitrary image on the LCD.
The present invention can be applied to an image display device having a display other than the LCD, or can be applied to a device other than the image display device. Furthermore, the image display control device may be an independent image display control device without being incorporated in another device.

Character storage means, image storage means,
The specific configurations of the transfer control means and the address conversion means are not limited to those described in the above embodiment, and various modifications are possible. In addition, various modifications can be made without departing from the scope of the present invention.

[0034]

According to the present invention, character pattern data such as a Chinese character pattern made up of an array of a large number of dot data is stored in advance and dot data corresponding to a designated first address (Kanji address) is output, for example. It corresponds to a second address (VRAM address) designated by character storage means such as a kanji ROM and a large number of storage areas for storing a large number of dot data constituting image data, and given dot data. An image storage unit such as a video RAM stored in a storage region, and dot data of character data stored in the character storage unit while changing the first address and the second address in a predetermined order. And a transfer control means such as an MPU for sequentially transferring the The second address but that is occurring,
In response to the first address generated by the transfer control means, the dot data output from the character storage means is converted into a third address (VRAM address) corresponding to the storage area to be stored and given to the image storage means. For example, since it is provided with an address conversion unit such as an address conversion circuit composed of four selectors, the character pattern data can be efficiently developed in the image storage unit, and thus an image can be displayed at high speed. Is possible,
In addition, the image display control device can reduce the load on software processing.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a configuration of an image display device configured by applying an image display control device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of an image display control device according to an embodiment of the present invention.

FIG. 3 is an enlarged view showing a portion of a Kanji ROM 2 in FIG.

FIG. 4 is an enlarged view showing portions of a VRAM 3 and an LCD controller 4 in FIG.

5 is an enlarged view showing a portion of an LCD controller 4 and an address conversion circuit 6 in FIG.

FIG. 6 is a diagram schematically showing a memory map viewed from MPU1 in FIG.

7 is a diagram showing an address conversion rule in the address conversion circuit 6 in FIG.

8 is a diagram showing a relationship between an input address and an output address of the address conversion circuit 6 when the address conversion circuit 6 in FIG. 1 performs an address conversion process.

FIG. 9 is a diagram illustrating a conventional technique.

FIG. 10 is a diagram illustrating a conventional technique.

FIG. 11 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 1 ... MPU 2 ... Kanji ROM 3 ... Video RAM (VRAM) 4 ... LCD controller 5 ... LCD 6 ... Address conversion circuit

Claims (1)

[Claims] 1. An image display control device for displaying an image corresponding to the image data on the display means by driving the display means based on image data composed of an array of a large number of dot data. A character storage unit for storing character pattern data having an array of the above and outputting dot data corresponding to a designated first address; and a large number for storing each of the plurality of dot data constituting the image data. Image storage means for storing given dot data in a storage area corresponding to a designated second address, and the character while changing the first address and the second address in a predetermined order. The dot data of the character data stored in the storage means is sequentially transferred to the image storage means. A transfer control means for controlling the second address generated by the transfer control means, and a memory for storing the dot data output from the character storage means in accordance with the first address generated by the transfer control means. An image display control device, comprising: an address conversion means for converting the third address corresponding to the area and giving it to the image storage means.