JPH08234714A - Memory circuit for display - Google Patents

Abstract

PURPOSE: To read or write data of several units of a prescribed dot number beginning from an arbitrary dot with one time of data access in a memory circuit for display which stores display data of a display device of electronic apparatus. CONSTITUTION: Respective 64 byte data corresponding to even columns divided by 8 dots each in an X direction among display data of 64×64 dots are stored in a memory (1)11a and respective 64 byte data corresponding to odd columns are stored in a memory (2) 11b. When a write start address A(11:0) for one byte-component is instructed from the arbitrary dot, the byte data of the even columns and the byte data of the odd columns across the write range thereof are read out of the memories (1)11a, (2)11b and are applied to input data forming circuits (1)13a, (2)13b and only the dot data parts corresponding to the respective write ranges are rewritten according to the byte data D for rewriting and are again written into the original address positions of the memory (1)11a, (2)11b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display memory circuit for storing display data in a display device of electronic equipment.

[0002]

2. Description of the Related Art Generally, a display memory for storing black and white display image data is a CPU as its upper device.
Since it is read / written by the (central processing unit), the display data stored in the display memory is addressed in byte units or word units.

FIG. 7 is a diagram showing memory addresses of a conventional display memory which stores display data of 64 dots × 64 dots. In this display memory, each 1-dot display data is specified by an address of 12 bits in which the X-direction address is the lower 6 bits and the Y-direction address is the upper 6 bits.
Since it is done in units of ts), the lower 3 bits are unnecessary,
Addressed in the upper 9 bits.

In the display memory in FIG. 7, the byte unit address is shown as an octal number. For example, in the address "000X", the bit address "0001" to
The 1-byte data at “0007” corresponds to the address “00
In 1X, bit addresses “0011” to “001”
1-byte data in 7 "is designated.

The address "X" represents unnecessary 3 bits. FIG. 8 is a diagram showing an array of display data designated in byte units. That is, in the display memory that performs address processing on a byte-by-byte basis, the read / write of display data that matches the range divided for each byte can access the read data or write data at once by addressing once. However, if the data to be rewritten or the data to be read exists between the two byte addresses, it is necessary to sequentially specify the respective byte addresses and perform the data access a plurality of times.

That is, for example, the lower 3 dot data of the 8 dot data designated by the address "000X" and the upper 5 dot data of the 8 dot data designated by the adjacent address "001X" are crossed. When rewriting, the first addressing "00
It is necessary to perform two writing processes, that is, writing new 8-dot data associated with 0X ”and writing new 8-dot data associated with the second addressing“ 001X ”.

[0007]

Therefore, in the conventional display memory control described above, it is possible to read / write byte or word data starting from an arbitrary dot which does not match the address range of each byte with one data access. There is a problem that cannot be done.

The present invention has been made in view of the above problems, and a display memory capable of reading or writing data in a predetermined number of dots starting from an arbitrary dot with one data access. The purpose is to provide a circuit.

[0009]

That is, the display memory circuit according to claim 1 of the present invention inputs the upper address of the write start address and successively continues in a predetermined bit number unit corresponding to the upper address. The first and second memories in which display data are written alternately and the continuous display data read from the first and second memories in units of a predetermined number of bits are respectively stored in the lower order of the write start address. And an input data generation circuit for rewriting according to external data at a bit position corresponding to an address value.

Further, in the display memory circuit according to the second aspect of the present invention, the upper address of the read start address is input, and the display data which is successively continuous is alternately written in a unit of a predetermined number of bits corresponding to the upper address. First and second
And the continuous display data read from the first and second memories in units of a predetermined number of bits respectively, and the data at the bit position corresponding to the value of the lower address of the read start address is input. And an output data generation circuit that outputs the data in combination.

[0011]

That is, in the display memory circuit according to the first aspect, the data is rewritten across the display data that are preceded and followed by a predetermined number of bits by one data access to the first and second memories. Can be done.

Further, in the display memory circuit according to the second aspect of the present invention, the data read across the display data which is preceded and succeeded by a predetermined number of bits by one data access to the first and second memories is read. Can be done.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a display memory circuit. This display memory circuit has, for example, 64 dots ×
It stores and manages 64-dot black and white display data, and data is accessed to an upper device through an 8-bit data bus. This display memory circuit is an SRAM.
It has two memories (1) 11a and (2) 11b.

FIG. 2 is a diagram showing the relationship between the memory address in the memory (1) 11a of the display memory circuit and the display data stored therein. FIG. 3 is a diagram showing a relationship between a memory address in the memory (2) 11b of the display memory circuit and display data stored therein.

The memory (1) 11a and the memory (2) 1
The display data of 64 dots × 64 dots is divided into two and stored in 1b.
In a, among the memory addresses in byte units for the display data of 64 dots × 64 dots shown in FIG. 7,
Even number of X-direction address (000X, 002X, 004
The display data corresponding to the column of (X, 006X) (octal) is stored.

Unless otherwise specified, addresses are expressed in octal notation below. In addition, in the memory (2) 11b,
Of the memory addresses in byte units for the display data of 64 dots × 64 dots shown in FIG.
The display data corresponding to the column X) is stored.

That is, for example, the display data corresponding to the logical address "000X" in FIG. 7 is stored in the physical address "00 ... 00" (binary) of the memory (1) 11a, and the same physical of the memory (2) 11b is stored. Address "00 ... 0
The logical address "001" in FIG.
The display data corresponding to X "is stored. Further, the display data corresponding to the logical address" 002X "in FIG. 7 is stored in the physical address" 00 ... 01 "(binary) of the memory (1) 11a, Display data corresponding to the logical address "003X" in FIG. 7 is stored in the same physical address "00 ... 01" (binary) of the memory (2) 11b.

The memory (1) 11a and the memory (2)
11b has an 8-bit address terminal A, an 8-bit input data terminal I, a write strobe terminal WR, an 8-bit even column output data terminal M, and an 8-bit odd column output data terminal m, respectively. ing.

As the 8-bit address, the address data in which the X direction address of 4 sections is shown by the lower 2 bits and the Y direction address of 64 sections is shown by the upper 6 bits is input.
That is, of the 12-bit address data A0 to A11, A4 and A5 are input as the X-direction address, and A6 to A6.
A11 is input as the Y direction address.

The address X (7: 0) generated by the address generating circuit 12 is applied to the address terminal A of the memory (1) 11a, and the address terminal A of the memory (2) 11b is supplied. Is directly given the upper 8-bit address A (11: 4) of the 12-bit address A (11: 0) given by the higher-level device.

The numbers in parentheses indicate the numbers of data lines or terminals, and A (11: 4) indicates the address bits A4 to A11. The address generation circuit 12 is arranged so that, of the 12-bit address A (11: 0) given by the higher-level device, the lower 8-bit address A (11: 4) of the lower 8-bit address A
(3) is added to generate the address X for the memory (1) 11a.

For example, a read command given when writing or reading data in the middle of a divided byte unit.
The write start address A (11: 0) corresponds to the address "001X" (octal number) in FIG. 7 and is "000.000.001.01" indicating the fourth dot of the byte data.
If it is 1 ”(binary), the address A (11: 4) of the higher 8 bits is“ 000000.00 ”and the address A (3) of the lower 4 bits is“ 1 ”. Therefore, the generated address "000000.01" is given to the address terminal A of the memory (1) 11a (see FIG. 2).

Therefore, from the memory (1) 11a, the logical address "0" in FIG.
The byte data corresponding to 02X ″ is output from the even column output data terminal M.

At this time, the higher-order 8-bit address A (11: 4) is applied to the address terminal A of the memory (2) 11b.
"000000.00" (binary) is given (see FIG. 3), and the byte data corresponding to the logical address "001X" in FIG. 7 is output from the odd column output data terminal m.

That is, the address "001" in FIG.
Read / write start address "000000..multidot.x" indicating the 4th dot of the byte data corresponding to X "(octal).
If "001.011" is instructed by the host device,
“001 in FIG. 7 including the read / write start address
X "byte data and the subsequent" 002X "in FIG.
Byte data are simultaneously output from the odd-numbered column output data terminal m of the memory (2) 11b and the even-numbered column output data terminal M of the memory (1) 11a as data relating to the read / write range.

Byte data M0 to M of even columns output from the even column output data terminal M of the memory (1) 11a.
7 is supplied to the input data generation circuit (1) 13a and the output data generation circuit 14.

Byte data m0 to m of the odd number column output from the odd number column output data terminal m of the memory (2) 11b.
7 is supplied to the input data generation circuit (2) 13b and the output data generation circuit 14.

The input data generation circuit (1) 13a includes byte data M0 to M7 of even columns related to the write range given from the memory (1) 11a and rewriting byte data D0 to D7 given from the host device. , The 12-bit write start address A given to it by the host device
The address A (3:
0), the byte data M related to the write range
Generating a rewritten Bytes data O _M of the even columns rewritten according rewritten subject to byte data D0~D7 for rewriting the individual dot data of 0～M7.

The rewritten byte data O _M of the even-numbered column is given to the memory (1) 11 a and written in the byte area addressed by the address generation circuit 12.

The input data generation circuit (2) 13b
Is the byte data m0 to m7 of the odd-numbered columns related to the write range given from the memory (2) 11b, the rewriting byte data D0 to D7 given from the upper device, and the 12-bit data given from the upper device. Address A of lower 3 bits of write start address A (11: 0)
(2: 0) and inverted address A (3) of the lower 4th bit
Based on the above, the individual dot data related to the write range is rewritten according to the rewriting byte data D0 to D7 to generate the rewritten byte data O _m of the odd-numbered column.

Rewritten byte data O _{m of} this odd-numbered column
Is given to the memory (2) 11b and written in the byte area addressed by the upper 8 bits A (11: 4) of the 12-bit read / write start address A (11: 0). .

FIG. 4 is a diagram showing a truth table of the input data generating circuits (1) 13a and (2) 13b in the display memory circuit. That is, each of the input data generation circuits (1) 13a and (2) 13b is composed of a combination circuit of logic elements according to the truth table, and the memory (1) 1
1a or (2) The byte data M0 to M7 or m0 to m7 of the even column or the odd column given from 11b and the rewriting byte data D0 to D7 given from the host device are written to the lower 4 bit address of the write start address. A (3: 0)
The rewritten byte data O of even-numbered columns or odd-numbered columns combined in accordance with the above is generated.

As a result, the byte data M and m in the even and odd columns related to the write range addressed by the write start address from the host device in the memory (1) 11a and the memory (2) 11b are input respectively. The rewritten byte data O _M and O _m generated by the data generation circuits (1) 13a and (2) 13b are rewritten.

On the other hand, the output data generating circuit 14 outputs the even-numbered column byte data M0 to M7 relating to the read range given from the memory (1) 11a, and the memory (2) 1.
Byte data m0 to m7 of an odd number column related to the read range given from 1b, and 12 given from the host device
Based on the address A (3: 0) of the lower 4 bits of the read start address A (11: 0) of the bit, the read byte data DO is generated by combining dot data of 1 byte after the read start address. .

FIG. 5 is a diagram showing a truth table of the output data generating circuit 14 in the display memory circuit. That is, the output data generation circuit 14 is composed of a combination circuit of logic elements according to the truth table, and the memory (1) 11
a and (2) For the byte data M0 to M7 and m0 to m7 of the even and odd columns given from 11b, one byte is extracted according to the lower 4 bit address A (3: 0) of the read start address. Read byte data DO is generated, whereby byte data of even columns and odd columns related to the read range addressed by the read start address from the host device in the memory (1) 11a and memory (2) 11b. The byte data DO corresponding to the read range is read from M and m.

Next, the operation of the display memory circuit having the above structure will be described. FIG. 6 is a diagram showing a data writing process and a data reading process in the display memory circuit.

First, for example, 64 dots × 6 shown in FIG.
Address "000X" in 4dots display data
Even-numbered column byte data (M0 to M) corresponding to (octal number)
The case where the rewriting byte data (D0 to D7) is written after the fourth dot (M3) in 7) will be described.

That is, the address "000" in FIG.
Byte data (M0 to M7) corresponding to X "(octal)
12-bit write start address A (11: 0) “0 indicating the writing in bytes from the fourth dot (M3) of
When "00,000,000,000,000011" is designated by the higher-level device, the upper 8-bit address A (11: 4) is "000000,000,000", and the lower-order fourth-bit address A (3). Is “0”, the memory (1) 11
A generated address "000000.00.00" by the address generation circuit 12 is given to the address terminal A of a (see FIG. 2).
6), the even-numbered column byte data (M0 to M7) corresponding to the address “000X” in FIG. 7 is output from the even-numbered column output data terminal M as shown in FIG. 1) is given to 13a.

Further, the address terminal A of the memory (2) 11b has the address A (11: 4) "000.0" of the upper 8 bits of the write start address A (11: 0).
00.00 ”is directly given (see FIG. 3), and the byte data (m0 to m7) of the odd number column corresponding to the address“ 001X ”in FIG. 7 is output to the odd number column output data as shown in FIG. 6B. The data is output from the terminal m and given to the input data generation circuit (2) 13b.

That is, the address "000" in FIG.
Byte data (M0) of even columns corresponding to X "(octal)
7 to M7) when the write start address "000000.000.0111" indicating the fourth dot (M3) is instructed by the higher-level device, the even number of "000X" in FIG. Column byte data (M0-M
7) and the odd-numbered column byte data (m0 to m7) of "001X" in FIG. 7 that follows, respectively, as data that the write range spans, as shown in FIGS. 6A and 6B. Input data generation circuits (1) 13a and (2) 13b are read simultaneously from the memories (1) 11a and (2) 11b.
Given to.

Then, the input data generation circuit (1) 13a
(See FIG. 4), the write start address A (11:
0) Five dots after the fourth dot of the even-numbered byte data (M0 to M7) according to the lower 4 bits A (3: 0) "0011" of "000000.000.011". The data (M3 to M7) is rewritten from the first dot of the rewriting byte data (D0 to D7) to the 5 dot data (D0 to D4) as shown in FIG. As shown, the rewritten byte data O _M (M0, M1, M2, D0, D1, D2) of an even-numbered column
D3, D4) are generated and written to the same address of the memory (1) 11a (see FIG. 2).

At the same time, in the input data generation circuit (2) 13b (see FIG. 4), the write start address A (11: 0) "000,000,000,000,000011".
Of the lower 3 bits A (2: 0) “011” and the inverted lower 4th bit “1” ““ 1011 ””
The 3-dot data (m0 to m2) from the first dot of the odd-numbered column byte data (m0 to m7) is shown in FIG.
The rewritten byte data of the odd-numbered column as shown in FIG. 6E, which has been rewritten to the third dot data (D5 to D7) after the sixth dot of the rewriting byte data (D0 to D7) as shown in FIG. O _m (D5, D6, D7, m3, m4,
m5, m6, m7) are generated, and the memory (2) 11
It is written at the same address of b (see FIG. 3).

As a result, the display data of 64 dots.times.64 dots stored in the memories (1) 11a and (2) 11b is the write start address A (11: 0).
The data of 1 byte from "000,000,000,000,000011" is rewritten to the rewriting byte data (D0 to D7) by one data access.

On the other hand, for example, 64 dots × 64 do shown in FIG.
In the display data of ts, the byte data (D) for rewriting after the fourth dot (m3) of the odd-numbered byte data (m0 to m7) corresponding to the address “001X” (octal)
The case of writing 0 to D7) will be described.

That is, the address "001" in FIG.
Byte data (m0 to m7) corresponding to X "(octal)
12-bit write start address A (11: 0) “0 indicating the writing in byte unit from the fourth dot (m3) of
When "00.000.001.011" is designated by the higher-level device, the upper 8-bit address A (11: 4) is "000000.00", and the lower 4-bit address A (3) Is “1”, the memory (1) 11
A generated address “000000.01” by the address generation circuit 12 is given to the address terminal A of a (see FIG. 2).
7), the even-numbered column byte data (M0 to M7) corresponding to the address “002X” in FIG. 7 is output from the even-numbered column output data terminal M, and the input data generation circuit (1) 13
a.

Further, the address terminal A of the memory (2) 11b has the address A (11: 4) "000.0" of the upper 8 bits of the write start address A (11: 0).
00.00 ”is directly given (see FIG. 3), the byte data (m0 to m7) of the odd column corresponding to the address“ 001X ”in FIG. 7 is output from the odd column output data terminal m, and the input data generation circuit ( 2) Given to 13b.

That is, the address "001" in FIG.
Byte data (m0) of an odd column corresponding to X "(octal)
7 to m7) when the write start address "000000.001.011" indicating the fourth dot (m3) is instructed by the higher-level device, the odd number of "001X" in FIG. Column byte data (m0-m
7) and the subsequent even-numbered byte data (M0 to M7) of “002X” in FIG. 7 are the data spanning the write range, respectively, in the memories (2) 11b and (1) 11 respectively.
a simultaneously read from the input data generating circuit (2) 13
b, (1) 13a.

Then, the input data generation circuit (2) 13b
(See FIG. 4), the write start address A (11:
0) According to the lower 3 bits A (2: 0) "011" of "000.000.001.011" and the inverted lower 4th bit "0""" 0011 "", the odd column byte data 5 after the 4th dot of (m0 to m7)
The dot data (m3 to m7) is 5 dot data (D0) from the first dot of the rewriting byte data (D0 to D7).
To D4), the rewritten byte data O _{m of} the odd-numbered columns (m0, m1, m2, D0, D1, D2, D3)
D4) is generated and written to the same address of the memory (2) 11b (see FIG. 3).

Along with this, in the input data generation circuit (1) 13a (see FIG. 4), the write start address A (11: 0) "000.000.001.011".
In accordance with the lower 4 bits A (3: 0) “1011” of the even-numbered column byte data (M0 to M7), the 3-dot data (M0 to M2) from the first dot is the rewriting byte data ( Rewritten byte data O _M (D5, D6, D7, M3, M) of the even-numbered columns rewritten to the 3-dot data (D5 to D7) after the sixth dot of D0 to D7)
4, M5, M6, M7) are generated, and the memory (1) is generated.
It is written to the same address 11a (see FIG. 2).

As a result, the display data of 64 dots × 64 dots stored in the memories (1) 11a and (2) 11b is the write start address A (11: 0).
The data of 1 byte from "000000.001.011" is rewritten to the rewriting byte data (D0 to D7) by one data access.

Next, for example, 64 dots × 64 do shown in FIG.
In the display data of ts, the case of reading the 1-byte data after the fourth dot (M3) of the even-numbered column byte data (M0 to M7) corresponding to the address “000X” (octal) will be described.

That is, the address "000" in FIG.
Byte data (M0 to M7) corresponding to X "(octal)
12-bit read start address A (11: 0) "0 indicating reading in byte units from the fourth dot (M3) of
When "00,000,000,000,000011" is designated by the higher-level device, the upper 8-bit address A (11: 4) is "000000,000,000", and the lower-order fourth-bit address A (3). Is “0”, the memory (1) 11
A generated address "000000.00.00" by the address generation circuit 12 is given to the address terminal A of a (see FIG. 2).
7), the even-numbered column byte data (M0 to M7) corresponding to the address “000X” in FIG. 7 is output from the even-numbered column output data terminal M and supplied to the output data generation circuit 14.

Further, the address terminal A of the memory (2) 11b has the address A (11: 4) "000.0" of the upper 8 bits of the read start address A (11: 0).
00.00 ”is directly applied (see FIG. 3), the byte data (m0 to m7) of the odd number column corresponding to the address“ 001X ”in FIG. 7 is output from the odd number column output data terminal m, and the output data generation circuit 14 Given to.

That is, the address "000" in FIG.
Byte data (M0) of even columns corresponding to X "(octal)
7 to M7), when the read start address "000000.000.011" indicating the fourth dot (M3) is instructed by the higher-level device, the even number of "000X" in FIG. Column byte data (M0-M
7) and the odd-numbered column byte data (m0 to m7) of "001X" in FIG. 7 that follows, as the data spanning the read range, respectively, as shown in FIGS. 6A and 6B. The data is read from the memories (1) 11a and (2) 11b at the same time and given to the output data generation circuit 14.

Then, in the output data generation circuit 14 (see FIG. 5), the read start address A (11: 0) "0".
In accordance with the lower 4 bits A (3: 0) "0011" of "00,000,000,000,000011", the fifth dot data (M3) after the fourth dot of the even-numbered byte data (M0 to M7). To M7) and the data (m0 to m2) from the first dot to the third dot of the odd-numbered byte data (m0 to m7) are combined, the read byte data as shown in FIG. 6 (F). DO (M3, M4, M
5, M6, M7, m0, m1, m2) are generated and read by the host device.

As a result, the display data of 64 dots × 64 dots stored in the memories (1) 11a and (2) 11b are read start address A (11: 0).
One byte of data from "000.000.001.011" is read by one data access.

Therefore, according to the display memory circuit having the above-mentioned configuration, for example, in the display data of 64 dots × 64 dots, the even number column “000X” divided by 8 dots in the X direction is used.
6 for each of "002X", "004X", and "006X"
The 4-byte data is stored in the memory (1) 11a and the odd-numbered columns “001X” “003X” “005X” “0
Each 64-byte data corresponding to 07X "is stored in the memory (2)
When the write start address A (11: 0) for 1 byte is designated from an arbitrary dot by storing it in 11b, the byte data of the even columns and the byte data of the odd columns that span the write range are respectively Memory (1) 11a, (2)
Input data generation circuit (1) 13 read from 11b
a, (2) 13b, only the dot data portions corresponding to the respective write ranges are rewritten byte data D.
Are rewritten according to
Since the data is written in the original address position of 11b, the byte data from an arbitrary dot can be written by one data access process executed simultaneously for the memories (1) 11a and (2) 11b. .

When a read start address A (11: 0) for 1 byte is designated from an arbitrary dot, the byte data of even columns and the byte data of odd columns that span the read range are respectively generated. Memory (1) 11a, (2)
The data is read from 11b and given to the output data generation circuit 14, and only the dot data portions corresponding to the respective read ranges are combined and read, so that the memory (1) 11a,
(2) Byte data can be read from an arbitrary dot by a single data access process executed simultaneously for 11b.

[0059]

As described above, according to the display memory circuit of the first aspect of the present invention, the display which is preceded and succeeded by a predetermined number of bits by one data access to the first and second memories is performed. Data can be rewritten across data.

Further, according to the display memory circuit of the second aspect of the present invention, one time data access to the first and second memories spans the display data which is preceded and succeeded by a predetermined bit number unit. Data can be read. Therefore, it is possible to read or write the data of a predetermined number of dots starting from an arbitrary dot with one data access.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display memory circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a memory address in the memory (1) of the display memory circuit and display data stored therein.

FIG. 3 is a diagram showing a relationship between a memory address in a memory (2) of the display memory circuit and display data stored therein.

FIG. 4 is a diagram showing a truth table of input data generation circuits (1) and (2) in the display memory circuit.

FIG. 5 is a diagram showing a truth table of an output data generation circuit in the display memory circuit.

FIG. 6 is a diagram showing a data writing process and a data reading process in the display memory circuit.

FIG. 7 is a diagram showing a memory address of a conventional display memory that stores display data of 64 dots × 64 dots.

FIG. 8 is a diagram showing an array of display data designated in byte units.

[Explanation of symbols]

11a ... Memory (1), 11b ... Memory (2), 12 ...
Address generation circuit, 13a ... Input data generation circuit (1), 13b ... Input data generation circuit (2), 14 ... Output data generation circuit.

Claims (2)

[Claims] 1. A first memory, a second memory in which an upper address of a write start address is input, and display data which is sequentially continuous in a predetermined bit number unit corresponding to the upper address is alternately written, and the first memory. An input data generation circuit for rewriting each of the continuous display data read from the second memory in units of a predetermined number of bits at a bit position corresponding to the value of the lower address of the write start address in accordance with external data. A display memory circuit comprising: and rewriting data between successive display data by a predetermined number of bits in one data access to the first and second memories. 2. A first memory, a second memory in which an upper address of a read start address is input, and display data which is sequentially continuous in a predetermined bit number unit corresponding to the upper address is alternately written, and the first memory. , Output data generation for inputting each of the continuous display data read from the second memory in units of a predetermined number of bits, and combining and outputting the data of bit positions corresponding to the value of the lower address of the read start address And a circuit, wherein data is read out across display data that are adjacent to each other in units of a predetermined number of bits by one data access to the first and second memories.