JPH07220065A - Method and device for picture processing - Google Patents

Abstract

PURPOSE:To provide the method and the device for picture rotation which rotate large-capacity picture data at a high speed in a minimum circuit scale. CONSTITUTION:32X32-Bit data is stored in RAMs 100 to 107. A decoder 2 decodes a RAM select signal 8 and a write signal 9 and outputs a write request signal. A decoder 3 takes a data select signal no as the input and outputs a bit select signal to select a specific bit of stored data in RAMs. Each circuit block 3000 selects only data selected by the bit select signal outputted by the decoder 3 out of output data from each RAM. Write data is given to each RAM through an original picture data line 6. An address signal 7 designates the data storage address of each RAM. The data write timing to each RAM is given through a write signal line 9. The data select signal 10 instructs selection of a specific bit of output data of each RAM. Rotated picture data is read out through a read data line 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image processing, and more particularly to an image processing method and apparatus for rotating image data.

[0002]

2. Description of the Related Art Conventionally, an image data rotating device is generally known as x, as described in JP-B-63-33348.
A register group composed of n bits in the coordinate direction and m bits in the y coordinate direction, a means for writing an image signal to n bits accessed at the same x address coordinate of the register group, and the same y of the register group. It is composed of gate means for decoding the read position at the address coordinate and reading the content of m bits at the same y coordinate. With this configuration, image data with a certain number of pixels can be rotated 90 ° to the left or right.
Rotate. For example, in fax or the like, a character is represented by image data consisting of vertical n bits x horizontal m bits.
The entire screen is formed. Therefore, in the screen configuration shown in FIG. 9, in the case of the horizontal writing shown in FIG. 9A and the case of the vertical writing shown in FIG. To convert from vertical writing to horizontal writing, or vice versa, the orientation of the image data must be changed.

FIG. 10 illustrates image rotation. FIG. 10A shows a case where image data consisting of n = m = 6 bits is rotated 90 ° to the left on the register, and (1) of FIG. 10A shows image data before rotation. 10, (2) in (a) of FIG. 10 shows image data after rotation. Such rotation of the image data can be performed by coordinate conversion calculation of each pixel forming the screen. However, the coordinate conversion calculation of each pixel requires a great deal of processing time.

Therefore, a register for coordinate rotation is provided,
The above-described method of rotating an image signal by performing writing and reading processing to and from this register has been proposed.

FIG. 11 shows the configuration of the conventional image data rotation device described above. In FIG. 11, 10, 20, ...,
Each of n0 is a register for storing n-bit image data, and the image data is written for each bit corresponding to the vertical direction by the write control signals 1, 2, ..., N to the respective registers. Reference numeral D denotes a decoder, which decodes the read register instruction signal and generates a read gate signal for controlling the read gate of each vertical bit string of the registers 10, 20, ..., N0. Each read gate signal is connected to each AND gate to which the read line of each vertical bit string is connected, and controls the data output from each 1 bit string. O-1, O-
2, ..., On are OR gates, and the OR gate O-1 is an AND gate 11- belonging to the register 10.
, 21-1, ..., N1-1 perform OR logic operation of the output signals, and output the OR gate O-n.
, N1-n of the gates 11-n, 21-n, ... Other OR
The relationship between the gate and the output signal of each gate belonging to the corresponding register is similar. OR gates O-1, O-
The output of 2, ..., O-n is read data and corresponds to each bit in the y direction.

FIG. 12 is a flow chart for explaining an image data rotating operation procedure using the conventional image data rotating device shown in FIG. In FIG. 12, (A) shows a procedure for setting contents to the register group, and (B) shows 90 °.
A procedure for saving the left-rotated image data in a memory (not shown) is shown.

In the image signal write data consisting of n × n groups, the image signal of the first row is first written in the lateral register 10 by the write control signal 1. Next, the write control signal 2 writes the image signal of the second row into the register 20. Similarly, the image signals of each row are sequentially written in the corresponding registers, and finally the image signal of the nth row is written in the register n0 by the write control signal n.

Next, in response to the gate 11 designating signal of the decoder D, the contents of the vertical 1-bit register row 11 are read out and output as read data, which is not shown in the drawing.
The data is written in the first row in the horizontal direction of the save memory consisting of xn groups. Next, the contents of the 1-bit register string 21 are read in response to the gate 21 designating signal, the coordinates are converted in the same manner, and the contents are written in the second row of the save memory. In the same manner, reading from the 1-bit register string and writing to the memory are sequentially performed, and finally the contents of the 1-bit register string n1 are read according to the gate n1 designation signal and written to the nth row of the memory. Be done.

In this way, the image signal written in the register of the n × n group is stored in the memory in the state of being rotated 90 ° counterclockwise, and the required image signal rotation is performed.

[0010]

However, in the above conventional example, the number of wiring patterns on the read side and the logical product circuit are n.
There is a problem in that the number of wiring patterns and the number of logic circuits increase in proportion to the increase in the image data, because the number x × m is required and the number of OR circuits is also required m. Due to the limitation of the circuit scale, there is a problem that a large-capacity image cannot be rotated at high speed.

The present invention has been made in view of the above-mentioned conventional example, and it is possible to rotate a large amount of image data with a minimum circuit scale.
It is also an object of the present invention to provide an image processing method and its apparatus that can be executed at high speed.

[0012]

In order to achieve the above object, the image processing method and apparatus of the present invention are (n bits) x
With respect to (m-bit) image data, k memories each including at least n bits per word and each having at least m / k word storage cells, and at the same address of each of the k memories, The same address is output to the storage means for storing each of the continuous row-wise data of the image data and the k memories,
Read-out means for sequentially selecting a predetermined bit of the output data of each of the memories and reading k-bit data rotated by 90 °.

Further, another invention is to provide (n bits) x (m bits) image data, at least n bits per word, and k memories each having at least m / k words of storage cells. A storing step of storing each of the continuous data of the image data in each row direction at the same address, and outputting the same address to the k memories to determine a predetermined output data of each of the k memories. A read step of sequentially selecting bits and reading 90-bit rotated k-bit data.

[0014]

In the above structure, (n bits) x (m bits)
Image data of k, each of the k memories includes at least n bits per word, and at least m /
The storage means of k words is provided, the storage means stores each of the continuous data of the image data in each row direction at the same address of each of the k memories, and the read means stores the k memories. The same address is output, predetermined bits of the output data of each of the k memories are sequentially selected, and k-bit data rotated by 90 ° is read.

Another invention is to provide (n bits) x (m bits) of image data with at least n bits per word and k memories each having at least m / k words of storage cells. At the same address, each of the continuous data in the row direction of the image data is stored, the same address is output to the k memories, and a predetermined bit of each output data of the k memories is sequentially output. Select and read k-bit data rotated by 90 °.

[0016]

According to the present embodiment, a plurality of RAMs are provided in addition to the conventional register group method, and a unique non-sequential writing procedure and a reading procedure for the plurality of RAMs of image matrix data are performed. Provided is an image rotation method and apparatus capable of rotating large-sized image matrix data at high speed. Further, according to the embodiment of the present invention as compared with the prior art, the image rotation device of the present embodiment can be provided with a significantly smaller number of wiring patterns and logic gates, so that there is a peculiar effect that can be realized at low cost.

FIG. 1 shows a configuration example of an image data rotation circuit which is an embodiment of the present invention. Here, for easy understanding, the size of the image data to be rotated is m = n =
32 (32 bits × 32 bits matrix).

In FIG. 1, 100 is 32 bits × 4.
R is a word RAM and has the same configuration as the RAM 100.
A total of eight AM101 to 107 are used. In Figure 1, of the 8 RAMs, only 3 are drawn and the remaining 5
That is, the RAMs 102 to 106 are omitted. With these eight RAM configurations, 32 × 32 bit matrix data can be stored. The matrix data is stored based on the correspondence between the matrix data and the addresses of the RAMs 100 to 107 for storing the matrix data as shown in FIG. This correspondence will be described below with reference to FIG.

Each horizontal axis of FIG. 2 shows a plurality of storage cell areas of 32 bits length from "D0" bit to "D31" bit, which correspond to each RAM address. Reference numeral 2000 indicates a row number of matrix data, and reference numeral 2001 indicates a RAM in which each row of the matrix data is stored and an address in the RAM. The unit of writing each row of matrix data to the RAM is 32 bits (6). Then, as shown by an arrow 1000, the writing procedure is started from the row number 1 of the matrix data, and writing is performed in the order in which the row number is incremented.

Returning to FIG. 1, the description of the configuration example of the image data rotation circuit according to the embodiment of the present invention will be continued. Reference numeral 2 denotes a decoder with an enable, which inputs a 3-bit RAM select signal 8 and a write signal 9 and decodes them to select and write a request signal to each RAM, that is, R
Wa, wb, for each of AM100-107
Output wc, wd, we, wf, wg, wh. still,
Here, the description of wc, wd, we, wf, and wg is omitted. In addition, the RAM select signal 8 and the write signal 9
Is, for example, from a CPU (not shown) to the RAMs 100 to 10
7 is output when the matrix data is written. A decoder 3 receives a data select signal 10 output from a CPU (not shown) and outputs a bit select signal for selecting a specific bit of the data stored in each RAM. An AND circuit 4 inputs one bit of the data output from each RAM and the bit selection signal output by the decoder 3 to perform a logical AND operation.
The calculation is performed and output to the OR circuit 5. The OR circuit 5 inputs the output from each AND circuit 4, performs a logical OR operation, and outputs it. The function of each circuit block 3000 composed of each AND circuit 4 and OR circuit is to select and output only the selected data from the data output from each RAM by the bit selection signal output from the decoder 3. Performs data selection function. Reference numeral 6 is a 32-bit original image data line, which is connected to, for example, a CPU (not shown), and writes data to the RAM to each RA.
It is a medium to give to M. 7 is, for example, a CPU (not shown)
Is an address signal connected to and driven by each R
Designate the AM data storage address. 8 is, for example,
A RAM select signal that is connected to a CPU (not shown) and is driven, and is input to the decoder 2. Reference numeral 9 is, for example, a write signal line which is connected to and driven by a CPU (not shown) and which gives a data write timing to each RAM and is input to the decoder 2. 10
Is, for example, a data select signal 10 that is connected to and driven by a CPU (not shown), and is a signal that gives a selection instruction for selecting a specific data bit in the output data of each RAM, and is input to the decoder 2. It Reference numeral 11 is a read image data line for reading the rotated image matrix data.

FIG. 3 is a flow chart for explaining the procedure of the image data rotation method in the embodiment shown in FIG. The embodiment shown in FIG. 1 will be described in detail below using this flowchart.

The current image data line (6), the address signal (7), the RAM select signal (8), the write signal (9), the data select signal (10) and the read data (11). , Connected to a CPU (not shown),
Address signals A0, A1 (7) output from the CPU
And RAM select signal (8) and write signal (9)
Then, input / output with each RAM is performed in synchronization with each timing signal of the data select signal (10). Here, the current image data line (6) is used to supply write data to each RAM, and the read data line (11) is used to read image data from each RAM. The execution of the flowchart shown in FIG. 3 is controlled by the CPU (not shown) described above.

In step S1, the CPU (not shown) clears the address signal 7 and the RAM select signal 8 to "0". Then, the data select signal 11 is set to the binary value "11111", and the internal register L of the CPU (not shown) is set to "1". This L is a pointer that points to the row number of the 32 × 32-bit image matrix data stored in advance in the memory in the CPU (not shown).

The rotation of the image data in the present embodiment is executed by the writing process of the image matrix data to each RAM and the reading process. The processing of each step will be described below.

In step S2, the write signal 9 is made active in order to write the data of one row of the matrix pointed to by L to the corresponding RAM. In response to this, the decode 2 selects the corresponding RAM and writes the write request signal (wa, w) to the selected RAM.
b, ..., Wh) is output. Then, the first row of the original picture matrix data is written in the selected area of the RAM at address 00.

In step 3, the RAM select signal 80
Is a binary value "111", and if different, the process proceeds to step S4, the RAM select signal 8 and L are incremented by 1, and the process returns to step S2.
The writing process is repeated. If they match, the process proceeds to step S5.

In step S5, the RAM select signal is cleared to "0".

In step S6, it is checked whether the address signal 7 has a binary value "11", and if different,
In step S7, the address signal is incremented by 1,
Returning to step S2, the writing process is repeated. If they match, the process proceeds to step S8.

In step S8, the address signal is set to "0".
Set to.

By the processing described above, writing is performed in the order shown in FIG.

In step S9, since the matrix data writing process to the RAM has been completed by the above process, a message notifying the end of the matrix data writing process is displayed on a display monitor (not shown) or the like. Then, a request for performing the rotation process is input from a keyboard (not shown). When a rotation processing request is input, step S
Go to 10.

Next, a method of reading from each RAM for generating the image matrix data subjected to the rotation processing will be described.

In step S16, the address signal is set to "0". Further, the data select signal 10 is set to the binary value “11111”.

In step S10, the read data (11) is accordingly read as each of the RAM100 to RAM10.
The 31st bit of the storage area of the address “00” of No. 7 is output. Then, the output read data (1
1) is saved in a memory (not shown) that stores the image matrix data that has been rotated by the timing control of the CPU (not shown).

In step S11, the address signal 7 is
Check if the binary value is "11", and if different,
In step S12, the address signal 7 is incremented by 1, the process returns to step S10, and the next data reading is performed. If they match, the process proceeds to step S13.

In step S13, the address signal 7 is set to "0".

In step S14, it is checked whether or not the data select signal 10 is "0". If they do not match, the data select signal 10 is counted down by 1 in step S15 and the process returns to step S10 to read the next data. I do. If they match, the process ends.

The rotated image data which is the processing result is stored in the above-mentioned memory (not shown).

By the above-described unique rotation processing procedure, that is, the unique non-sequential writing procedure and the reading procedure of the image matrix data with respect to the plurality of RAMs, it is possible to rotate the image matrix data of a large size at one time. it can.

Here, in the process of generating the rotated image matrix data, each RA after step 16 is executed.
The procedure of reading from M will be further described with reference to FIG.

FIG. 4 shows each R in the processing up to step 15.
It is a figure explaining the procedure which reads in different procedures, in order to obtain the data of the rotated arrangement from the image matrix data stored in AM. Each row shows a written data bit storage area corresponding to one address of the RAM to be read. Reference numeral 2001 indicates one address of the RAM to be read. Reference numeral 3000 indicates the reading order of each data bit storage area. That is, the sequence number "1" is continuously described in 8 bits from the top in the bit (MSB: most significant bit) of "D31".
Address 00-RAM 107 address 00 "D"
This means that 31 "bits are simultaneously read and output to the read data line (11). At the next read timing, 8 bits of the sequence number" 2 "are read. Similarly, this reading process is performed by the sequence number “128”.
Up to 8 bits. 1001 indicates the reading order of each bit, and the bit order in the direction of the arrow, that is, "D"
It is read in the order of 31 "bits to" D0 "(LSB: least significant bit) bits.

According to the rotation processing method and its apparatus of the present embodiment described above, for example, the original image matrix data as shown in FIG. 5 is written in the RAMs 100 to 107 and read out according to the procedure described above. Then, the rotated image matrix data shown in FIG. 6 can be obtained.

FIG. 7 is a diagram for explaining the estimation of the circuit scale when the configuration of FIG. 1 is realized at the semiconductor chip level. As can be seen from FIG. 7, there are 8 32-bit x 4-word RAMs, 256 2-input AND gates, and 3
A 2-input OR gate can be composed of 8 gates.

By comparing the estimations of FIGS. 7 and 12, it can be seen that the image rotation method and its apparatus of this embodiment can reduce the number of wiring patterns and the number of logic gates to about 1/4 of the conventional one.

For image data smaller than the allowable matrix data size composed of a plurality of RAMs,
It suffices to write only the image matrix data, read only the data in the effective area, and discard the extra bits. This state is shown in FIG. That is, for example, when the image data is 16 bits × 20 bits, up to 20 lines are written in the order indicated by the arrow 1004. And 1
Up to 16 columns are read in the order shown in 003. Unused data in multiple RAMs can be ignored. On the contrary, for image data larger than the allowable matrix data size configured by a plurality of RAMs, the image data may be divided into a matrix size and divided into a plurality of times for processing.

As another method for large image data, simply increasing the size of the RAM in the word direction makes it possible to cope with the change without changing the logic portion. That is, although the 32-bit x 4-word RAM is used in FIG. 1, for example, a 32-bit x 16-word RAM may be used, or four 32-bit x 4-word RAMs may be connected in the word direction.

It should be noted that it rotates 90 ° in the reverse direction (27 in the forward direction).
To rotate 0 degree), reverse the reading order,
Further, it can be realized by turning over the bit order (MSB, LSB inversion).

It is also clear that if 90 ° rotation is repeated twice, 180 ° rotation is obtained, and if it is repeated 3 times, 270 ° rotation is obtained.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, the present invention is a program for a system or apparatus. As described above, according to the present embodiment, a plurality of R
AM is provided and a plurality of RAs of image matrix data are provided.
By the unique non-sequential writing procedure and reading procedure for M, it is possible to provide an image rotation method and apparatus capable of rotating a large size image matrix data at high speed. Further, according to the embodiment of the present invention as compared with the prior art, the image rotation device of the present embodiment can be provided with a significantly smaller number of wiring patterns and logic gates, so that there is a peculiar effect that can be realized at low cost.

[0050]

As described above, according to the present invention, it is possible to rotate a large amount of image data at a high speed with a minimum circuit scale.

[0051]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image rotation device of this embodiment.

FIG. 2 is a diagram showing an arrangement and a writing order of a plurality of RAMs in the image rotation device of the present embodiment.

FIG. 3 is a flowchart illustrating a processing procedure in this embodiment.

FIG. 4 is a diagram showing an arrangement and a reading order of a plurality of RAMs in the image rotation device of the present embodiment.

FIG. 5 is a diagram showing an example of original image matrix data.

FIG. 6 is a diagram showing data obtained by rotating the original image matrix data of FIG. 5 using the image rotating device of the present embodiment.

FIG. 7 is a diagram showing an estimation of the circuit scale of the image rotation device of the present embodiment.

FIG. 8 is a diagram showing a method of rotating small image data.

FIG. 9 is a diagram showing an example of an image before rotation and an image after rotation.

FIG. 10 is a diagram showing an example of an image before rotation and an image after 90 ° left rotation.

FIG. 11 is a diagram showing a configuration of a conventional image rotation device.

FIG. 12 is a flowchart of a rotation process of a conventional image rotation device.

FIG. 13 is a diagram for estimating the circuit scale of a conventional image rotation device.

[Explanation of symbols]

 1 RAM 2, 3 Decoder 4 AND circuit 5 OR circuit

Claims (4)

[Claims] 1. An image processing apparatus for rotating (n-bit) × (m-bit) image data, comprising k bits each including at least n bits per word and each having at least m / k word storage cells. A memory, a storage unit that stores each piece of continuous image data in the row direction at the same address of each of the k memories, and the same address is output to each of the k memories. An image processing apparatus, comprising: a reading unit for sequentially selecting a predetermined bit of each output data of the memory and reading k-bit data rotated by 90 °. 2. The k memories are i-th memories (i.
= 1,2, ..., k), wherein the storage means stores n bits in the row direction and m bits of image data having a coordinate range in the column direction of 0 to m-1 into the i-th image data. The coordinates "c · (m / k) + (i-
1) :( c = 0,1, ..., k-1) ", each n-bit data is stored, The image processing apparatus according to claim 1. 3. An image processing method for rotating (n-bit) × (m-bit) image data, comprising k bits each including at least n bits per word and having at least m / k word storage cells. A storing step of storing each of the continuous data of the image data in each row direction at the same address of each of the memories, outputting the same address to the k memories, and outputting the output data of each of the k memories. An image processing method, comprising: a step of sequentially selecting predetermined bits and reading out k-bit data rotated by 90 °. 4. The k memories are i-th memories (i.
= 1,2, ..., k), in the storing step, n-bits in the row direction and m-bits of image data having a coordinate range in the column direction from 0 to m-1 are converted into the i-th image data. The coordinates of the image data in the same column direction "c.
4. The image processing according to claim 3, wherein each n-bit data of (m / k) + (i-1) :( c = 0,1, ..., k-1) "is stored. Method.