JPH0721239A - Design rule check execution device - Google Patents

Abstract

PURPOSE:To efficiently and precisely execute verification without altering a conventional layout inspection execution program by providing a means for simultaneously verifying a layout for plural systems in parallel. CONSTITUTION:A rule file 11, layout data 12, a layer selection processing means 2 and a layout verification means 3 are provided with means for dividing the rule file 11 of the plural n-systems into groups which can independently process the check items prior to the verification of a layout from one basic rule file where the plural n-systems are provided in parallel and all the check items are recorded and for distributing them, and they are provided with means which simultaneously verify the layout for the plural n-systems in parallel. Furthermore, a result synthesis means 4 synthesizing the verification result of the layout verification means 3 of the plural n-systems and the verification result file 13 of the n-system, which individually accumulates the verification result of the layout verification means 3 of the plural n-systems are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used for layout verification of large-scale layout design data of an integrated circuit.
The present invention divides the check items of a complicated and large number of design rule checks into some groups that are independent of each other in advance, processes each item group, and can perform layout verification at high speed. Regarding the execution device.

[0002]

2. Description of the Related Art With the recent increase in scale and density of integrated circuits, layout verification of layout design data must deal with a large amount of graphic data at a time, and the processing time thereof is increasing. . Therefore, a method of performing layout verification at a higher speed has been conventionally studied.

FIG. 7 is a flow chart showing the flow of the processing operation in the case where the layout verification is parallelly processed by dividing the layout design data in the conventional example.

First, the layout design data is subjected to area division processing (step 1), the data is divided into several areas, and the data of each of the divided areas is used as an input to check items of design rules. The layout verification is performed in parallel according to the items of the rule file in which is described (step 2). Next, when each verification result is output, the error data of each verification result is combined (step 3) to obtain one result data corresponding to the entire layout design data. In the case of this example, since each input data is divided and made smaller in each verification process, the processing time is shortened and the entire processing time is speeded up (see Japanese Patent Laid-Open No. 125369/1990).

FIG. 8 is a flow chart showing the flow of processing operations in the case where a layer of layout design data is designated in advance and verification is performed by limiting check items in the conventional example.

Of all the layers of the layout design data, some layers to be checked are designated in advance (step 1), the check items required for checking the layers are selected from the rule file, and the carefully selected check items are output ( In step 2), the layout verification is executed only for this check item (step 3). Also in this case, the processing time is shortened and the data amount of the verification result is reduced, so that the verification result confirmation work can be easily performed (see Japanese Patent Laid-Open No. 3-77346).

[0007]

As described above, in the conventional method, since the input data is limited to a small size, the layout verification execution time can be shortened. When the normal layout verification process is performed on the, the data that is divided into two areas in the layout data around the boundary of the area cannot be checked. It is necessary for the verification execution program to take special measures regarding the data processing around this area boundary. In this case, it is easy to overlook an error, and there is a problem that the program modification is troublesome.

Further, the layer designation method is premised on shortening the execution time by narrowing down the number of layers to be checked. Therefore, when it is desired to execute a complicated check involving many layers, it is almost necessary. Ineffective,
Therefore, there is a problem that it is not suitable for verifying the layout design data of an integrated circuit which becomes large in scale.

The present invention solves such a problem, and an object of the present invention is to provide an apparatus capable of performing efficient and accurate verification without modifying a conventional layout verification execution program.

[0010]

According to the present invention, there is provided a rule file in which check items represented by a combination of types of processing and layers used in the processing are recorded, and layout data in which input inspected data is recorded. And layer selection processing means for selecting the data of the corresponding layer from the layout data according to the command of the check item read from the rule file, and the layout verification is executed for the data selected by the layer selection processing means. In a design rule check execution device including layout verification means, a plurality of n series are provided in parallel for the rule file, the layout data, the layer selection processing means, and the layout verification means, and all check items are provided. From the recorded basic rule file, the plurality of n For each rule file of the column,
It is provided with means for dividing and distributing the check items into groups that can be processed independently of each other prior to execution of the layout verification, and means for simultaneously executing the layout verification in parallel over a plurality of n series. And

Result combination processing means for combining the verification results of the layout verification means of the plurality of n series is provided,
It is desirable to provide an n-series verification result file for individually accumulating the verification results of the series layout verification means.

[0012]

[Function] From the input rule file in which the check items are expressed by the combination of the type of processing and the layer used for the processing, those having the connection of layers are collected and extracted as a plurality of groups into the division rule files independent from each other.
The contents of this division rule file and layout design data are input and layer selection processing is performed. Of the layers existing in the layout design data, the input layers that appear in the division rule file are extracted in advance as the layout verification processing target, and the design Performs rule checks and performs layout verification independently. After all the verification processes are completed, the output error data is combined, and the data of a plurality of files are combined into one.

Thus, the layout verification can be efficiently performed and layout verification can be efficiently performed without modifying the conventional layout verification execution program, and a correct verification result can be obtained without overlooking errors due to division.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a diagram showing the contents of a rule file in the first embodiment of the present invention, and FIG. It is a figure which shows the content of the division rule file in one Example.

In the first embodiment of the present invention, a rule file 11 in which check items expressed by a combination of types of processing and layers used in processing are recorded, and layout data 12 in which input inspection data are recorded. And an item division processing means 1 for fetching check items from the rule file 11 and temporarily storing the connected items of respective layers of the integrated circuit in the division rule file 14 as a group of independent check items, and a rule file. Layer selection processing means 2 for selecting the data of the corresponding layer from the layout data 12 according to the command of the check item read from 11, and layout verification means for performing layout verification on the data selected by this layer selection processing means 2. 3 and further, as a feature of the present invention, a rule file Le 11, the layout data 12, the layer selecting unit 2, and the layout verification unit 103 is a plurality n sequences are provided in parallel, the plurality n from the basic rules file one in which all of check items are recorded
For each rule file 11 of the series, the check items are divided and divided into groups that can be processed independently of each other prior to the execution of the layout verification, and the layout verification is simultaneously performed in parallel over a plurality of n series. And means for executing the same.

Also, a plurality of n-series layout verification means 3
The result synthesizing processing unit 4 for synthesizing the verification result and the n-series verification result file 13 for individually accumulating the verification results of the plurality of n-series layout verifying units 3 are provided.

Next, the processing operation of the first embodiment of the present invention thus constructed will be described. FIG. 4 is a flow chart showing the flow of processing operations in the first embodiment of the present invention. As shown in FIG. 2, the rule file has items to be checked line by line, which are realized by a combination of types of processing and layers used for processing. For example, the first line shows that the first layer and the second layer are ANDed and output to the tenth layer. AND, OR, and NOT represent graphic operation commands, and INT, EXT, and ENC represent line check commands. If you trace the connection of layer numbers in this rule file from the line check item side, the ENC on the 5th line
The operation is performed using the result of the NOT operation on the fourth row and the ninth layer. Similarly, the INT check on the sixth line is AN on the first line.
10 layers of the D operation result and 1 of the OR operation result of the second row
It can be seen that the first layer is used and the EXT check on the seventh line is performed using the 12th layer which is the result of the AND operation on the third line. Therefore, if the items having these layers are combined into one group, they can be divided into three check item groups that are completely independent of each other. In this way, one rule file is divided into three division rule files (1) to (3) as shown in FIG. 3 (step 1).

Next, the layer selection process is performed by inputting the contents of the division rule file and the layout design data (step 2). This process is based on the division rule / layer of the layers existing in the input layout design data.
Only the input layers that appear in the file are extracted in advance for layout verification processing.
In the case of the rule file (1) shown in FIG. 3, 1 layer, 2
Select 3 layers, 4 layers, 5 layers and 6 layers in the case of rule file (2), 7 layers, 8 layers and 9 layers in the case of rule file 3 respectively. A design rule check is performed based on the extracted data and a rule file, and layout verification is executed independently of each other (step 3).

When all the verification processes are completed, the error data resulting from the verification processes is combined (step 4). Because each error data has no overlapping data due to the rule file division method,
As a result, the synthesizing process is simply a process of combining the data of a plurality of files into one.

(Second Embodiment) FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention. FIG. 6 is a flow chart showing the flow of processing operations in the second embodiment of the present invention.

The second embodiment of the present invention is constructed by removing the result synthesizing processing means 4 in the first embodiment, and is otherwise the same as the first embodiment. The advantage of this second embodiment is that
When performing divided result verification processes in parallel and combining the results, it is necessary to wait until the end of the verification process for all the divided parts, but the processing ends earlier by outputting each verification result separately. Since the result can be confirmed from, it is possible to efficiently verify even if the execution time of one divided portion becomes significantly longer than the other.

[0023]

As described above, according to the present invention, the conventional layout verification execution program can be divided and efficiently executed without modification, and correct verification results can be obtained. . Further, when the divided layout verifications are performed in parallel, the execution time can be shortened in almost inverse proportion to the number of divided rule files, and the error can be overlooked by the division.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing the contents of a rule file in the first embodiment of the present invention.

FIG. 3 is a diagram showing the contents of a division rule file in the first embodiment of the present invention.

FIG. 4 is a flowchart showing the flow of processing operations in the first embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 6 is a flowchart showing the flow of processing operations in the second embodiment of the present invention.

FIG. 7 is a flowchart showing a flow in a case where layout verification is processed in parallel by dividing the layout design data into areas in the conventional example.

FIG. 8 is a flowchart showing a flow of processing operations when a layer of layout design data is designated in advance and verification is performed by limiting check items in the conventional example.

[Explanation of symbols]

 1 item division processing means 2 layer selection processing means 3 layout verification means 4 result composition processing means 11 rule file 12 layout data 13 verification result file 14 division rule file

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04

Claims (3)

[Claims] 1. A rule file in which check items expressed by a combination of types of processing and layers used for processing are recorded, layout data in which input inspection data is recorded, and read from the rule file. Layer selection processing means for selecting data of a corresponding layer from the layout data according to an instruction of the check item
A design rule check execution device comprising: layout verification means for executing layout verification for the data selected by the layer selection processing means, wherein the rule file, the layout data, the layer selection processing means, and the layout verification means A plurality of n series are provided in parallel, and one check rule file is recorded from the basic rule file in which all check items are recorded. And a unit for dividing and distributing each group that can be processed independently of each other, and a unit for simultaneously performing the layout verification in parallel over a plurality of n series. 2. The result synthesizing processing means for synthesizing the verification results of the layout verification means of the plurality of n series.
Design rule check execution device described. 3. The design rule check execution device according to claim 1, further comprising an n-series verification result file for individually accumulating verification results of the plurality of n-series layout verification means.