JPH07211722A - Semiconductor device and its packaging structure - Google Patents

Abstract

PURPOSE:To enhance the reliability upon the semiconductor device by increasing the level of the fine bump electrodes on a semiconductor chip for optimizing the material composition of the bump electrode to be formed. CONSTITUTION:The semiconductor device is provided with a metallic thin film 5 formed on bonding pads 4 of a semiconductor chip, the bump electrodes comprising the first metallic layer 6 and the second metallic layer 7 projectively formed on the metallic thin film 5 while the second metallic layer 7 contains 40wt.% of carbon, 30wt.% of sulfur and 10wt.% of oxygen. This semiconductor device is to be flip-chip packaged on the electrode pads 10 of a circuit wiring substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having bump electrodes on a semiconductor chip and a semiconductor device mounting structure in which the semiconductor device having bump electrodes is flip-chip mounted on a circuit wiring board.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated,
Mounting technology is also required to have higher density. Wire-bonding technology, TAB technology, etc. are typical examples of high-density mounting technology for semiconductor devices. In recent years, flip-chip mounting technology has been used as the highest-density mounting technology to improve semiconductor devices such as computer equipment. It is often used as a technology for mounting at high density. This flip chip mounting technique is disclosed in US Pat. Nos. 3,401,126 and 3,42.
It has become a widely known technique since the disclosure of 9,040.

In the flip-chip mounting technique, as shown in FIG. 67, bump electrodes 42 having a protrusion shape are formed on the bonding pads 4 of the semiconductor device 1, and the semiconductor device 1 is bonded via the bump electrodes 42. Pad 4
Is a technique for electrically and mechanically interconnecting an electrode pad of a circuit wiring board. In FIG. 67, reference numeral 3 indicates a passivation film and reference numeral 5 indicates a metal thin film serving as a barrier metal.

In flip-chip mounting, since the constituent material of the semiconductor device and the constituent material of the circuit wiring board on which the semiconductor device is mounted are different, the thermal expansion coefficient of the semiconductor device and the thermal expansion coefficient of the circuit wiring board are different from each other. Is common.
Therefore, the amount of heat generated during the operation of the semiconductor device is transferred to the circuit wiring board through the bump electrodes, and the displacement caused by the difference in the thermal expansion coefficient occurs between the semiconductor device and the circuit wiring board.
The generated displacement between the semiconductor device and the circuit wiring board causes stress distortion in the bump electrodes connecting the semiconductor device and the circuit wiring board.

Further, the stress strain due to the displacement caused by the difference in the coefficient of thermal expansion also occurs when the semiconductor device that has generated heat is cooled. Further, even when a temperature difference occurs in the external temperature atmosphere, the same stress strain as described above occurs in the bump electrode portion. The stress distortion of the bump electrode portion breaks the bump electrode mounted on the flip chip, and reduces the reliability life.

The stress strain generated in the bump electrode portion has been conventionally solved by using the following means.

(1) To reduce the distance from the center point of the semiconductor device to the center point of the bump electrode.

(2) To reduce the difference between the coefficient of thermal expansion of the semiconductor device and the coefficient of thermal expansion of the circuit wiring board.

(3) Improving heat dissipation so that temperature change does not increase.

(4) The gap between the semiconductor device and the circuit wiring board is filled with resin to strengthen the flip-chip mounting structure.

(5) The bump electrode structure has a structure capable of sufficiently absorbing the stress strain generated.

That is, IBM J. Res. Develo
p. , 13; 251 (1969), the reliability life is Nf = Cf ^1/3 γ _max · exp (1
428 / T _max ) from the cycle life formula (C; constant, f; frequency, T _max ; maximum temperature), the maximum shear strain γ _max generated in the bump portion is reduced to improve the reliability life. It is known to improve.

Further, the maximum shear strain generated in the bump electrode portion shown in the reliability life formula is expressed by the following formula.

Γ _max = {1 / (D _min / 2) ^{2 / β} } (V
/ Πh ^{1 + β} ) ^{1 / β}・ d ・ ΔT ・ Δα (D _min ; minimum bump diameter, β; material constant, V; solder volume, h; solder height, Δα; thermal expansion coefficient difference, ΔT; temperature Therefore, in order to improve the reliability of flip chip mounting,
The above (1) to (5) for relieving the stress of the bump electrode portion
It can be realized by means of.

For example, a method (1) of changing the arrangement of the bump electrodes to reduce the distance from the center point of the semiconductor device to the center point of the bump electrodes is proposed in Japanese Patent Application No. 4-19855. There is. This method is usually a method of re-laying out the bonding pads laid out for wire bonding on the semiconductor chip using the polyimide multilayer wiring technology, and is a proposal to reduce the amount of displacement due to temperature cycle. is there.

An attempt to make the coefficient of thermal expansion similar to or the same as the coefficient of thermal expansion of a semiconductor device in consideration of the material of the circuit wiring board (2) is to use silicon as the circuit wiring board material.
Or, as an attempt to use AlN, MCM (M
This is a widely known technique in the multichip module technique.

The method (3) for reducing the temperature change of the flip-chip mounted semiconductor device and reducing the generated displacement can be solved by providing a radiation fin on the back surface of the semiconductor chip, and many proposals have been made. Is being done,
For example, Japanese Patent Application Laid-Open No. 58-23462 discloses an example in which a radiation fin is mounted on the back surface of a semiconductor device.

With respect to the displacement caused by the temperature difference,
A method of filling a resin in the gap between the semiconductor device and the circuit wiring board in order to strengthen the structure of the flip chip mounting body (4)
For example, a method of filling a resin (Japanese Patent Laid-Open No. 61-
194732), a method of sealing an ultraviolet curable resin (JP-A-62-252946), a method of sealing a gap with a room temperature-curable resin (JP-A-63-13337), and further sealing. There are many methods such as a method for optimizing the physical properties of the resin (Japanese Patent Laid-Open No. 4-219944).

Further, since the stress strain applied to the bump electrode also depends on the material constant, as is clear from the above shear strain equation, it is proposed to limit the solder material constant within the optimum range. Is being done. For the solder material, see Proc. 26th ECC, 67, (1976)
As described in P.
It has been reported that a -5% Sn alloy is effective for reliability.
2 and JP-A-61-80828, the Sn content is 65-80%, or 50%.
There have been many reports that it is desirable to make the ratio%, and stress relaxation is carried out by a method according to the actual situation.

Further, the strain applied to the bump electrode in the flip chip mounting decreases in inverse proportion to the bump height, as is clear from the above shear strain equation, and the reliability life increases with the bump height. Conventionally, flip chip mounting has been applied when the semiconductor device has a relatively small number of I / O pins, so that the bump height can be relatively easily increased.

However, the increase in I / O pins accompanying the recent increase in integration of semiconductor devices causes a decrease in the diameter of bump electrodes. Therefore, the conventional method of increasing the bump height by utilizing the surface tension of solder is used. Then, as the diameter of the bump electrode decreases, the bump height inevitably decreases, resulting in a serious problem that the reliability against stress strain decreases. The substrate is a ceramic substrate, AlN substrate,
The problem is not large in the case of a silicon substrate, but the problem is particularly large in the case of a glass epoxy substrate having a relatively large coefficient of thermal expansion.

A method of arranging the bump electrodes on the semiconductor chip in an area is described in Microelectronics Pa.
Clacking handbook (1989). This method is a method in which bump electrodes are formed into areas on bonding pads which are arranged in areas in advance. By arranging the bump electrodes in the area, the bump size can be increased and the bump height can be increased. However, there is a limit in arranging the bump electrode having a large size on the semiconductor device having a very high integration and a small chip size, and as a result, there is a problem that the bump height cannot be increased.

As a method for increasing the bump height, as described in JP-A-62-117346,
Typically, a bump electrode structure having a multi-stage structure with a polyimide tape interposed is proposed. According to this method,
Since the bump height can be increased, it is possible to improve the reliability life as compared with the conventional technology, but bump formation using a polyimide tape is complicated and difficult,
In addition to requiring a high level of technology, the number of steps has increased as the number of stages has increased, which has increased the cost for forming electrodes.

Next, the method (5) for sufficiently absorbing the stress strain generated in the bump electrode will be described in detail below.

The bump electrodes on the semiconductor device flip-chip mounted on the circuit wiring board usually have a drum-shaped structure as shown in FIG. 68 due to the load of the semiconductor device itself when reflowing. U.S. Pat. No. 3,401,126 describes drawings showing the bump structure of a drum-shaped bump. Further, Japanese Patent Laid-Open No. 60-38839 proposes a structure in which a bump having a drum shape has an elliptical shape in the stress generation direction in order to reduce the stress strain generated. In FIG. 68, reference numeral 2 is a circuit wiring board, 8 is an electrode pad of the circuit wiring board, 9 is a solder resist or a protective film of the circuit wiring board, and 11 is an electrode barrier metal of the circuit wiring board. Shown respectively.

On the other hand, the stress strain applied to the bumps destroys the bump structure itself and causes delamination near the contact between the bump metal and the barrier metal. This peeling is due to the large stress strain concentrated in the bump metal and barrier metal portions, especially in the drum-shaped bump. As a means for relieving the stress concentrated in the vicinity of the barrier metal, Japanese Patent Laid-Open No. 59-5637 proposes a structure in which the bumps 42 are staggered as shown in FIG.

The reason why the bump structure is the continuous type is that the bump structure can be strengthened in the barrier metal portion where stress strain is most likely to concentrate. Therefore, many proposals have been made so far as a method of making the bump electrode structure a continuous type. Japanese Unexamined Patent Publication No. 62-139386 discloses a method in which a drum-shaped bump is formed into a staggered type by using bump height control pins, and Japanese Unexamined Patent Publication No. 62-156745 discloses a bump structure in which the bump structure is formed into a staggered type. Japanese Unexamined Patent Publication No. 60-119737 discloses a method of forming bumps with a solder having a large volume as a support, and Japanese Unexamined Patent Publication No. 62-206843 discloses a continuous bump structure using spacers. Each method is described.

As a special method of forming the bump electrode structure in a continuous shape, Japanese Patent Laid-Open Nos. 62-117346 and 59-218744 disclose bump metal as a low melting point metal layer and a low melting point metal layer. A method has been proposed in which the structure has a staggered shape when reflowing as a combination of two layers of melting point metal layers.

Further, US Pat. No. 3,303,393 discloses a structure in which a bump electrode structure is formed in a continuous type and copper balls capable of increasing the bump electrode height are arranged in solder. Have been described. However, in this method, although the bump height can be increased by disposing the copper balls, by using the copper balls, the aspect ratio represented by the ratio of the bump diameter to the bump height becomes 1, and the required bump height can be increased. In order to secure the bump, there is a problem that the bump electrode having a fine structure with a small bump diameter cannot be formed.

That is, as is clear from the above shear strain equation, in order to improve the reliability life of the flip-chip mounting structure, even if a staggered bump is formed,
Since it is required to form bump electrodes with high height, this method has a problem in reliability. The cross-sectional structure of this bump electrode is described in IBM J. Res. Development. , 13; 2
31 (1969).

Further, the structure shown in FIG. 70 described in Japanese Patent Laid-Open No. 235102/1993 has a mushroom type metal column member 6 disposed inside a bump electrode 7. In this structure, it is possible to increase the height of the bump electrode 7 by increasing the height of the mushroom-type metal column member 6. Further, according to this structure, US Pat.
Since the spherical pillar material as described in No. 303,393 is not used, it has the effect of excellent heat dissipation and improved pull-out strength.

However, in this proposal, it is difficult to control the shape of the mushroom type, and unless the dimension control is strictly performed, the upper dimension of the mushroom type internal metal exceeds the electrode pad dimension of the circuit wiring board to be interconnected. However, there is a problem that it cannot be sufficiently miniaturized.

Therefore, in JP-A-60-57957, as shown in FIG. 71, a copper pole 6 having a high aspect ratio is used.
Has been proposed in which the bumps 7 are arranged in the bump metal 7 to form the bumps 7 having a high height, and the bump shape is formed into a hook shape to improve reliability. 71 (a) shows the case where the bump electrode height is increased, and FIG. 71 (b) shows the case where the copper pole size is made smaller than that of FIG. 71 (a) to reduce the bump electrode height. c) shows the structure when the amount of solder to be formed is adjusted and the bump electrode shape is drum-shaped.

This proposal proposes that copper bumps can be connected even if the bump electrode is broken, that the semiconductor chip and the circuit wiring board are provided with poles, respectively, and that the reliability is improved. The effect is that the height and shape can be controlled. However, this structure uses copper poles to connect the circuit wiring board to the semiconductor device, so if the height of the copper poles is not uniform, a connection failure will occur and an extremely strong connection structure will result. Therefore, there is a serious problem that the stress strain caused by the displacement caused by the temperature cycle cannot be relaxed.

That is, when the bump material is formed of only solder, the bump electrode is easily deformed by increasing the height of the bump electrode, and the stress strain can be sufficiently relaxed. When copper, which is a hard metal material, is provided in the portion, the bump electrode is less likely to be deformed, and conversely, the reliability against stress strain is not improved.

Further, this structure is disclosed in JP-A-60-5795.
According to the method described in the example of Japanese Patent Publication No. 7, the production is extremely difficult. That is, PGA (Pin Gri)
In the dArray) pin mounting method, the manufacturing time is extended as the number of I / O pins is increased, and the cost is improved. In the mask vapor deposition method, it takes a long manufacturing time to form a high pole. Furthermore, with the method using plating, it is impossible to firmly fix the poles on the semiconductor device side and the circuit wiring board side with good adhesion, and it is extremely difficult to form a connector shape. Also, the bump structure is
Although the structure is described in both the drum type and the drum type, it is considered that the shape control is performed by the amount of solder forming the connection portion, which is difficult in practical use.

FIG. 72 shows a structure in which the shape of copper arranged inside the bump electrode is inverted trapezoidal and the upper surface is curved. The details of this structure are described in 1993 IEICE Autumn Meeting Proceedings p5-13. In the figure shown in this document, since the upper portion of the copper placed in the bump electrode has an arc shape, it has a shape close to an inverted trapezoidal shape, but regarding the composition and physical properties of the solder forming the bump electrode, and the dimensional shape, Since no particular consideration was given, sufficient results were not obtained for the reliability life.

In the structure described above in which the rigid metal is arranged inside the bump electrode, the bump electrode is not sufficiently deformed even if the height of the bump electrode is increased. It is naturally included in Japanese Patent No. 3,303,393 and Japanese Patent Laid-Open No. 5-235102.

Further, the bump electrodes, which are miniaturized with the recent trend of higher integration of semiconductor devices, also affect the reliability in strength of the bump electrodes before the flip-chip mounting process. For example, a bump electrode formed on a semiconductor device has a compressive stress therein after the bump electrode is formed. Therefore, if the bump electrode is miniaturized, the bump electrode itself may be a barrier metal portion before the flip chip mounting process. There was a problem of breaking due to stress.

Japanese Unexamined Patent Publication No. 59-121955 proposes a solution to the problem of delamination due to residual stress particularly in the barrier metal part, in which titanium having oxygen dispersed in the barrier metal is used to increase tensile stress. It is a way to alleviate. The barrier metal structure that uses titanium as an adhesive metal basically has a tensile stress, but it was discovered that a titanium thin film in which oxygen is dispersed has a compressive stress. Apply to metal,
It is a proposal to reduce peeling defects due to tensile stress.

Further, in Japanese Patent Laid-Open No. 56-121955 and US Pat. No. 5,137,845, the barrier metal composed of Cr / Cu / Au has a structure in which the end has an inclination, and stress concentrated at the end is applied. It alleviates. 67 and 68 are diagrams showing a barrier metal structure having an inclination at the end. With such a structure, even if stress strain concentrates on the barrier metal portion, the stress can be gradually relaxed upward. Therefore, the reliability against peeling of the barrier metal portion is improved.

However, the known structure described above sufficiently exerts its effect when the barrier metal is used alone, but in order to increase the height of the bump electrode with respect to the fine bump electrode, the bump electrode is made of copper. When such a rigid pillar material metal is arranged, the residual stress inherent in the pillar material metal becomes particularly small and the bump electrode structure becomes apparent, causing a problem of bump electrode destruction due to peeling of the barrier metal.

In any case, the conventional techniques have proposed means for reducing the stress strain applied to the bump electrodes for a semiconductor device having a relatively small number of I / O pins and a large bump electrode size. It has been effective to some extent. However, the bump electrode formed by the conventional technique on the bonding pad of the I / O pin which is miniaturized due to the high integration of the semiconductor device has a limit that the height of the bump electrode cannot be increased. The method of arranging the pillars is considered as one solution, and many proposals have been made.

However, in the method of arranging the pillar material in the bump electrode, since the rigid pillar metal is embedded in the soft solder metal, the height of the bump electrode can be increased, but the bump electrode is resistant to stress strain. There is a problem that the reliability life cannot be sufficiently improved with the problem that it cannot be freely deformed. Furthermore, as the miniaturization of bump electrodes progresses, the tensile stress of the copper pillars placed in the metal becomes
There was a problem that the bump electrode was broken before the flip chip mounting process.

On the other hand, in flip-chip mounting, since the heat generating surface of the semiconductor element faces the substrate, the amount of heat generated is likely to be accumulated in the semiconductor chip, and the accumulated amount of heat causes failure of the semiconductor element. In particular, when resin is sealed between the semiconductor element and the substrate, the effect of heat storage is significant. Therefore,
There has been proposed a bump having a structure in which a metal having excellent thermal conductivity such as Cu is centered and the surrounding is covered with solder.

The formation of such fine bumps with a high aspect ratio is not possible depending on the vapor deposition method using a metal mask whose alignment is difficult, the dipping method which is difficult to miniaturize, or the method using solder balls. Since it is possible, the method using the electroplating method has become the mainstream. In particular, when the aspect ratio is 1 or more and the ratio of the gap to the bump height accompanying miniaturization is equal to or more than the aspect ratio, it is impossible except using electroplating.

However, when the bumps have a high aspect ratio, the strain that cannot be absorbed is concentrated on the barrier metal portion, resulting in destruction of the barrier metal. Therefore, there is a method of enlarging the barrier metal, but miniaturization becomes difficult. Further, in order to use the electroplating method for bump formation, it is necessary to form a cathode metal for supplying a current on the main surface of the wafer, deposit the bump metal, and then selectively etch the bump metal portion. Since the cathode metal eventually becomes a barrier metal, a refractory metal (Ti, W, etc.) is often used.

However, as the barrier metal, it is common to use a noble metal electrochemically in order to prevent the mutual diffusion of the bonding pad and the bump metal material, and therefore selective etching becomes impossible. An etching resist must be formed. When the cathode metal is etched, if the solder forming the bump and the cathode metal can be selectively etched, naturally, it is not necessary to form a resist for etching.

If the bump metal does not have a high aspect ratio as in the conventional case, the resist can be formed by a known technique by devising the resist coating condition and the exposure condition. It was impossible in principle to use either the positive type or the negative type.

There is also a method of oxidizing one portion of the cathode metal and etching without using a resist, but it is difficult to selectively oxidize a fine portion. In particular,
In order to obtain fine wiring with a high aspect ratio, it is not necessary to form a resist because an etching method that utilizes the rate ratio of metal dissolution in an etching solution without forming an oxide film is not used. is there.

As shown in FIG. 73 (a), when a positive resist is used, the resist film in the portion where the resist is dissolved is thick, so that sufficient exposure must be performed. There is a problem that the broken line resist shown in FIG. 73A is formed and the metal to be covered is exposed.

On the other hand, as shown in FIG. 73 (b), when a negative type resist is used, it is necessary to coat the resist up to the side surface of the protruding metal, and therefore a mask size pattern smaller than the gap size must be used. However, also in this case, there is a problem that the resist is formed and the metal to be covered is exposed as shown by the broken line in FIG. 73 (b).

If a resist film having a low viscosity is used,
There is a problem that the cathode metal portion can be covered, but the side surface portion of the protruding metal cannot be covered.

In any case, in the conventional methods, in order to reduce the stress applied to the bumps and improve the reliability,
Although resin was injected or the bump shape was made into a staggered shape, there was a problem that the process became complicated and the cost increased, resulting in insufficient connection. Therefore, a structure has been proposed in which the periphery is covered with solder around the Cu pillar material, but it is difficult to control the shape of the bumps.
There was a problem that the drawing strength was weak. Further, in the electroplating method required for forming bumps, the cathode metal etching becomes a problem with the miniaturization. Further, with the miniaturization of bumps, it has become necessary to relax the stress in the barrier metal portion.

[0055]

As described above, in the flip-chip mounting in which the bump electrodes formed on the semiconductor device are interconnected with the electrode pads of the circuit wiring board, the stress caused by the mismatch of the coefficient of thermal expansion is The strain concentrates on the bump electrodes, causing the bump electrodes to break.

Therefore, many methods have been proposed so far in order to prevent the destruction of the bump electrode portion and improve the connection reliability life. For example, (1) A method of reducing the distance from the center point of the semiconductor device to the center point of the bump electrode. (2) A method in which the circuit wiring board is made of silicon or AlN so that the coefficient of thermal expansion is similar to that of the semiconductor device. (3) A method of reducing the temperature difference by improving heat dissipation to reduce the amount of heat generated in the semiconductor device and the circuit wiring board. (4) A method of filling the gap between the main surface of the semiconductor device on which the bump electrodes are formed and the circuit wiring board with an ultraviolet curable resin or a room temperature curable resin. (5) A method of making the bump electrode structure strong against stress distortion.

In particular, regarding the bump electrode structure, the bump electrode shape, which is usually formed in a drum shape, is controlled to form a staggered type, and the combination of the melting points of the solders forming the bump electrodes is appropriately set. Has proposed a structure that realizes a strong bump structure against stress strain, and a method of relaxing the stress strain applied to the bump by suppressing the solder composition within a limited range, and a certain effect has been recognized. .

However, the bump structure described above requires a bump height of at least a certain level or more, and if the bump electrode height is extremely low, even if the bump structure is optimized, there is a limit in improving the reliability life. was there. Therefore, when a bump electrode having a small bump electrode diameter is formed on a bonding pad having a finer I / O pitch with the recent higher integration of semiconductor devices, it is inevitable that the bump electrode of the conventional technique is used. There is a problem that the height cannot be increased and it becomes impossible to form a bump electrode having a high height.

That is, in spite of the miniaturization of the bump diameter with the recent high integration of semiconductor devices, in the conventional technique,
The bump height could not be increased. In particular, when flip chip mounting is performed on a circuit wiring board having a remarkably different coefficient of thermal expansion such as on a resin substrate, the bump electrode itself needs to be formed in spite of the extremely high bump height required. There was a limit.

As one of the methods for increasing the bump height,
Although a method of providing bump electrodes in multiple stages has been proposed, it was a method that still has problems from the viewpoint of process and manufacturing cost.

Further, there has been proposed a method of increasing the height of the bump electrode by disposing a refractory metal composed of copper or the like inside the bump electrode. There is a limit to conversion. Also, if a metal such as copper is placed to make the connection a strong structure, the solder of the soft metal that covers the periphery of the copper will not be easily deformed, and the bump height can be increased, but on the contrary, reliability will be improved. There was a problem that the life was not improved.

Further, with the miniaturization of the bump electrodes, the stress inside the bump electrodes on the semiconductor chip before the flip chip mounting process also becomes a problem. That is, when the bump electrode size is relatively large, stress relaxation can be effectively performed by optimizing the material composition or shape of the barrier metal metal layer, but the bump electrode size is smaller than that of the I / O pin. If the refractory metal becomes smaller with the increase in the thickness, or if a refractory metal is present inside the bump electrode in order to increase the height, peeling of the barrier metal due to tensile stress becomes a problem.

In any case, the methods proposed so far have been effective in the case where a limited bump electrode size or a circuit wiring board is used within a certain range. If there is a demand for finer bumps and higher bump heights, there was a limit.

Further, when a semiconductor device having bumps formed on the bonding pads is mounted, the number of pins of the semiconductor device increases, which makes it difficult to perform the flip-chip mounting alignment and causes thermal expansion of the substrate and the semiconductor element. There has been a problem that the thermal stress due to the coefficient causes breakage at the bump portion. On the other hand, a structure that relieves the stress applied to the bumps is used. However, even in this case, a connection failure may occur even though strict control is required in the bump manufacturing, and this is not always a sufficient method. Was not.

Therefore, a method of increasing the bump height to improve reliability has been proposed, and an electroplating method is used for forming the bump. If the bump height is high, bump formation cannot be performed by the conventional vapor deposition method or dip method. Further, a method of arranging a columnar material such as Cu in the bump in consideration of heat dissipation has been proposed, but there is a problem that it is difficult to control the bump shape and the pulling strength becomes insufficient. The etching of the cathode metal required for electroplating is not problematic if selective etching with the bump metal is possible, but if the bump structure is made excellent in heat dissipation in consideration of heat dissipation, selective etching becomes impossible.

Therefore, it is required to cover the bump metal with the resist for etching, but it has been impossible to cover the side surface with the resist on the protruding metal having a high aspect ratio by the conventional method. When the bumps are further miniaturized, the stress at the barrier metal portion becomes a problem.

The present invention has been made in view of the above problems, and has a bump electrode structure for relaxing the stress concentrated on the bump electrode before the flip chip mounting process to prevent the bump electrode from breaking, and a bump electrode structure after the flip chip mounting process. It is an object of the present invention to provide a semiconductor device for realizing a bump structure for improving the fatigue reliability life due to a temperature cycle by an easy method for the mounting structure and the mounting structure thereof.

[0068]

The present invention (Claim 1) includes:
A metal thin film formed on a bonding pad of a semiconductor chip; and a bump electrode formed on the metal thin film and formed of a first metal layer and a second metal layer so as to project therefrom. The layer is 10 ⁻⁴ to 40% by weight of carbon,
There is provided a semiconductor device characterized by containing 10 ⁻⁴ to 30% by weight of sulfur and 10 ⁻⁴ to 10% by weight of oxygen.

Further, according to the present invention (claim 2), a metal thin film formed on a bonding pad of a semiconductor chip, and a first metal layer and a second metal layer formed so as to project on the metal thin film. A mounting structure in which a semiconductor device having a bump electrode made of is mounted on an electrode pad of a circuit wiring board by flip-chip mounting, wherein the first metal layer and the electrode pad are provided via the second metal layer. Connected to each other, and a portion of the second metal layer between the first metal layer and the electrode pad has a different density from other portions of the second metal layer. A semiconductor device mounting structure is provided.

Further, according to the present invention (claim 3), a metal thin film formed on a bonding pad of a semiconductor chip, and a first metal layer and a second metal layer formed so as to project on the metal thin film. A mounting structure in which a semiconductor device having a bump electrode made of is mounted on an electrode pad of a circuit wiring board by flip-chip mounting, wherein the first metal layer is covered with the second metal layer, The second metal layer is the second
A semiconductor device mounting structure characterized in that the semiconductor device mounting structure is connected to the electrode pad through a third metal layer different from the metal layer.

Furthermore, the present invention (claim 4) provides a metal thin film formed on a bonding pad of a semiconductor chip, a first metal layer and a second metal formed so as to project on the metal thin film. A mounting structure in which a semiconductor device having a bump electrode composed of a layer is flip-chip mounted on an electrode pad of a circuit wiring board, wherein the first metal layer and the electrode pad are the second metal layer. Connected through
The semiconductor device mounting structure is characterized in that the first metal layer has an inverted trapezoidal shape and the electrode pad has a thickness of 20 μm or more.

The present invention also includes the following aspects.

That is, according to the present invention, in order to increase the bump height of the bump electrode structure formed on the semiconductor chip to be flip-chip mounted, material properties such as melting point, thermal conductivity and Young's modulus are formed. By disposing different metal materials as bump metals in the bump electrode, setting the composition of the metal material forming the bump electrode within a certain range, and setting the structure of the mounting structure to a certain structure, It proposes a method of relaxing the applied stress strain.

The present invention also proposes a structure for alleviating the stress strain inherent in the bump electrode formed on the semiconductor chip before the step of flip-chip mounting the semiconductor device.

In particular, in the present invention, the melting point, thermal conductivity, and
In a semiconductor device having a bump electrode in which metal groups having different material properties such as Young's modulus are laminated in at least a two-layer structure, on a first metal group formed on a thin film metal,
Metals having different physical properties are continuously formed, and the first and second metal groups each have an inverted trapezoidal shape with respect to the thin film metal, and the second metal group is a metal of the first metal group. A structure is provided that is characterized by being larger than a volume.

The first metal group is composed of at least one of copper, gold and alloys thereof, and has a concentration range of 40 wt% or less of carbon and 30 wt% or less of sulfur in the metal group. In this case, the stress relaxation effect is more exerted.

Further, the second metal group continuously formed on the first metal group is a solder alloy composed of Pb-Sn,
It is composed of at least one metal of tin, lead, indium, gallium, and germanium, and when at least one element of carbon, sulfur, or oxygen is dispersed in these metals, the effect is further improved.

The first metal group is formed to have a dimension smaller than the width dimension of the thin film metal on the thin metal layer formed to be larger than the width dimension of the bonding pad, and the aspect ratio is 0. When it is set within the range of 0.01 to 200 or less, a preferable structure may be obtained.

Further, in the present invention, the thin film metal forming the barrier metal of the bump electrode is formed of at least a two-layer structure of a metal group having at least one of material properties such as melting point, thermal conductivity and Young's modulus different from each other. Also provided is a mounting structure in which a semiconductor chip having a bump electrode formed as described above is flip-chip mounted, in which the first metal group has an inverted trapezoidal shape with respect to the thin film metal. First
A second metal having a lower density than the surroundings of the first metal group, or a third metal having a different melting point, thermal conductivity, or Young's modulus between at least a part of the metal group of the first metal group and the electrode pad of the circuit wiring board. This is characterized in that the metal group of is arranged.

Further, when the first metal group is thicker than the electrode metal thickness arranged on the wiring board or on the thin film metal having a size larger than the opening size of the bonding pad, a thin film metal is formed. If the bump is formed to have a size smaller than the width of the bump, a good bump structure may be obtained.

When resin is filled and sealed in the gap between the semiconductor device and the circuit wiring board, the stress applied to the bump electrode is further alleviated, and the aspect ratio shape of the first metal group is 0.01 to 200. When set within the range,
More effective.

The gap portion formed between the first metal group and the electrode of the circuit wiring board is either the structure having the largest bump electrode diameter or the structure having the smallest bump electrode diameter. By arranging a metal having the lowest melting point, a metal having a high Young's modulus, or an alloy thereof in this gap portion, and optimizing the relationship between the size of the barrier metal and the size of the bump electrode, The structure can be either drum-shaped or staggered.

The mounting structure according to the present invention has a structure in which the circuit wiring board has a coefficient of thermal expansion different from that of the semiconductor device by about one digit, for example, when flip-chip mounting is performed on a glass epoxy substrate, the unevenness of the substrate can be absorbed. As a result, it becomes a particularly effective method for improving reliability, and its effect is very large as compared with the conventional method.

[0084]

According to the present invention, since the bump electrode structure formed on the semiconductor chip before flip-chip mounting the semiconductor device has an inverted trapezoidal shape, the bump electrode for forming a bump electrode with a high height is formed. Even if the volume of the metal forming the electrode is increased, the adhesion area to the thin film metal can be reduced. Therefore, even if the tensile stress generated in the bump is large, the tensile stress on the thin film metal can be relaxed.

When the tensile stress is large, the stress generated in the thin film metal can be further alleviated by making the size of the inverted trapezoidal bump electrode to be formed smaller than the opening size of the thin film metal group. Furthermore, by setting the aspect ratio of the first metal group within the range of 0.01 to 200, the reliability life is improved more than in the case of using the conventional technique.

Further, by dispersing 40 wt% of carbon and 30 wt% or less of sulfur in copper constituting the first metal group to be arranged, the tensile stress generated when carbon and sulfur are not dispersed is compressed. It is possible to prevent peeling of the thin film metal.

The same effect can be obtained by converting the compressive stress into the tensile stress when 40 wt% or less of carbon, 30 wt% or less of sulfur, and 10 wt% or less of oxygen are dispersed in the solder forming the second metal group. The effect of the stress is that even if the compressive stress remains in the first metal group, the stress remaining in the bump electrode as a whole can be converted into a tensile stress. As a result, the stress generated in the bump electrode becomes a tensile stress. Barrier metal peeling can be prevented.

In this case, the lower limit of the content of carbon, sulfur and oxygen is preferably 10 ^-4 % by weight.

Further, according to the present invention, since the first metal group having a high melting point and a low thermal conductivity is arranged in order to increase the bump height in the flip chip mounting process,
It is possible to prevent damage due to stress strain applied to the bump.
By increasing the bump height, the gap amount between the semiconductor device and the circuit wiring board can be increased, so that the stress generated in the resin can be reduced when the sealing resin is arranged in the gap. Reliability is improved, and as a result, stress strain applied to the bump can be reduced.

Therefore, as a matter of course, the stress of the bump electrode itself can be relaxed. In addition, the first with high thermal conductivity
By disposing the metal in the bump electrode, the heat storage amount of the semiconductor chip can be reduced, and even if the difference in the thermal expansion coefficient between the semiconductor device and the circuit wiring board is large, the heat generation amount can be reduced. As a result, the displacement amount can be reduced. Further, since the shape of the first metal group has an inverted trapezoidal shape, it is possible to improve the drawing strength and also to reduce the portion where a stress difference with the thin film metal occurs, thus reducing the trapezoidal shape. It is possible to prevent the bump electrode from being destroyed, as compared with the first metal group which is included.

Furthermore, between the first metal group and the circuit wiring board, at least a part of the third metal or the first metal group, which has a lower melting point or a lower Young's modulus than the second metal group. When the second metal group having a physical property having a lower density than the second metal group covering the surroundings is arranged, it is possible to solve the problem that the bump electrode is broken in the portion where the stress is most concentrated. Since the bump shape can be made into a drum shape or a staggered shape with the gap portion as the center, the reliability can be improved. Since the shape of this bump electrode is specified by the barrier metal size, it is possible to easily realize a drum type or a stagger type by increasing or decreasing the solder amount compared to the cylindrical volume considering the barrier metal size. become.

The first metal group is formed on the thin film metal larger than the bonding pad size so as to have a width dimension smaller than the thin film metal group, and the aspect ratio is 0.01.
When it is set within the range of up to 200, the reliability life can be improved as compared with the conventional flip-chip mounting structure using the bump structure by the technique that does not consider the dimensions.

Further, in the present invention, since the gap is provided between the first metal group and the electrode pad of the circuit wiring board, the circuit wiring board has large irregularities, for example, the copper clad wiring is formed on the glass epoxy substrate. In such a case, since the unevenness can be absorbed and the semiconductor device can be flip-chip mounted in parallel with the circuit wiring board, the reliability can be improved.

Carbon 4 is contained in the first metal group to be arranged.
When 0 wt% or less and sulfur of 30 wt% or less are dispersed,
As compared with the case where carbon or sulfur is not dispersed, the tensile stress can be relaxed sufficiently and peeling of the thin film metal can be prevented.

Furthermore, the second metal element disposed in the first metal group
The metal group includes at least 40 wt% of carbon and 3 sulfur.
When either 0 wt% or less or 10 wt% or less oxygen is dispersed, the tensile stress generated when the element is not dispersed can be converted into a compressive stress, and the residual tensile stress in the first metal group can be adjusted. As a result, the stress applied to the bumps can be reduced to zero.

The semiconductor mounting body having the bump electrode structure described above is formed by the conventional technique when the semiconductor device is flip-chip mounted on, for example, a glass epoxy substrate made of a resin substrate having a remarkably different thermal expansion coefficient. Compared with the flip-chip mounting structure, the effect is remarkably large.

[0097]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor device mounting structure according to a first embodiment of the present invention, FIG. 2 shows a semiconductor device mounting structure according to a second embodiment of the present invention, and FIG. 4 shows a semiconductor device mounting structure according to a third embodiment of the present invention, and FIG. 4 shows a semiconductor device mounting structure according to a fourth embodiment of the present invention. In the drawings, reference numeral 1 is a semiconductor chip,
Reference numeral 2 is a circuit wiring board, 3 is a passivation film, 4 is a bonding pad, 5 is a thin film metal to be a barrier metal portion, 6 is a first metal, 7 is a second metal, and 8 is an electrode pad of the circuit wiring board. Metal, 9 is a solder resist or a protective film of a circuit wiring board, 10 is a wiring metal and an electrode metal of the circuit wiring board, 11 is an electrode barrier metal of the circuit wiring board, and 12 is a gap between the semiconductor chip and the circuit wiring board. The respective sealing resins are shown.

In the semiconductor device mounting structure according to the first embodiment of the present invention, as shown in FIG. 1, the periphery of a first metal group having an inverted trapezoidal shape made of, for example, copper is made of solder. Or a completely different metal between the first metal group and the electrode pad of the circuit wiring board, which is different in density from the solder that covers the periphery of the first metal group. A third metal group having physical properties is arranged.
At this time, the electrode metal 10 of the circuit wiring board has a trapezoidal shape with respect to the circuit wiring board 2. At this time, the electrode metal 10 also serves as an electrode pad.

Further, in the semiconductor device mounting structure according to the second embodiment of the present invention, as shown in FIG. 2, the gap between the semiconductor chip and the circuit wiring board is filled with a thermosetting resin or a thermoplastic resin. There is.

Further, in the semiconductor device according to the third embodiment of the present invention, as shown in FIG. 3, the electrode metal structure of the circuit wiring board has an inverted trapezoidal shape unlike the trapezoidal shape shown in FIG. Cage,
It is formed on the electrode pad 8 via a barrier metal 11.

The semiconductor device mounting structure according to the fourth embodiment of the present invention is different from that of FIG. 4 in comparison with the mounting structure shown in FIG.
As shown in, a thermosetting resin or a thermoplastic resin 12 is filled between the semiconductor chip and the circuit wiring board.

Furthermore, in the semiconductor device according to the fifth embodiment of the present invention, as shown in FIG. 5, the first metal 6 has an inverted trapezoidal shape with respect to the semiconductor device and has a melting point. At least one of the following: thermal conductivity, Young's modulus
Metal 7 is continuously formed in a larger volume than the first metal 6. The portion of the first metal 6 in contact with the thin film metal 5 is larger than the opening size of the bonding pad 4 and smaller than the size of the thin film metal 5, and its thickness is larger than the thickness of the barrier metal thin film metal 5. It is a thing.

Although copper is used for the first metal group in this embodiment, gold or an alloy containing them may be used. This first metal group contains 40 wt% or less of carbon and 30 wt% or less of sulfur, and has an aspect ratio of 0.
It is set in the range of 01 to 200.

Therefore, the semiconductor device of the present invention has the features according to the gist of the present invention even in the structures shown in FIGS. 6, 7, 8, 9, and 10.

Details will be shown below, but FIG. 6, FIG. 7, FIG.
The outline of the structure shown in FIGS. 9 and 10 is as follows.
That is, FIG. 6 is a view showing a state in which the bump electrode on the semiconductor device shown in FIG. 5, FIG. 7, FIG. 8, FIG. 9 or FIG. 10 is reflowed, and FIG. 7 is a side view of the first metal group. FIG. 8 is a diagram showing a state in which a second metal group is continuously formed. FIG. 8 shows a case where, when reflow melting is performed in a later step on the first metal group, for example, tin and lead to be a second metal group are sequentially laminated. FIG. 9 is a view showing a state in which the first metal group is formed, and FIG. 9 is a view showing a state in which a metal layer to be a second metal group in a later step is sequentially laminated around the first metal group.
FIG. 9 is a diagram showing a state in which a metal layer of, for example, indium or the like is further laminated in the structure shown in FIG. 8 if necessary.

Each embodiment will be described in detail below.

Example 1 A semiconductor device having bump electrodes according to the present invention is shown in FIG.
And the steps shown in FIG. First, the bonding pad 4 is formed on the semiconductor chip 1 and, for example, PSG (phosphorus.
For example, Cu / Ti is vapor-deposited on the entire surface of a semiconductor device silicon wafer on which a passivation film 3 made of silica / glass) or SiN (silicon nitride) is formed, and a cathode metal for forming bumps by electroplating. 22 is formed.

This Cu / Ti finally becomes a barrier metal of the bump electrode by forming a bump electrode by electroplating and then etching a necessary portion. Therefore, the thin film metal need not be limited to Cu / Ti, but Cu
/ Ti. Similarly, the wafer does not have to be a silicon wafer, but in the present embodiment, silicon is used for the sake of explanation (FIG. 11A).

Next, a thick film resist AZ4903 (manufactured by Hoechst Japan Co., Ltd.) was spin-coated to a film thickness of 100 μm.
A resist 23 having a thickness of m is formed, and exposed / developed to 40 μm.
An opening portion of 50 μm having a size of 5 μm on each side is larger than that of the bonding pad 4 having an opening size of m square.
Form on u / Ti. Using the above method, the angle control is performed so that the resist film 23 and Cu / Ti are less than 90 °.

Here, in the embodiment described in the present invention, the angle with the metal thin film is 80 °. The exposure is performed by irradiating a sufficient amount of exposure energy even if the resist is thick, and the development is performed by an AZ400K developer (manufactured by Hoechst Japan). The angle adjustment of the portion of the resist surface in contact with the thin film metal is controlled by adjusting the exposure energy, the distance between the resist surface and the glass mask, and the concentration of the developing solution. For details, see 13th IEMT Symp. pp2
88, so detailed description will be omitted here (FIG. 11B).

Thus, the silicon wafer in which the resist film 23 is opened with an angle of 80 ° with a size smaller than that of the bonding pad 4 in the portion corresponding to the bonding pad 4 is treated with a copper sulfate plating solution containing the following mixed solution. Immerse and gently stir at a bath temperature of 25 ° C. with Cu / Ti as a cathode and a phosphorus-containing (0.03 to 0.08 wt%) high-purity copper plate as an anode at a current density of 1 to 5 (A / dm ² ). Meanwhile, copper 6 is electroplated to a thickness of 35 μm.

It is not always necessary to plate to a thickness of 35 μm, and there is no problem if it is smaller than the thickness of the second metal group due to the correlation with the thickness of the second metal group.

Copper Sulfate Pentahydrate 2 ounces / gallon Sulfuric acid 30 ounces / gallon Hydrochloric acid 10 ppm Thioxanthate-s-propanesulfonic acid (or thioxanthatesulfonic acid) 20 ppm Polyethylene glycol (molecular weight: 400,000) 40 ppm Reaction product of polyethyleneimine (molecular weight: 600) with benzyl chloride 2 ppm or copper sulfate pentahydrate 30 oz / gallon sulfuric acid 8 oz / gallon hydrochloric acid 30 ppm dithiocarbamate-s-propanesulfonic acid 30 ppm polypropylene glycol ( Molecular weight: 700) 10 ppm Reaction product of polyethyleneimine with allyl bromide or dimethylsulfate 0.3 ppm Then, the plating bath was changed to the sulfonic acid solder plating solution described in detail below, and the case of electrolytic copper plating was used. same C to
Electroplating is performed using u / Ti as a cathode and a high-purity eutectic solder plate corresponding to the plating solution as an anode. The current density is 1 to 4 (A / dm ² ), and the composition of the solder composition (Pb / Sn) is almost equal to the eutectic composition while slightly stirring at a bath temperature of 25 ° C., or slightly on the Pb side or the Sn side. The solder alloy 7 having the transferred composition is deposited to 65 μm (FIG. 11 (c)).

Composition of Sulfonic Acid Solder Plating Solution Tin ion (Sn ²⁺ ) 12 vol% Lead ion (Pb ²⁺ ) 30 vol% Aliphatic sulfonic acid 41 vol% Nonionic surfactant 5 vol% Cationic surfactant 5 vol% isopropyl alcohol 7 vol% Copper 6 having different melting points, thermal conductivity and Young's modulus
The solder alloy 7 is continuously plated on the bonding pad 4 in an inverted trapezoidal shape. Next, the resist AZ4903 on the wafer is removed using acetone (FIG. 11 (d)).

Next, for example, an image reversal type resist AZ is formed on the wafer on which the Cu / Ti bump electrodes are formed.
A solution of 5214E (manufactured by Hoechst Japan Co., Ltd.) whose viscosity has been adjusted is spin-coated to form a resist film 25.
The viscosity is adjusted to a high viscosity in order to perform the etching accurately even when the plated metal is thick. At this time, the resist film 25 has a shape corresponding to the bump metal on the surface, and has a thickness of 10 μm on the bump metal and 55 μm on the portion of the cathode metal 22 made of Cu / Ti on which the bump metal is not formed. It had a film thickness (FIG. 11 (e)).

Next, a glass mask 26 having an opening pattern 27 having an opening dimension of 2 μm larger than that of the bump electrode 50 μm and a side of 54 μm is aligned with a required position and then exposed (FIG. 11 (f)). The exposure is performed with an exposure energy of 2000 mJ, and the wafer is baked on a hot plate at 150 ° C. after the exposure. Next, the baked wafer is immersed in a developing solution for development.

By performing the above steps, the resist film 25 as shown in FIG. 12A is selectively formed only on the bump electrodes. At this time, the resist film 25 covering the first metal group had a width of 55 μm in the lower portion in contact with the thin film metal and a width of 75 μm in the upper portion.

In this embodiment, the image reversal type resist is used. However, in the aspect ratio shape in the range where the resist can be formed up to the side surface portions of the first and second metal groups, the normal positive type resist OFPR- is used. It is also possible to use 800 (manufactured by Tokyo Ohka) or negative resist OMR-85 (manufactured by Tokyo Ohka).

Then, after a necessary portion of copper is removed by etching with a mixed solution composed of ammonium persulfate, sulfuric acid and ethanol or a mixed solution composed of citric acid, hydrogen peroxide solution and a surfactant, ammonia and ethylenediaminetetraacetic acid are used. , A necessary portion of titanium is removed by etching with a mixed solution composed of hydrogen peroxide solution, and finally the etching resist 25 coated is dissolved and removed by using acetone (FIG. 12B).

By performing the above steps, the inverted trapezoidal first and second metal groups are formed as shown in FIG. 12B. At this time, the cathode metal Cu /
Ti has a trapezoidal structure with respect to the passivation film on the semiconductor device, and as a result, the barrier metal also has a strong structure against stress.

Example 2 FIG. 11 on which the resist film described in Example 1 was formed.
In (b), a first metal group made of copper 6 which constitutes a part of the bump electrode is deposited under an ultraviolet-free light by using an electroplating method. That is, using the copper plating solution and conditions described in Example 1, 100 μm of copper is deposited under UV-free light.
Then, using a glass mask having a pattern in which a copper portion whose one side is 5 μm larger than the formed pattern filled with 50 μm square copper is covered with a resist film, 60 μm
An opening centered on m square copper is formed. The exposure and development conditions for the resist film are realized under the conditions described in Example 1.

Then, Example 1 was applied to the formed opening.
Plating is performed using the solder plating solution described in 1) under the same conditions as described in Example 1. The solder plating at this time does not necessarily need to be performed under non-ultraviolet light.

In this way, the etching of the cathode metal of the bump electrode on which the copper 6 and the solder 7 are formed is performed by using the same means as the steps of FIG. The semiconductor device having the formed bump electrode has a structure shown in FIG.

Example 3 FIG. 11 on which the resist film described in Example 1 was formed.
In (b), copper forming the inside of the bump electrode is electroplated by using the same plating solution and conditions as described in Example 1 to form a copper layer 6 having a thickness of 35 μm.

Next, the plating solution was changed to the tin plating solution described below, and Cu / Cu /
Ti is used as a cathode and, for example, a high-purity tin plate corresponding to the electroplating solution is used as an anode, and the current density is 1 to 10 (A / d).
m ² ) is applied and 60 μm-thick tin 7 a is continuously plated on the copper 6 at a bath temperature of 25 ° C. with gentle stirring.

The composition of the tin plating solution is as follows.

Stannous sulphate 55 g / l Sulfuric acid 70 g / l Cresol sulphonic acid 100 g / l Beta naphthol 1 g / l Gelatin 2 g / l or stannous sulphate 30 g / l Phenol sulphonic acid 25 g / l Polyoxyethylene alkylamine 2 g / l Further, the plating solution was changed to the lead plating solution described below, and Cu was added in the same manner as in the case of electrolytic copper plating and electrolytic tin plating.
/ Ti as a cathode and a high-purity lead plate corresponding to a plating solution as an anode, a current density of 1 to 3 (A / dm ² ) is applied, and while stirring gently at a bath temperature of 25 ° C., 5 μm
m lead 7b is continuously plated on tin.

Lead sulfamate 80 g / l Gelatin 0.15 g / l Glue 0.40 g / l Thus, the etching of the cathode metal of the bump electrode having the copper 6, tin 7a and lead 7b formed thereon was carried out in Example 1. It is performed by the same means as the steps shown in FIG. The semiconductor device having the bump electrode formed in this way is
The structure is as shown in FIG.

This bump electrode contains tin and lead at a temperature of 350.
When melted and reflowed at 0 ° C., a solder alloy 7 having a composition of Pb / Sn = 5/95 is formed.

In the present embodiment, for the sake of explanation, the cathode metal serving as a barrier metal is Cu / Ti, and the etching of copper is performed by a mixed solution of ammonium persulfate, sulfuric acid, ethanol or citric acid, hydrogen peroxide solution, The etching was performed with a mixed solution composed of a surfactant, and then a necessary portion of titanium was etched with a mixed solution composed of ammonia, ethylenediaminetetraacetic acid, and hydrogen peroxide solution. For example, nickel was used as a part of the barrier metal. In this case, selective etching with tin becomes impossible, and when solder is formed on the uppermost part of the bump electrode, the nickel etching solution dissolves tin and the solder composition shifts from the desired value. become.

The nickel etching solution at this time is a mixed solution composed of copper sulfate pentahydrate, hydrochloric acid and methanol. However, for example, when lead is used as the uppermost layer, lead is less likely to be dissolved by the nickel etching solution. Therefore, when a metal layer is used for the barrier metal portion as needed, the order of forming the second metal group to be formed is not necessarily limited, and the order can be changed as necessary.

Example 4 FIG. 11 in which the resist film 23 described in Example 1 was formed.
In (b), a first metal group made of copper 6 which constitutes a part of the bump electrode is deposited to a thickness of 100 μm under non-ultraviolet light using an electroplating method. Subsequently, formed 50
5 μm on one side than the pattern filled with copper 6 of μm square
An opening centered on 60 μm square copper having a pattern larger than m is formed in the resist 23. Resist film 23
Can be patterned under the exposure and development conditions described in Example 1.

Next, using the tin plating solution and plating conditions described in Example 3, a 10 μm thick tin film 7a is deposited by electroplating in the formed opening under the non-ultraviolet light. Further, the same procedure is repeated to repeat the electrotin plating film 7
An opening is formed in the resist film 23 around a and the lead 7b is filled in the opening using the lead plating solution and conditions described in the third embodiment. The subsequent etching process of the cathode metal is similar to the processes of FIG. 11 (e) and the subsequent processes described in the first embodiment.

The bump electrode formed by using the above method has a structure as shown in FIG. In this structure, the tin-plated film 7a is completely covered with the lead-plated film 7b. Therefore, for example, when the nickel is used as the barrier metal, the tin film has a resistance to etching liquid with respect to the nickel etching liquid in comparison with the case of the third embodiment. Then it will be much improved.

Although the tin 7a and the lead 7b are formed independently, the effect does not change even if they are collectively formed as a solder alloy. Further, the formation of the tin 7a and lead 7b coatings is not limited to the electroplating method. For example, after forming a necessary portion with a resist film, the tin 7a and lead 7b coatings may be formed by the known electroless plating method. good.

Example 5 FIG. 11 on which the resist film described in Example 1 was formed.
In (b), the copper 6 forming the inside of the bump electrode is deposited with the electrolytic copper plating film 6 having a thickness of 35 μm by using the same plating solution and conditions as those described in the first embodiment.

Then, the plating solution is changed to the tin plating solution described in Example 3, and the electrotin plating film 7a is plated to a thickness of 35 μm under the same conditions as those described in Example 3. Further, the plating bath is changed to the lead plating solution described in Example 3 to deposit the lead film 7b having a thickness of 5 μm.

Subsequently, indium, antimony, gallium, and germanium are successively deposited using, for example, the plating solution described below, and the bump electrode having the structure shown in FIG. 10 is obtained.

Indium: Current density 2 to 10 (A / dm ² ) Bath temperature 25 ° C. Indium sulfamate 105 g / l Sodium sulfamate 150 g / l Sulfamic acid 26 g / l Sodium chloride 45 g / l Dextrin 8 g / l Triethanolamine 2 g / l Antimony: Current density 2.5 (A / dm ² ) Bath temperature 55 ° C. Antimony trioxide 52 g / l Potassium citrate 150 g / l Citric acid 180 g / l Aloine 2 g / l Regarding β-naphthol 1 g / l clove oil 3 g / l gallium and germanium, a salt is formed and then solubilized, and then an additive containing carbon, sulfur and oxygen is added, or a dip method is used.

With respect to solder, tin, lead, indium, antimony, gallium, and germanium, it is not always necessary to stack all the metals, and a part of these metals may be combined and stacked. Therefore, the deposition method does not necessarily have to be electroplated for all metals. Therefore, it is needless to say that the metal films to be laminated do not have to be formed in the order described in this embodiment, and can be variously modified without departing from the gist of the present invention, for example, having a structure of tin / lead / tin / lead. is there.

In FIG. 10, the laminated film is shown by 7.

This example is based on US Pat. No. 5,130,77.
Although it appears to be similar to the structure described in 9,
Since the basic structure is an inverted trapezoidal shape, the structure is completely different and is not a known structure.

Example 6 A semiconductor device having bump electrodes shown in FIGS. 5, 7, 8, 9 and 10 is subjected to heating reflow in a nitrogen atmosphere at, for example, 250 ° C. to obtain the structure shown in FIG. The bump electrode has a continuous structure as shown in FIG.

In the present embodiment, since the reflow is performed within a temperature range higher than the melting point of the first metal group 6 made of copper and lower than the melting point of the second metal group 7, FIG. The second metal group 7 in which different metal films shown in FIGS. 7, 8, 9, and 10 are laminated has an integral structure.

Example 7 The following results were obtained when the performance of the semiconductor device having the bump electrode according to the present invention was evaluated.

FIG. 13 is a graph showing the relationship between the ratio V ₁ / V ₂ of the volume V ₁ of the first metal group and the volume V ₂ of the second metal group, and the stress remaining in the bump electrodes. In this embodiment, copper is used for the first metal group 6 and eutectic solder is used for the second metal group 7. If the volume of the second metal group 7 is smaller than that of the first metal group 6, V ₁ / V ₂ > 1, and if the volume of the second metal group 7 is larger than that of the first metal group 6, V
₁ / V ₂ <1.

As shown in FIG. 13, when the volume of the first metal group 6 is smaller than the volume of the second metal group 7, the tensile stress is inherent in the bump electrode. 6
Is larger than the volume of the second metal group 7, V ₁
The compressive stress is inherent in the bump electrode by reversing at the boundary of / V ₂ = 1. Further, the stress value increases as the width dimension of the bonding pad forming the bump electrode increases.

From this result, since the stress value of the second metal group 7 is larger than that of the first metal group 6, the residual stress of the entire bump electrode is dominant in the metal mainly forming the bump electrode. I understand that it is a target.

FIG. 14 is a graph showing the residual stress (tensile stress) in the bump electrode with respect to the ratio (l ₃ / L ₁ ) of the upper dimension (L ₁ ) and the lower dimension (l ₃ ) of the first metal group 6. Is. A large value of this residual stress causes destruction of the barrier metal, so a smaller value is preferable. This is the result when copper is used for the first metal group 6 and eutectic solder is used for the second metal group 7, as in the case of FIG.

When l ₃ / L ₁ <1, inverted trapezoidal shape, l ₃ /
When L ₁ > 1, it becomes trapezoidal. The residual stress in the bump electrode is small in the inverted trapezoidal shape, but sharply increases in the trapezoidal shape that exceeds l ₃ / L ₁ > 1. Therefore, it was found that the inverted trapezoidal shape of the first metal group 6 is suitable for the metal in the bump electrode. The evaluation according to this example is a result performed on the bump electrode having the structure of FIGS. 5 to 10, and the same result was obtained in any case.

FIG. 15 shows the stress (σf) remaining in the bump electrode and the high temperature and high humidity storage test (85 ° C.,
It is a result of obtaining a 50% defective rate (Nf ₅₀ ) when performing 5% RH. l ₁ is the width of the bonding pad,
l ₂ is the width dimension of the barrier metal, and l ₃ is the width dimension of the first metal group. Also in this case, copper was used for the first metal group and eutectic solder was used for the second metal group.

As is apparent from FIG. 15, σf is the smallest in FIGS. 15 (c) and 15 (d), and the reliability life is Nf _50.
Has been revealed to be large. 15 (a) and FIG.
In the structures shown in (b), FIG. 15 (e) and FIG. 15 (f), σf is large, Nf ₅₀ is small, and low reliability results are obtained. Therefore, as a factor parameter constituting the bump electrode, l ₂ > l ₁ > l ₃ or l ₂ > l ₃ > l ₁ is preferable, that is, the width dimension of the thin film metal is larger than the opening dimension of the bonding pad. It was revealed that the effect is exhibited when the width dimension of the first metal group is smaller than that of the thin film metal group. It has been revealed that the structure according to the present invention exerts more effect when the thickness of the first metal group is thicker than that of the thin film metal group.

FIG. 16 shows the aspect ratio (H
₃ is a graph showing the relationship between / l ₃ ) and the residual stress in the bump electrode. The height of the first metal group was H, and the lower width dimension of the first metal group was l ₃ . The first metal group is copper, and the second metal group is eutectic solder. As is clear from FIG. 16, the residual stress does not increase within the range of the aspect ratio of 0.01 to 200 and shows a substantially constant value, but it increases rapidly from the area exceeding 200. . Therefore, it is more preferable to set the aspect ratio of the first metal group within the range of 0.01 to 200.

Furthermore, when bumps are formed by using the methods described in Examples 1 to 6 of the present invention, an element having a concentration of 40 wt% carbon and 30 wt% sulfur or less in the first metal group is added to the solder alloy (Pb). / Sn).

As shown in FIG. 18, the residual stress of the metal according to the present embodiment in which carbon and sulfur are dispersed and arranged in a metal group composed of copper, for example, is found, and as a result, the concentration of carbon and sulfur increases. Accordingly, when the dispersion concentration is 0, the stress in the metal showing the compressive stress shifts to the tensile stress as the concentration of the dispersed element increases. Carbon concentration is 30wt%, sulfur is 20w
When it is about t% or less, the residual stress becomes a tensile stress. on the other hand,
As shown in FIG. 19, the electric conductivity tends to increase as the carbon and sulfur concentrations increase, but it shows the minimum value in the relatively low concentration region of carbon and sulfur, and the carbon concentration of 40 wt.
% Or less, and a sulfur concentration of 30 wt% or less, it is possible to obtain a value equivalent to that in the case where carbon and sulfur are not dispersed or a value exhibiting performance higher than that. This tendency is particularly remarkable when the carbon concentration is 4 wt% and the sulfur concentration is 3 wt% or less.

Comprehensively judging the results shown in FIG. 18 and FIG. 19 above, when dispersed in the first metal group composed of copper in the concentration range of 40 wt% carbon and 30 wt% sulfur or less, The residual stress in the bump electrode can be reduced, and the electrical conductivity, which is one of the characteristics required after flip-chip mounting, can be sufficiently reduced, and the overall reliability can be improved.

Also, when gold was used as the first metal group, similar results regarding residual stress were obtained in the same concentration range.
Furthermore, similar results were obtained with alloys containing copper or gold. Furthermore, as shown in FIG. 20, for example, residual stress in the alloy metal according to the present embodiment in which at least one element of carbon, sulfur and oxygen is dispersed and arranged in a eutectic solder alloy composed of Pb-Sn, for example. As a result, the residual stress shifts from the compressive stress to the tensile stress as the carbon, sulfur and oxygen concentrations increase.

Further, as shown in FIG. 21, it was revealed that the electric resistivity also increases with the increase of carbon, sulfur and oxygen concentrations, but conversely decreases in the low concentration region of the dispersive element. The tensile stress is shown when the carbon concentration is 40 wt%, the sulfur concentration is 30 wt%, and the oxygen concentration is 10 wt% or less.
This tendency is especially due to the carbon concentration of 4 wt% and the sulfur concentration of 3 wt.
%, When the oxygen concentration is 1 wt% or less, it is remarkable.

Therefore, comprehensively judging the results shown in FIGS. 20 and 21, in the second metal group composed of solder, 40 wt% or less of carbon, 30 wt% or less of sulfur,
When oxygen content of 10 wt% or less is included, the compressive residual stress can be reduced, and the electrical conductivity, which is one of the characteristics required after flip-chip mounting, can be sufficiently reduced to improve the reliability life. Will be possible.

FIG. 17 shows whether or not the residual stress decreases when at least one element selected from carbon, sulfur and oxygen is contained in the metals constituting the second metal group, for each combination of metals. The results of classification are shown below. As shown in FIG. 17, it was revealed that the residual stress was reduced except for the combination of some elements. Furthermore, when the residual stress is reduced by including carbon, sulfur and oxygen among the elements shown in the table, it is clear that the residual stress is reduced even when a plurality of metals are combined. It was The concentration range of the element in which the residual stress is reduced by combining these metal groups was 40 wt% or less of carbon, 30 wt% or less of sulfur, and 10 wt% or less of oxygen.

It has been known that when a metal is deposited by an electroplating method, residual stress is generated in the deposited metal film due to the amount of the additive to cause peeling of the deposited metal film. The stress applied to the base film by the stress generated therein and the stress value remaining due to the element concentration contained in the metal were not known facts. In the method of containing carbon and sulfur, a compound containing carbon and sulfur is brought into contact with the first metal group and the second metal group,
It is also possible to disperse by diffusion.

Therefore, in the semiconductor device having the bump electrodes formed on the semiconductor chip, even if the metal for increasing the bump height is arranged in the bump electrodes, the problem that the barrier metal peels off due to the residual stress does not occur. . Further, the pillar material in the bump electrode has a smaller volume than the surrounding metal and has an inverted trapezoidal shape with respect to the thin film metal, and the parameters constituting the bump electrode and the aspect ratio of the first metal group. Even if it is necessary to set the compression stress side in order to improve the electric conductivity because the ratio is optimized, the defects of thin film metal peeling due to the tensile stress can be reduced.

Example 8 A process of flip-chip mounting a semiconductor device having bump electrodes formed on a semiconductor chip by the above-described process on a circuit wiring board will be described below.

Using the flip chip bonder M8 (research device) having a half mirror, which is a known technique, the semiconductor device 1 having the bump electrodes 6 and 7 shown in FIG. 5 and the circuit wiring board 2 are aligned with each other. Then, the bump electrodes 6 and 7 of the semiconductor device 1 are brought into contact with the electrode pads 10 of the circuit wiring board 2. Electrode pad 10 of circuit wiring board 1
Has an inverted trapezoidal shape with respect to the circuit wiring board 2.

The bump electrodes 6 and 7 of the semiconductor device 1 and the electrode pad 10 of the circuit wiring board 2 for this alignment are
A flux of, for example, NS-30 (manufactured by Nippon Superior Co., Ltd.) is applied to one or both of them in order to facilitate melting of the solder. When performing flip-chip mounting, the circuit wiring board 2 is held on the stage of a flip-chip bonder having a heating mechanism and is higher than the melting point of the solder having a composition slightly deviated from the eutectic solder composition and lower than the melting point of copper. It is preheated to a temperature of 280 ° C.

This flip-chip mounted semiconductor device 1
Bump electrodes 6 and 7 of 126 pins are formed on the circuit wiring board 2, and 126 connection electrode pads 10 are formed on the circuit wiring substrate 2 at the plane symmetrical positions of the bump electrodes 6 and 7 of the semiconductor device 1. . 1.4m for circuit wiring board material
A glass epoxy resin material having a thickness of m is used (FIG. 22 (a)).

Furthermore, with the bump electrodes 6, 7 of the semiconductor device 1 and the electrode pads 10 of the circuit wiring board 2 in contact with each other,
The collet holding the semiconductor device 1 is heated in a nitrogen atmosphere to the same temperature as that of the stage on which the circuit wiring board 2 is mounted, 280 ° C., to melt the solder 7 forming the bump electrodes 6 and 7. 1 bump electrode 6,7
And the electrode pad 10 of the circuit wiring board 2 are electrically and mechanically connected. (FIG. 22B and FIG. 3) After performing the above steps, a thermosetting resin is inserted into the gap portion 29 between the circuit wiring board 2 and the semiconductor device 1 for sealing. This sealing step is performed while heating the resin at about 100 ° C. to reduce the viscosity of the injected resin and easily seal the resin in the minute gap between the circuit wiring board and the semiconductor device. By performing the above steps, the semiconductor device mounting structure having the structure shown in FIG. 4 can be realized. Incidentally, when the aspect ratio is extremely high and the width dimension of the copper pillar material is fine, copper will be dissolved in the solder, but there is no inconvenience to increase the bump electrode height, and in this case, , Copper will be dispersed in the solder.

Also in this case, the mechanical properties of the solder exhibit excellent physical properties with respect to stress and strain, and the reliability of the flip chip mounting structure is improved as a result.

Example 9 The semiconductor device 1 having the bump electrodes 6 and 7 having the structure shown in FIG. 5 is brought into contact with the circuit wiring board 2 by using the same apparatus and method as the method described in Example 8. (FIG. 23 (a)). Then, flip-chip mounting is performed by the same method as that described in the eighth embodiment. The sectional structure of the electrode pad 10 at this time is trapezoidal with respect to the circuit wiring board 2 (FIGS. 23B and 1).

Further, when the resin 12 is filled in the gaps of the flip-chip mounted semiconductor mounting structure, the structure shown in FIG. 2 can be realized. Further, the semiconductor device having the bump structure shown in FIG. 6 is brought into contact with the electrode pad 10 of the circuit wiring board 2 by using the same method as that of the eighth embodiment. At this time, the electrode pad 10 of the circuit wiring board 2 has an inverted trapezoidal shape (FIG. 24A).

When the semiconductor device 1 and the circuit wiring board 2 shown in FIG. 24A are reflowed to perform flip chip connection,
The structure shown in FIG. 24B can be realized, and when the resin is filled, the structure shown in FIG. 4 is obtained.

Similarly, when the bump electrode structure shown in FIG. 6 is brought into contact with the trapezoidal electrode pad 10, FIG.
The structure shown in FIG. 25A and the structure shown in FIG. 25B are obtained by reflowing. Further, when the resin is filled, the structure shown in FIG. 2 is obtained.

Example 10 A circuit wiring board on which a semiconductor device is flip-chip mounted is manufactured according to the steps as shown in FIG. 26 and FIG. That is, one side of a 1.4 mm-thick glass epoxy laminate 30 laminated with the copper foil 31 shown in FIG. 26A is coated with an etching resist, and a desired pattern is formed by etching (FIG. 26B. )). Then
A photosensitive insulating material 33 is applied on the substrate, and a via 34 for connecting the previously formed pattern and the upper layer circuit pattern to be formed later is formed (FIG. 26C).

Further, copper 31 is formed on the entire surface of the photosensitive insulating material 33.
And electroplating is performed to further form copper 31 thicker than the thickness of the copper previously formed (FIG. 26D). By a method similar to the above, a substrate on which copper is formed is coated with an etching resist, and a desired pattern is formed by etching (FIG. 26E).

By repeating the above steps, a circuit pattern is formed on the glass epoxy substrate 30 (FIGS. 27 (a), 27 (b) and 27 (c)). The method of manufacturing the circuit wiring board described in the present embodiment is a technique already known as the SLC technique, and thus further detailed description will be unnecessary.

The method of manufacturing the circuit wiring board is not limited to the method of manufacturing SLC, and may be, for example, an FR-4 board using an ordinary glass epoxy board as a main material. Further, the main material of the circuit wiring board is not limited to the glass epoxy resin, and for example, an alumina substrate may be used,
Of course, an AlN substrate and a silicon wafer can also be used. In addition, since the connection electrode pad formed on the circuit wiring board generally uses a part of the wiring on the circuit wiring board as an electrode pad, the formation of the electrode pad is basically different from the formation of the wiring. There is no place.

Next, FIG. 28 is a process drawing showing in detail a method of forming an inverted trapezoidal electrode pad. An opening 37 of 40 μm square is formed on a necessary portion on the glass epoxy substrate 30 shown in FIG. 28A where the copper foil 31 is laminated.
A resist film 36 provided with is formed. The resist film 36 can be formed by using, for example, the positive resist shown in Example 1 (FIG. 28B).

Then, for example, copper 32 is deposited to a thickness of 35 μm by using a method typified by an electroplating method or a vapor deposition method (FIG. 28C). Further, the resist film 36 formed around the deposited metal is dissolved and removed with acetone or the like, and the resist film 38 for etching and removing the laminated copper foil is coated again by the method shown in the first embodiment. (FIG. 28 (d) and FIG. 28 (e)).

Thereafter, as shown in Example 1, a mixed solution composed of ammonium persulfate, sulfuric acid and ethanol, a mixed solution composed of citric acid, hydrogen peroxide solution and a surfactant, or ferric chloride. The copper foil is etched and removed by the solution, and the resist film 38 is again dissolved and removed with acetone or the like (FIG. 29A). Finally, a region portion other than the portion to be the electrode pad is covered with, for example, a well-known solder resist film 9. By performing the above steps, the electrode pad 10 (3 having an inverted trapezoidal shape having an upper dimension of 50 μm and a lower dimension of 40 μm is formed on the circuit wiring board.
2) can be formed.

In addition, the trapezoidal electrode pad 10 is
The method described in FIG. 30 is used. That is, first copper foil 3
1 is laminated on the glass epoxy substrate 30 shown in FIG.
Or the copper foil 39 having a thickness of 35 μm
The step of laminating is performed. At this time, the copper foil 31
Need not be laminated in advance (see FIG. 30).
(B)).

Then, 50 is formed on the portion corresponding to the electrode pad.
A resist film 38 having a side of μm is formed (FIG. 30).
(C)). Furthermore, using the etching solution described in Example 1 or above, the required portions of the copper 39 and the copper foil 31 are removed by etching, and the etching resist film is also removed by dissolution (FIGS. 30 (d) and 30 (e)). . Then, finally, a portion other than the portion to be the electrode pad is covered with, for example, the solder resist 9 (FIG. 30 (f)). By performing the above steps, the upper dimension 40 is formed on the circuit wiring board 30.
electrode pad 1 having a trapezoidal shape with a bottom dimension of 50 μm
0 can be formed.

The method shown in FIGS. 28, 29 and 30 is an example for forming an electrode pad having a trapezoidal shape or an inverted trapezoidal shape, and is not necessarily the method described in this embodiment. It is not limited to. Therefore, for example, not only a structure in which copper is directly arranged on a glass epoxy substrate, but a dissimilar metal is interposed between the resin substrate and copper, and a nickel film or the like is provided on the uppermost layer to prevent the diffusion of copper and the solder alloy. In order to achieve the same effect, if the effect is the same, the forming method and the partial structure can be variously changed.

For example, FIG. 31 is a diagram showing a state in which the semiconductor device 1 is flip-chip mounted on the circuit wiring board 2 on which the inverted trapezoidal electrode pads 10 having no barrier metal are formed. FIG. 32 is a diagram showing a state in which the semiconductor device 1 is flip-chip mounted on the circuit wiring board 2 on which the trapezoidal electrode pads 10 having no barrier metal are formed.

Embodiment 11 This embodiment has a structure in which a third metal group is arranged between the first metal group and the electrode-constituting metals on the circuit wiring board.
The details will be described below.

The third metal group may be continuously formed on the second metal formed on the bump electrodes, or may be previously formed on the electrode pads of the circuit wiring board. For example, when the third metal group is formed in advance on the second metal on the semiconductor device side, the copper pillar material 6 is formed on the bonding pad 4.
Pb-5% Sn solder 7a is formed on the
b-63% Sn7b is continuously laminated to form a bump electrode as shown in FIG.

Then, the semiconductor device is reflowed in a nitrogen atmosphere at about 300 ° C. to ensure that Pb-5% Sn7a is not sufficiently melted but Pb-63% Sn7b is sufficiently melted. . The structure shown in FIG. 33 is realized by flip-chip mounting and connecting the semiconductor device 1 having the bump electrodes composed of the semi-molten solder to the circuit wiring board 2.

When the third metal group is previously formed on the circuit wiring board, the eutectic solder 41 made of Pb-63% Sn is formed on the electrode pad 10 on the circuit wiring board 2, for example. Then, the structure shown in FIG. 34 is realized by flip-chip mounting the semiconductor device 1 on which bump electrodes are formed so as to face the electrode pads.

When the bump electrode on the semiconductor device 1 has a structure in which copper 6 is arranged in the lower portion and Pb-5% Sn7 is formed in the upper portion, the bump electrodes shown in FIGS. 35 (a) and 35 (b) are used.
The steps shown in are to be performed.

Further, when the bump electrode on the semiconductor device 1 is covered with the solder 6 formed of Pb-5% Sn in a spherical shape and the copper 6 is arranged in the center, the bump electrode shown in FIG.
The steps shown in FIGS. 36A and 36B are performed.

In either case, the structure shown in FIG. 33 is realized by flip-chip mounting reflow in such a manner that the solder-formed portions are interconnected.

Note that in the case where a method of arranging the second or third metal group having different melting points on the bump electrodes on the semiconductor device 1 is performed, or in the case where the solder alloy is preformed on the circuit wiring board 2, By combining the methods as shown in this embodiment, it is possible to realize a structure in which three or more different metal layers are stacked as shown in FIG.

Further, in the case of this embodiment, the second metal group or the third metal group in the gap portion arranged between the first metal group 6 and the electrode pad 10 of the circuit wiring board 2 is the other second metal group. Alternatively, it is desirable that the Young's modulus or the melting point is the lowest as compared with the third metal group, but on the contrary, the Young's modulus or the melting point may be high, and between the first metal group 6 and the electrode pad 10 of the circuit line board 2. Within the scope of the present invention, if the second metal group of the arranged gap portion has physical properties that are resistant to stress strain as compared with the second metal group that constitutes the other portion. The other characteristics are not limited in any way.

Example 12 In the method according to this example, as parameters constituting the bump structure, the dimensional structure of the first metal group and the structural size of the electrode pad on the circuit wiring board, and the space between the first metal group and the electrode pad were used. The gap dimension and the width dimension of the bump electrode are set in a range that makes the structure strong against stress.

In FIG. 37, when the thickness of the first metal group 6 is thicker than the thickness of the electrode 10 on the circuit wiring board 2, the gap dimension G between the electrodes is changed to G ₁ , G ₂ and G ₃ . The case is shown. Gap G between the first metal group 6 and the electrode pad 10
Since the ratio of the first metal group 6 filled in the bump electrode becomes higher as the bump electrode becomes smaller, the bump height can be made higher even if the bump electrode size becomes fine. However, the reliability life is shortened. However, if the diameter of the bump electrode is maximized in the gap between the first metal group 6 and the electrode pad 10, the reliability life will not decrease.

FIG. 38 is a diagram showing the relationship of the bump electrode structure parameters necessary for forming the drum-shaped bump electrode. In the dimensional relationship in which the barrier metal dimension (l ₂ ) is preferably formed larger than the bonding pad dimension (l ₁ ), the barrier metal dimension is formed smaller than the upper dimension (l ₄ ) of the refractory metal, Further, when the width dimension L ₂ of the electrode pad 10 of the circuit wiring board 2 has a mutual relationship smaller than the upper dimension L ₁ of the electrode pad 10, the bump electrode structure has a refractory metal group that constitutes the first metal group 6. It will have a drum shape that conforms to the outer shape of.

Further, when the structure parameters having the dimensional relations as shown in FIG. 39 are provided, a staggered bump structure is formed. That is, the barrier metal dimension l ₂ formed to be larger than the bonding pad dimension l ₁ is formed to be larger than the upper dimension l _{4 of the} refractory metal, and the circuit wiring board 2
When the width dimension L ₂ of the side electrode pad 10 is larger than the upper dimension L ₁ of the electrode pad 10, the bump electrode structure has a shape along the corner of the first metal group 6. It becomes a staggered type as shown in FIG. At this time, since the first metal group 6 and at least a part of the electrode pad 10 are in contact with, for example, the glass epoxy substrate part, the bump electrode having the structure of FIG. 39 can be set.

The drum-shaped and claw-shaped bump electrode structures described above are optimized in the structural parameters described below. That is, a drum-shaped bump structure is formed in a gap portion where the width dimension l ₂ of the thin film metal group forming the bump electrode and the lower dimension W ₀ (L ₂ ) of the electrode pad 10 of the circuit wiring board 2 are sandwiched by those metals. When you have,
As shown in 0, the relationship W ₁ is the largest l _2, W ₀
(L ₂ ) <W _1, and when the bump is a staggered type bump, W ₂ is the smallest as shown in FIG. 41.
It is a structure showing l ₂ , W ₀ (L ₂ )> W ₁ . By setting the structural parameters as described above, the method which requires extremely strict control of the solder amount in the conventional technique is not required, and the drum-shaped or staggered bump electrode can be configured by an extremely easy method.

Example 13 The following results were obtained when the performance of a mounting structure in which a semiconductor device having bump electrodes according to the present invention was flip-chip mounted was evaluated.

FIG. 42 shows a temperature cycle test (-55 ° C.).
(30 min) to 25 ° C (5 min) to 150 ° C (30
(min) to 25 ° C. (5 min)) is a result showing the fatigue life cycle number Nf ₅₀ showing the 50% cumulative defective rate with respect to the Young's modulus of the solder alloy constituting the second metal group. The solder alloy was evaluated when eutectic solder was used.

The second metal group disposed around the first metal group is
It can be seen that when the Young's modulus is low, Nf ₅₀ has a high reliability with a high value. However, when the Young's modulus is high, the reliability life tends to be relatively short, and the Young's modulus is 0.
When it is 55 × 10 ⁻¹² or more, the reliability life becomes almost constant. Therefore, it was found that the reliability life of the bump electrode against stress strain can be increased as the Young's modulus of the second metal group is lower. The Young's modulus of, for example, a solder alloy forming the second metal group can be typically realized by changing the material and composition of the metal group forming the second metal group.

Further, FIG. 43 shows the results of measuring the fatigue life cycle number Nf ₅₀ with respect to the melting point of the solder alloy forming the second metal group. The solder alloy was evaluated by eutectic solder. When the melting point of the solder alloy that is the second metal group is low,
Although the fatigue life cycle number Nf ₅₀ shows a low value, the reliability life improves as the melting point increases, and tends to saturate at around 350 ° C. or higher.

Therefore, it was found that the reliability life of the bump electrode against stress strain increases as the melting point increases. The second metal group is a comparison of melting points with the first metal group, and if the value is lower than that of the first metal group, the temperature range and the third metal group
The combination regarding the melting point with the metal group is not necessarily limited.

FIG. 44 shows the relationship between the density of the solder alloy constituting the second metal group and the stress remaining in the bump electrodes. When a eutectic solder composition is formed by electroplating and reflowed for flip-chip mounting, it usually has a tendency to exhibit compressive stress in the density range shown in FIG. When it shifts to the high density side, it shows tensile stress, so that it is possible to prevent the bump electrode from breaking due to stress strain, and the stress strain inside the bump electrode can be relaxed even when flip-chip mounting, so the reliability life can be improved. . The results shown in FIGS. 42, 43, and 44 were similarly obtained in the combined metal group of the second metal group described in Example 7.

FIG. 45 shows the relationship between the fatigue life cycle number Nf _{50 and} the ratio L ₁ / L ₃ of the electrode upper dimension L ₁ and the lower electrode dimension L ₃ of the circuit wiring board electrode. Therefore, it has a trapezoidal shape when L ₁ / L ₃ <1, and an inverted trapezoidal shape when L ₁ / L ₃ > 1. Reliability life is L ₁ / L ₃ = 1
It has a minimum value in the vicinity and tends to have an improved Nf ₅₀ on both sides thereof.

When the first metal group serving as the pillar material arranged on the semiconductor device side has an inverted trapezoidal shape, the pulling strength is improved similarly to the semiconductor device side. In the case of having a trapezoidal shape, the structure becomes strong against stress strain, and when connecting with a solder that is not sufficiently melted, the method of crushing due to composition deformation and connecting becomes easy.

That is, it has been found that the reliability life is improved when the electrode pad structure of the circuit wiring board is not vertical but has a trapezoidal shape or an inverted trapezoidal shape. On the other hand, FIG. 46 is a graph showing the relationship between the angle θ of contact with the thin film metal group of the first metal group and the fatigue life cycle number Nf ₅₀ . Angle 9
Although the reliability life has the highest value in the region of 0 ° or less, it can be seen that the reliability life decreases conversely when the angle becomes too small. The angle with the highest reliability life was around 80 °, which is smaller than 90 °.

FIG. 47 is a graph showing the relationship between the lower dimension (l ₃ ) of the first metal group in the width dimension (l ₂ ) of the thin film metal group and the fatigue life cycle number Nf ₅₀ . The evaluation was performed when the gap G / h between the metals occupying the bump height was 0.8 and the bonding pad size was 40 μm width.

In the width dimension, when the ratio of the first metal group increases, the reliability life decreases at any bump electrode height, but the ratio (l ₃ / l ₂ ) is a constant value from around 0.75. Tend to converge to. On the contrary, when the bump electrode height increases, the reliability improves. As a result, the reliability life of the metal arranged to increase the height of the bump electrode is shortened if the proportion thereof is increased, but if the height of the bump electrode exceeds a certain value, Even if the metal is arranged, it means that the reliability life of the bump electrode manufactured by the conventional technique is exceeded and the reliability life is improved. In particular, until now, the bump electrode having a copper occupancy ratio of about 30 μm in height has been used. However, by increasing the bump height,
It has been revealed that the reliability life is improved more than ever before.

Further, FIG. 48 is a graph showing the relationship between the aspect ratio (1-G / h) / l _{3 of} the first metal group and the fatigue life cycle number. The width dimension of the bonding pad was evaluated in the case of 40 μm. The result shown in FIG. 47 is the result of evaluating the reliability with respect to the first metal group occupancy in the width direction, while FIG. 48 shows the result of evaluating the reliability with respect to the first metal group occupancy in the vertical direction. The result.

Also in this case, it means that the volume occupied in the bump electrodes of the first metal group increases as the aspect ratio increases, so that the aspect ratio basically increases. It is considered that the reliability life is shortened as a result. As a result of actually evaluating the reliability life, the reliability life decreases as the aspect ratio increases.

However, similar to the result shown in FIG. 47,
A bump electrode having a bump electrode height of a certain value or more has a reliability higher than that of the bump electrode in which the first metal group manufactured by the conventional technique is not formed even if the aspect ratio becomes high. I understand.

In order to reduce the stress strain on the bump electrode pad, if the bump electrode structure is to be realized only by the copper pillar material without coating the bump electrode with a relatively high stress nickel film or the like, If the copper thickness is large, the solder portion may be separated from the electrode pad of the circuit wiring board due to the solder diffusion. Therefore, it is effective to form copper thickly to prevent solder diffusion. In such a case, if the copper size is made the same as the barrier metal size, peeling will occur in a film with high stress, so it is effective to form a metal group having a relatively small size width to be thick.

FIG. 49 shows the relationship between the fatigue life cycle number and the gap ratio G / h in which the gap G, which is the distance between the electrodes of the first metal group, occupies the bump height h. Increasing the gap ratio means increasing the size of the gap portion, and decreasing the gap ratio G / h means decreasing the gap portion. This means that the bump electrode height can be increased as the size of the gap portion becomes smaller, and it is possible to cope with the bump electrode which is further miniaturized.

The smaller the gap ratio G / h is, the shorter the reliability life is. However, the higher the bump electrode height is, the more the reliability life is improved by compensating for the insufficient gap ratio. Therefore, it can be seen that by optimizing the gap ratio so as to maintain the bump electrode height above a certain level, it is possible to achieve more reliable life than the bump electrode manufactured by the conventional technique.

FIG. 50 shows the ratio W ₁ / W ₀ between the width W _{0 of the} thin film metal forming the drum-shaped bump electrode and the maximum diameter W ₁ of the bump electrode at the center of the bump electrode, and the reliability life cycle number Nf.
It is a graph which shows the relationship with ₅₀ . The reliability life tends to improve Nf _{50 in the} dimension setting in which W ₁ increases, and further increases as the gap ratio G / h increases. However, when W ₁ / W ₀ is increased, it becomes impossible to cope with miniaturization, and when G / h is increased, W ₁ / W ₀ is also increased and it becomes impossible to cope with miniaturization. It was found that it is necessary to arbitrarily set between the reliability life and the diameter of the bump to be formed.

FIG. 51 shows the ratio W ₂ / W ₀ between the width W _{0 of the} thin film metal forming the staggered bump electrode and the maximum diameter W ₂ of the bump electrode at the center of the bump electrode, and the number N of reliable life cycles.
is a graph showing the relationship between f _50. Reliability life is W ₂
/ W ₀ is becomes maximum within a range of _{l 3> W 2 / W 0} > 1, it was found that the higher the higher the bump electrode height.

When W ₂ / W ₀ > 1, the drum-shaped bump electrode whose reliability life is controlled by only the solder amount and the gap ratio by excluding the bump electrode structural parameters shown in FIGS. 38 and 39. It shows the case where it becomes a structure. Therefore, in the staggered bump electrode structure according to the embodiment of the present invention, it is a necessary condition that the maximum bump electrode diameter is smaller than at least the thin film metal size to improve the reliability life.

Furthermore, the distance between the electrode pad of the semiconductor device and the electrode pad of the circuit wiring board described above greatly affects the reliability life due to the heat dissipation of the semiconductor device itself. FIG. 52 shows the distance (G) between the semiconductor device and the circuit wiring board and the bump electrode height (h).
It is a graph which shows the relationship between the gap ratio (G / h) with and thermal conductivity. As shown in the graph of FIG. 52, as the gap distance (G) becomes smaller and G / h approaches 1, the thermal conductivity improves, but it tends to saturate from the vicinity of G / h = 0.5 or more. There is.

Therefore, it was found that the thermal conductivity does not improve when the gap G is large apart, but improves when the distance approaches to a certain extent, and the heat dissipation property improves significantly. This result means that the reliability life begins to show a substantially constant value from the vicinity of G / h exceeding 0.5, and the reliability does not decrease. It agrees well.

FIG. 53 shows the results of evaluating reliability by dispersing carbon and sulfur in the first metal group such as copper. The bump electrode height was 100 μm and the bonding pad width dimension was 40 μm. When a metal in which carbon and sulfur are dispersed in copper is provided in the bump electrode, the reliability life increases as the carbon and sulfur concentrations increase.
On the contrary, the reliability life Nf ₅₀ decreases from the range in which the wt% and the sulfur exceed about 30 wt%.

As shown in FIG. 54, similar results are obtained with a metal in which carbon, sulfur and oxygen are dispersed in the second metal group, solder. It was found that the reliability life is improved up to 40 wt% of carbon, 30 wt% of sulfur, and 10 wt% of oxygen, but the reliability life is decreased when the content exceeds this range. 53 and 5 shown above.
The result of No. 4 was clarified by the physical properties of the bump electrode material constituting the bump electrode described below.

FIG. 55 shows the results of evaluating the thermal conductivity by dispersively disposing carbon and sulfur elements in copper which is the first metal group. Approximately 40 wt% when carbon is dispersed in copper
It has a tendency to gradually decrease to the vicinity, but when sulfur is dispersed and arranged, it shows the minimum value at 10 to 30 wt% and 30 w
After increasing at t% or more, it shows a constant value.

This result shows that in the carbon and sulfur dispersion concentration range where the stress in the first metal group used for increasing the bump electrode height is reduced, the heat dissipation property, which is one of the causes of stress distortion, is good at the same time. Is meant to In particular, this tendency shows that the carbon concentration is 4 wt% and the sulfur concentration is 3 wt.
It is remarkable when it is less than or equal to%.

Similar results were obtained when carbon, sulfur, and oxygen were dispersed in solder. Therefore, the tendency of the gap ratio G / h shown in FIG. 52 to approach a certain value and become saturated from the vicinity of exceeding 0.5 exceeds the influence of the thermal conductivity on the heat dissipation more than the influence of the gap dimension G. It was found that the reliability life was improved as a result. Therefore, even if the gap dimension G is reduced in order to increase the bump height of the fine bump electrode, a structure in which the reliability life is not reduced can be realized.

Further, FIG. 56 shows the results of evaluating the Young's modulus when carbon, sulfur and oxygen are dispersed and arranged in the solder alloy which is the second metal group. 40 wt% when carbon is dispersed in solder, 30 w when sulfur is dispersed
It was found that the Young's modulus shows a low value in the region of 10% by weight or less when t% and oxygen are dispersed.

Therefore, carbon 40 wt as shown in FIG.
%, Sulfur 30 wt% and oxygen 10 wt% or less, the Young's modulus was small, so that the stress strain generated was relaxed and the reliability life was maximized. This tendency is particularly remarkable when carbon is 4 wt%, sulfur is 3 wt%, and oxygen is 1 wt% or less. Although not particularly described in this example, similar effects were obtained when copper was diffused and dispersed in the solder at 50 wt% or less.

Usually, reflow of solder at the time of flip-chip mounting is carried out by sufficiently lowering the oxygen concentration in nitrogen in order to prevent the oxidation of the solder alloy, but it is about 100 pp.
reflow at m or less, or if 40 wt% or less of oxygen is dispersed in the solder alloy before reflow,
An oxygen concentration range of 10 wt% or less can be realized after flip chip mounting.

The results shown in FIG. 56 were obtained similarly in the combination metal group shown in FIG. 17 described in Example 7.

Example 14 With the bump electrode having the features of the present invention, the bump electrode could be sufficiently formed even when the bonding pad size became a fine pitch and the bump electrode to be formed needed to be made small.

FIG. 57 shows that by arranging a pillar material in the bump electrodes, it becomes possible to form bump electrode pitches that could not be formed by the conventional method. By doing so, the bump electrode height necessary for further improving the reliability life can be secured at the same time.

FIG. 58 is a graph showing the relationship between the gap ratio G / h in which the electrode pad distance G between the first metal group and the circuit wiring board occupies the bump electrode height h and the bump electrode height that can be formed. is there. From FIG. 58, the height of the bump electrode that can be formed increases as the gap ratio G / h approaches 0. Naturally, the bump electrode height that can be formed increases as the size of the bonding pad increases. However, from the vicinity of G / h = 0.5, even if G / h becomes small, it becomes almost constant. From this result, it can be seen that the bump electrode height can be obviously increased and the reliability life can be improved by disposing the first metal group serving as the pillar material in the bump electrode.

FIG. 59 is a graph showing the relationship between the gap ratio G / h of the semiconductor device mounting structure flip-chip mounted and the minimum bump electrode diameter that can be formed. The bump electrode diameter cannot be reduced when the gap ratio is close to 1, which is a conventional technique, but the bump electrode diameter that can be formed can be reduced as the gap ratio becomes smaller. As shown.

From these results, the height of the bump electrode to be formed can be increased and the diameter of the bump electrode can be decreased by reducing the gap ratio to some extent, so that the gap ratio G / h does not necessarily have to be near zero. I understood it.

Example 15 It has been described in the above examples that the bump electrode of the semiconductor device mounting structure of the present invention exerts its effect when the thickness of the first metal group is thicker than the electrode thickness of the circuit wiring board.

FIG. 60A shows the bump electrode structure of the semiconductor device mounting structure according to this example, and the structural parameter is H> H ₀ . However, when the performance evaluation shown in Example 13 was performed, the structural parameter 0 ≦ shown in FIG.
It was found that the reliability life was not reduced even when H <H ₀ was satisfied. That is, the circuit wiring board side is given the role of increasing the height of the bump electrode, and the reliability life can be secured even if the height of the first metal group on the semiconductor device side is finally set to zero. .

FIG. 61 shows the relationship between the ratio H ₀ / H of the electrode height of the circuit wiring board to the height H of the first metal group and the fatigue life cycle number Nf ₅₀ . H ₀ / H> 1
When, the Nf ₅₀ shows a high value as described above,
Even when H ₀ / H <1, especially 0.5 <H ₀ / H
When it is 1 or more, a certain reliability life can be secured.
Therefore, even when H ₀ / H = 0, a reliable life can be ensured if necessary. Therefore, H / H which is the reverse of H ₀ / H
_{When 0} = 0, the same result as that shown in FIG. 61 is naturally obtained.

The reliability of the mounting structure in which the semiconductor device having the bump electrode according to the present embodiment is flip-chip mounted on the circuit wiring board is subjected to a high temperature bias test (85 ° C., 85 ° C.).
%, V _DD = 5V), a semiconductor device flip-chip mounted by forming a solder bump electrode of 60 μm square with a conventional drum-shaped bump showed a migration at 500H. In the method according to the example, the insulating property was sufficient up to 3000H, and migration did not occur.

Further, a semiconductor device is provided at 14 to 17 × 10 ⁻⁶ /
Flip-chip mounting with the connection structure of Fig. 1 on a glass epoxy substrate having different thermal expansion coefficients of about 1 digit of ^{3.5x10 -6} / ° C of silicon and 3.5 x 10 ^-6 / ° C.
(30 min) to 25 ° C (5 min) to 150 ° C (30
(min) to 25 ° C. (5 min)) for 3000 cycles, no defect occurred. Similarly, even when the high temperature storage test (150 ° C.) was performed for 1000 hours, the barrier metal peeling failure due to the diffusion of copper and solder did not occur.

Similar results were obtained also in the flip chip mounting structure in which the barrier metal size l ₂ forming the bump electrode was made larger than the upper size L ₂ of the refractory metal group to form a stub type bump. That is, in the high temperature bias test, 30
Defects due to migration did not occur up to 00H, and defects due to stress strain did not occur up to 3000H in the temperature cycle test.

Also in the high temperature storage test, the peeling failure of the barrier metal due to diffusion did not occur similarly. Therefore, the above results show that the semiconductor device according to the present invention has sufficient reliability.

Further, in the semiconductor device mounting structure having the structure according to the present invention, a gap is formed between the first metal group forming the bump electrode formed on the semiconductor device and the electrode pad of the circuit wiring board, In this gap, the second metal group or the third metal group
Although the effect of the structure in which the metal group is arranged has been described, the characteristic of the physical properties of the metal material forming the bump electrode according to the present invention is also exhibited in Japanese Patent Application No. 3-126406. , Reliability life is improved.

In addition, in Examples 1 to 15 described above, it was described that the metals dispersedly arranged in the first metal group and the second metal group reduce the residual stress strain and improve the reliability life. . However, it has been found that carbon, sulfur, and oxygen elements dispersedly arranged in the first metal group and the second metal group also improve the yield stress of the metal at the same time and improve the strength against stress strain. In particular, carbon 40 wt%, sulfur 30
When the concentration range of wt% and oxygen of 10 wt% or less was dispersed, the behavior was almost the same as the behavior of residual stress, and the reliability life was increased more than when the conventional technique was used.

Furthermore, the same behavior is obtained by the first metal group and the second metal group.
The hardness of the metal group was also found, and it was found that the hardness of the first metal group decreased within the range of 40 wt% carbon and 30 wt% sulfur. Therefore, it was found that even if copper is arranged in the bump electrode, the reliability is significantly improved as compared with the conventional case where carbon and sulfur elements are not arranged dispersedly.

On the other hand, since the first metal group is a pillar material, it is desirable that the height is originally uniform, but for example, ± 5 μm.
When flip-chip mounting is performed on the circuit wiring board with height variations within the range, even in a multi-layer wiring board where the unevenness of the electrode pad surface is significant, the height variations can be well absorbed, resulting in connection failure. It never happened. This result was due to variations in bump electrode height forming a gap between the first metal group and the electrode pad of the circuit wiring board, and making the connection defective at this portion. Further, this gap portion has the effect of absorbing and relaxing the impact due to the pressing force during flip-chip mounting, and not particularly damaging the electrode pads of the circuit wiring board. Example 16 Hereinafter, an example of the present invention will be described with reference to FIGS. 62 to 66. 62 is a first example of the semiconductor device according to the present embodiment, and FIG. 63 is a second example of the semiconductor device according to the present embodiment.
64 and 65 are cross-sectional views showing a manufacturing process for realizing the method for manufacturing a semiconductor device according to this embodiment, and FIG. 66 is a third embodiment of the semiconductor device according to this embodiment. Here is an example.

62 to 66, reference numeral 100
Is a semiconductor substrate, 200 is a cathode metal, 300 is a bump electrode metal, 400 is a resist film, 400 is a bonding pad, 320 is a passivation film, 330 is a plating resist, 340 is a Cu metal protrusion, 350 is a solder film, 360 is a resist, 370 is a glass mask and 380
Is a mask pattern and 390 is a wiring board.

First, referring to FIG. 64, the semiconductor device 100 is shown.
A bonding pad 310 is formed on the passivation film 32 except the bonding pad 310.
On the wafer on which 0 is formed, for example, Cu / Ti is vapor-deposited on the entire surface to form the cathode metal 200. (Fig. 6
4 (a)).

Then, a resist AZ4903 (Hoechst Japan) is spin-coated to form a resist 330 having a film thickness of 50 μm, and a side of 5 μm, which is smaller than the bonding pad 310 having an opening of 20 μm □ by exposure and development, has a size of 10 μm. To form the opening (FIG. 64)
(B)). The resist film 330 is the Cu / Ti film 20.
It has a contact angle of 0 and less than 90 °.

In this way, a wafer in which the resist 330 is opened with a size smaller than that of the bonding pad in the portion corresponding to the bonding pad 310 is formed into copper sulfate 250.
Immersion in a solution consisting of 50 g / l of sulfuric acid (specific gravity 1.84), g / l, Ti / Cu at the bath temperature of 25 ° C. as the cathode, high-purity copper plate as the anode, and current density of 5 A / dm ² applied Then, 35 μm of copper is plated with gentle stirring.

Then, the plating bath was set to 40 g / l of total tin, the first
Tin 35g / l, Lead 44g / l, Free boric acid 40g /
l, boric acid 25 g / l, glue 3.0 g / l, instead of Cu / Ti as the cathode,
A current density of 3.2 A / dm ^{2 was} applied using 40% tin as an anode, and the temperature of the bath was 25 ° C. with gentle stirring, and Pb / Sn =
40/60 alloy is continuously plated by 15 μm (see FIG. 64).
(C)).

The plating resist AZ-4903 of the wafer in which only the bonding pads are plated with two kinds of copper and Pb / Sn alloy is removed with acetone. (Fig. 64
(D)).

Then, for example, an image reversal type resist AZ5 is formed on the wafer on which the protruding electrodes are formed on Cu / Ti.
A solution of 214E (Hoechst Japan) whose viscosity has been adjusted is spin-coated to form a resist film. At this time, the resist film had a shape corresponding to the bump metal on the surface, and had a thickness of 10 μm on the bump metal and a thickness of 55 μm on the cathode metal portion where the bump metal was not formed. (FIG. 64 (e)).

Then, a glass mask having an opening pattern having an opening dimension of 2 μm larger than that of the projecting metal of 10 μm and having a side of 14 μm is aligned with a required position and then exposed (FIG. 64 (f)). The exposure is performed with an exposure energy of 2000 mJ, and after exposure, the wafer is baked on a hot plate at 150 ° C. The baked wafer is immersed in a developing solution for development.

By performing the above steps, FIG.
A resist as shown in FIG. The resist is formed on the protruding metal in a reverse taper shape in which the lower portion contacts the protruding metal and the cathode metal and the upper portion sufficiently covers the protruding metal (FIG. 65 (a)).

Then, after etching Cu with a mixed solution of ammonium persulfate / sulfuric acid / ethanol, EDT was performed.
Ti is etched with a solution of A, ammonia, and hydrogen peroxide solution, and the finally formed etching resist is removed with acetone (FIG. 65 (b)). By etching in this way, a barrier metal having an angle of less than 90 ° can be formed, and the protruding metal is not dissolved and the state after electroplating is maintained.

Next, the semiconductor chip and the wiring board are aligned using a flip-chip bonder that is equipped with a half mirror, which is a known technique, and the bumps are brought into contact with the electrodes on the substrate. At this time, the substrate is held on a stage having a heating mechanism, and Pb / Sn = 40/6
0 higher than melting point of solder and lower than melting point of Cu 28
It is preheated to 0 ° C. (FIG. 65 (c)).

Further, with the semiconductor chip and the substrate in contact with each other, the collet holding the semiconductor chip is heated in a nitrogen atmosphere to the same temperature as the stage on which the substrate is mounted, 280 ° C., to remove the solder formed on the bump. By melting, the semiconductor chip and the electrodes of the substrate are electrically connected. At this time, since the barrier metal dimension l ₁ is smaller than the upper dimension L _{1 of the} refractory metal, the bump shape becomes a drum shape conforming to the outer shape of the refractory metal (FIG. 65).
(D)).

When the etching accuracy of the cathode metal of the wafer having the protruding metal described above was evaluated, the following results were obtained.

Bump electrode size 10 μmφ, gap 10
15μm upper resist, 11μm lower resist
And the etched cathode metal is 11μ
mφ and a gap of 9 μm. The etching accuracy was dramatically improved as compared with the cathode metal of 18 μmφ and the gap of 2 μm when etching was performed using the positive / negative type resist of the prior art.

Further, when the metal was etched by using the difference in the speed at which the protruding metal was dissolved in the etching solution without using the resist, the bump electrode had a diameter of 2 μmφ and the gap was 2 μm. Further, in the conventional technique, the metal exposed to the etching solution was partially corroded, but in the method according to the present invention, the metal was not dissolved and was etched with high precision.

Further, the semiconductor chip on which bump metal is formed by the above method is flip-chip mounted on a wiring board and subjected to a high temperature bias test (85 ° C., 85%, V _DD = 5).
V) was performed, the semiconductor device manufactured by using the conventional method with low etching accuracy showed migration at 500H, whereas the method according to the present invention had sufficient insulation up to 3000H and migration occurred. I didn't.

Further, a semiconductor element is provided in an amount of 14 to 17 × 10 ⁻⁶ /
Flip-chip mounting with the connection structure shown in FIG. 62 on a FR-4 substrate having a thermal expansion coefficient of 3.5 × 10 ⁻⁶ / ° C. different from that of silicon by 3.5 × 10 ⁻⁶ / ° C.
(30 min) to 25 ° C (5 min) to 150 ° C (30
(min) to 25 ° C. (5 min)) for 3000 cycles, no defect occurred.

Further, when the barrier metal dimension l ₂ is made larger than the upper dimension L _{2 of the} refractory metal for flip-chip mounting, as shown in FIG. 63, it becomes a hook type with the corners of the refractory metal. It was

In this case as well, the etching accuracy of the barrier metal is remarkably improved as compared with the case of using the conventional technique as in the case described above, and migration is caused up to 3000 H in the high temperature bias test. No defects occurred. Further, even when the temperature cycle test was performed, no defects occurred up to 3000H.
Therefore, from the above results, the reliability of the semiconductor device according to this example was sufficient.

In the present embodiment, the refractory metal need not always be separated on the bump side and the substrate side as described above, and the refractory metals may be in contact with each other as shown in FIG. . Further, the metal forming the bump electrode is C
Not limited to u and Pb / Sn, but In and S
b, etc. may be added and the material is not limited. Similarly, the cathode metal may be not only Cu / Ti but also a laminated film of different metals. Further, the size, thickness, and structure of the barrier metal used as the cathode during electroplating shown in the examples are not limited, and the resist is not limited in the same manner. The same applies to the etching resist and the etching method, and the contents described in Examples are not limited.

According to this embodiment, since the high melting point metal and the barrier metal arranged inside the bump metal having different melting points have an inverted trapezoidal shape with a contact angle of 90 ° or more, the bump type bump and the drum type drum are formed. Any bump shape of the bumps can be set arbitrarily. Therefore, the bump having the required shape can be easily realized, and the reliability is improved. Further, since the barrier metal formed on the substrate has an angle of less than 90 ° with the substrate, it becomes resistant to thermal stress.

Further, the resist film formed on the bump electrode metal undergoes negative / positive inversion due to heat treatment, so that the resist film is protected up to the side surface of the bump electrode. Further, since the resist film is formed thick at the portion where the bump electrode metal is most exposed, the cathode metal can be selectively etched with high precision except the bump electrode metal portion.

Unlike the conventional method, the resist film to be formed in which negative / positive reversal occurs has the thinnest film thickness in the exposed portion, so that sufficient exposure is possible. Further, in order to sufficiently perform the exposure up to the portion in contact with the cathode metal under the bump electrode, the required increase in exposure energy causes the resist film on the bump electrode metal to have an inverse taper shape.

Therefore, as a result, the resist film has an inverse taper shape along the shape of the bump electrode metal, and becomes thicker at the portion where the bump electrode metal is most exposed, and the reliability against etching is improved.

Further, since the resist film can be formed up to the side surface portion of the bump electrode metal which is in contact with the cathode metal, the fine gap portion can be etched accurately.

Furthermore, when metal is deposited by electroplating, minute bump electrode metal may be formed due to abnormal deposition. However, when the method according to the present invention is used, the bump electrode metal portion is exposed and the other portions are not exposed, and the resist is formed. Therefore, only the abnormal deposition portion can be selectively removed by etching.

Therefore, since the bump electrode metal having a high aspect ratio shape can be made to have a structure resistant to thermal stress and can be etched with high precision, a highly reliable semiconductor device can be realized.

The present invention is not limited to the above embodiments, but various modifications can be made without departing from the spirit of the invention.

For example, although the bump electrode formation is described by using a specific material in the above-mentioned embodiments, the material is not limited to the materials described in the embodiments. Furthermore, in the present embodiment, the semiconductor device and the mounting structure thereof in which drum-shaped and staggered bump electrodes are formed respectively have been described. Of course, a semiconductor device in which these bump electrodes are mixed in the same semiconductor device, and The mounting structure may be used, and its configuration and contents are not limited at all.

[0275]

As described above, according to the present invention,
Since the bump electrode structure formed on the semiconductor chip in the previous step of flip-chip mounting the semiconductor device has an inverted trapezoidal shape, the adhesion area to the thin film metal is reduced. Therefore, even if a pillar metal having a high melting point and a low thermal conductivity is arranged in the bump electrode for the purpose of forming a bump electrode having a high height, it is possible to reduce the residual stress in the first metal. is there. Furthermore, since the volume of the first metal group is set smaller than that of the second metal group, the stress remaining in the bump electrodes can be reduced.

When the structural parameters forming the bump electrode are l ₂ > l ₁ > l ₃ or l ₂ > l ₃ > l ₁ , the width dimension of the thin film metal is larger than the width dimension of the bonding pad. Since the metal group is smaller than the width dimension of the thin film metal, the stress remaining on the bump electrode can be reduced. Furthermore, this bump electrode structure parameter 1
As an aspect ratio of the first metal group is 0.01 to 200
It is possible to reduce the residual stress in the bump electrode by setting it within the range.

If the residual compressive stress is not reduced, the thin film metal which is the barrier metal metal is peeled off. With the above structure, the residual stress in the first metal group and the residual stress in the bump electrode remain. It is possible to reduce the applied stress, and it is possible to improve the reliability life especially against stress strain as compared with the prior art.

In the first metal group constituting the first metal group to be arranged, carbon is 40 wt% or less and sulfur is 30 wt.
When dispersed in a concentration range of not more than%, the compressive stress generated when carbon and sulfur are not dispersed can be converted into the opposite tensile stress and peeling of the thin film metal can be prevented. The same effect is obtained by adding 40 wt% or less of carbon and 30 wt% or less of sulfur to the solder forming the second metal group.
It can also be obtained when oxygen of 10 wt% or less is dispersed.

The effect of the tensile stress is based on the relationship of the bump electrode structural parameters in consideration of the reliability life of the bump electrode to be formed, even if the compressive stress remains in the first metal group, Since the residual stress as a whole is converted into a tensile stress, the stress generated in the bump electrode can be converted into a tensile stress as a result, barrier metal peeling can be prevented, and the reliability life is improved.

Further, when carbon and sulfur are dispersed in the first metal group within a certain concentration range, and when carbon, sulfur and oxygen are dispersed in the second metal group within a certain concentration range, electric Since the resistivity can be reduced as compared with the case where each element is not dispersed, the characteristics of the semiconductor device mounted by flip chip can be sufficiently exhibited.

Further, according to the present invention, in order to increase the bump height in the flip chip mounting process, the bumps are arranged in the first metal group bump electrode having a high melting point and a high thermal conductivity. Therefore, it is possible to increase the height of the bump electrode having a fine structure that cannot be formed by the conventional technique. Since the amount of the gap between the semiconductor device and the circuit wiring board can be increased by increasing the bump height, it is possible to reduce the stress generated in the resin when the sealing resin is arranged in the gap. As a result, the reliability of the resin is improved, and the stress strain applied to the bump electrode can be reduced, so that the reliability life is improved.

Also, by disposing the first metal having high thermal conductivity in the bump electrode, heat dissipation from the semiconductor chip can be improved, and the difference in thermal expansion coefficient between the semiconductor device and the circuit wiring board can be reduced. Even if it is large, the amount of heat generation can be reduced, and as a result, the stress strain due to the amount of displacement can be reduced.

When the shape of the first metal group has an inverted trapezoidal shape, it is possible to improve the extraction strength of the bump electrode and reduce the portion where a stress difference with the thin film metal occurs. You can Therefore, as compared with the semiconductor device mounting structure in which the first metal group having a trapezoidal shape is arranged, the breakage of the bump electrode can be easily prevented,
The reliability life can be improved. In particular, when the angle of the portion in contact with the thin film metal group is set in the range of 80 ° to 90 °, the reliability is improved.

Further, between the first metal group in the bump electrode and the circuit wiring board, at least a part of the third metal group has a lower melting point or a lower Young's modulus than the second metal group, or the first metal group. When the second metal group having a lower density than the second metal group that covers the periphery of the metal group is provided, the problem that the bump electrode is broken at the portion where the stress is most concentrated can be solved. On the other hand, regarding the melting point of the second metal group,
Since the higher the melting point of the bump electrodes mounted by flip-chip mounting, the longer the reliability life is. Therefore, when arranging the metal groups having different melting points, the metal having a high melting point should be arranged in the gap between the first metal group and the circuit wiring board. As a result, the reliability is extremely improved.

Further, it is possible to easily realize a bump shape having a drum shape or a zigzag type structure centering on the gap portion. The drum shape bump electrode has the largest diameter in the gap portion, and the zigzag type bump electrode has the largest diameter. Since the gap has the smallest diameter, the reliability life can be improved. The shape of the bump electrode is defined by the relationship between the electrode pad size of the first metal group and the circuit wiring board and the barrier metal size. Therefore, a method of increasing the solder amount from the column volume considering the barrier metal size, or As compared with the conventional method which is specified by the method of reducing the size, a drum-shaped or staggered bump structure can be easily realized.

The first metal group has a width dimension smaller than the thin film metal group on the thin film metal larger than the bonding pad dimension, and the aspect ratio is set within the range of 0.01 to 200. Therefore, even if a rigid metal group is placed in a soft metal, which is a structure in which the deformation of the bump electrode does not sufficiently occur due to the stress strain, the flip structure using the bump structure by the technique that does not consider the conventional size is used. The reliability life can be improved as compared with the chip mounting structure.

Further, in the present invention, when the first metal group and the electrode pad of the circuit wiring board are provided with a gap portion, the circuit wiring board has a large unevenness, for example, the copper clad wiring is formed on the glass epoxy substrate. In such a case, the semiconductor device can be flip-chip mounted in parallel with the circuit wiring board by absorbing the unevenness, and the reliability is improved.

Furthermore, when 40 wt% or less of carbon and 30 wt% or less of sulfur are dispersed in the first metal group to be disposed, the compressive stress is sufficient as compared with the case where carbon or sulfur is not dispersed. Therefore, it is possible to prevent the peeling of the thin film metal.

Further, the second metal group disposed around the first metal group contains at least 40 wt% of carbon and 30% of sulfur.
When either wt% or less or oxygen 10 wt% or less is dispersed, the tensile stress generated when the element is not dispersed can be converted into compressive stress, and the residual tensile stress in the first metal group can be adjusted. As a result, the stress applied to the bump can be reduced to zero as a result.

The semiconductor package having the bump electrode structure described above is particularly effective when the semiconductor device is flip-chip mounted on, for example, a glass epoxy substrate made of a resin substrate having a significantly different thermal expansion coefficient. It is significantly larger than the flip-chip mounting structure manufactured by using.

Therefore, according to the present invention, the semiconductor device and its mounting structure can be realized by reliable and easy means.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device mounting structure according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device mounting structure according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor device mounting structure according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a semiconductor device mounting structure according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 13 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 14 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 15 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 16 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 17 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 18 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 19 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 20 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 21 is a characteristic diagram illustrating effects of the semiconductor device of the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 27 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 30 is a sectional view showing a manufacturing process of a semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 31 is a sectional view showing a semiconductor device mounting structure according to a fifth embodiment of the present invention.

FIG. 32 is a sectional view showing a semiconductor device mounting structure according to a sixth embodiment of the present invention.

FIG. 33 is a sectional view showing a semiconductor device mounting structure according to a seventh embodiment of the present invention.

FIG. 34 is a sectional view showing a semiconductor device mounting structure according to an eighth embodiment of the present invention.

FIG. 35 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure according to another embodiment of the present invention.

FIG. 37 is a sectional view showing a semiconductor device mounting structure according to a ninth embodiment of the present invention.

FIG. 38 is a sectional view showing a semiconductor device mounting structure according to a tenth embodiment of the present invention.

FIG. 39 is a sectional view showing a semiconductor device mounting structure according to an eleventh embodiment of the present invention.

FIG. 40 is a sectional view showing a semiconductor device mounting structure according to a twelfth embodiment of the present invention.

FIG. 41 is a sectional view showing a semiconductor device mounting structure according to a thirteenth embodiment of the present invention.

FIG. 42 is a characteristic diagram showing the effect of the semiconductor device mounting structure of the present invention.

FIG. 43 is a characteristic diagram showing the effect of the semiconductor device mounting structure of the present invention.

FIG. 44 is a characteristic diagram showing the effect of the semiconductor device mounting structure of the present invention.

FIG. 45 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 46 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 47 is a characteristic diagram showing an effect of the semiconductor device mounting structure of the present invention.

FIG. 48 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 49 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 50 is a characteristic diagram showing the effect of the semiconductor device mounting structure of the present invention.

FIG. 51 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 52 is a characteristic diagram showing the effect of the semiconductor device mounting structure of the present invention.

FIG. 53 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 54 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 55 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 56 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 57 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 58 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 59 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 60 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 61 is a characteristic diagram showing effects of the semiconductor device mounting structure of the present invention.

FIG. 62 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 63 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 64 is a cross-sectional view showing the manufacturing process of the semiconductor device according to another embodiment of the present invention.

FIG. 65 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 66 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 67 is a sectional view showing a semiconductor device according to a conventional technique.

FIG. 68 is a sectional view showing a semiconductor device according to a conventional technique.

FIG. 69 is a cross-sectional view showing a semiconductor device according to a conventional technique.

FIG. 70 is a sectional view showing a semiconductor device according to a conventional technique.

71 is a cross-sectional view showing a semiconductor device according to a conventional technique.

FIG. 72 is a cross-sectional view showing a semiconductor device according to a conventional technique.

FIG. 73 is a cross-sectional view showing a semiconductor device according to a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Circuit wiring board, 3 ... Passivation film, 4 ... Bonding pad, 5 ... Thin film metal used as barrier metal, 6 ... 1st metal group, 7 ... 2nd metal group, 8 ... Circuit wiring Metal that constitutes the electrode pad of the substrate, 9
... Solder resist or protective film for circuit wiring board, 10
... Wiring electrode metal of circuit wiring board, 11 ... Electrode barrier metal of circuit wiring board, 12 ... Resin filling gap between semiconductor chip and circuit wiring board, 21 ... Semiconductor device, 22 ... Cathode metal, 23 ... Plating resist, 24 ... bump electrode formation region, 25 ... etching resist, 26 ... glass,
27 ... Bump forming pattern, 28 ... Glass mask, 29
... Gap between semiconductor chip and circuit wiring board, 30 ... Glass epoxy resin, 31 ... Copper foil, 32 ... Circuit wiring pattern, 3
3 ... Photosensitive insulating material, 34 ... Connection via, 35 ... Through hole, 36 ... Plating resist, 37 ... Electrode forming region, 38
... Etching resist, 39 ... Copper film, 40 ... Gap between first metal group and circuit wiring board electrode pad, 41 ... Third metal group, 42 ... Bump electrode metal.

Claims (4)

[Claims] 1. A metal thin film formed on a bonding pad of a semiconductor chip, and a bump electrode formed on the metal thin film so as to project from the first metal layer and a second metal layer. The second metal layer comprises 10 ⁻⁴ to 40% by weight of carbon, 10 ⁻⁴ to 30% by weight of sulfur, and 10 ⁻⁴ to
A semiconductor device containing 10% by weight of oxygen. 2. A semiconductor comprising a metal thin film formed on a bonding pad of a semiconductor chip, and a bump electrode formed on the metal thin film so as to project from the first metal layer and a second metal layer. A mounting structure in which a device is flip-chip mounted on an electrode pad of a circuit wiring board, wherein the first metal layer and the electrode pad are connected via the second metal layer, and the second metal layer is connected. A semiconductor device mounting structure, wherein a portion of the layer between the first metal layer and the electrode pad has a density different from that of other portions of the second metal layer. 3. A semiconductor comprising a metal thin film formed on a bonding pad of a semiconductor chip, and a bump electrode formed of a first metal layer and a second metal layer protrudingly formed on the metal thin film. A mounting structure in which a device is flip-chip mounted on an electrode pad of a circuit wiring board, wherein the first metal layer is covered with the second metal layer, and the second metal layer is A semiconductor device mounting structure, which is connected to the electrode pad via a third metal layer different from the second metal layer. 4. A semiconductor comprising a metal thin film formed on a bonding pad of a semiconductor chip, and a bump electrode formed on the metal thin film so as to project from the first metal layer and a second metal layer. A mounting structure in which a device is flip-chip mounted on an electrode pad of a circuit wiring board, wherein the first metal layer and the electrode pad are connected via the second metal layer. The semiconductor device mounting structure, wherein the layer has an inverted trapezoidal shape, and the electrode pad has a thickness of 20 μm or more.