JPH07202659A - Pulse width modulation signal output circuit - Google Patents

Abstract

PURPOSE:To form a pulse width modulation signal output circuit outputting a pulse width modulation signal whose degree of modulation degree is 1/3 to 2/3 according to analog signals. CONSTITUTION:A clock pulse of the frequency which is three times as many as the frequency of a transmission signal is imparted to a Johnson ternary counter 10. By the output of the Johnson counter 10, the period of a transmission signal is divided into three. The terminal voltage of a capacitor 26 is rapidly discharged via a first NPN transistor 16 and is made 0v in a first section, the terminal voltage is rapidly charged via a second NPN transistor 20 and is made operating voltage in a third section, and the terminal voltage is gradually charged via a PNP transistor 18 according to the voltage of an analog signal in a second division. The terminal voltage of this capacitor 26 is compared with the threshold Vs of a Schmidt inverter 28 and is further inverted, and a pulse width modulation signal of degree of modulation of 1/3 to 2/3 according to the voltage of an analog signal is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation signal output circuit for converting an analog signal into a pulse width modulation signal having a modulation degree of 1/3 to 2/3.

[0002]

2. Description of the Related Art In recent years, various data including video signals and the like have been transmitted by pulse width modulation signals using general telephone lines. And, since the general telephone line is used, it is desirable that the occupied bandwidth of the pulse width modulation signal is narrow,
It is known that if the modulation degree is 1/2, the occupied band is the narrowest. Therefore, a pulse width modulation signal in which the modulation degree changes within a predetermined range centering on the modulation degree 1/2 is generally used.

[0003]

In a conventional circuit for converting a pulse width modulated signal, a pulse width modulated signal having a modulation degree corresponding to an analog signal as an input signal is output. Therefore, even if the analog signal has an abnormally high or low voltage value and an error, a pulse width modulation signal with an abnormally high or low modulation degree is output correspondingly. Therefore, the modulation factor of the output pulse width modulation signal is not necessarily limited to the predetermined range, and the occupied band may be widened.

The present invention has been made in view of the conventional circumstances as described above, and when converting an analog signal into a pulse width modulation signal, the modulation degree thereof is set to 1/3 to 2/3. It is an object to provide a width modulation signal output circuit.

[0005]

To achieve the above object, the pulse width modulation signal output circuit of the present invention converts an analog signal into a pulse width modulation signal having a modulation degree of 1/3 to 2/3. A pulse width modulation signal output circuit, which supplies a clock pulse having a frequency three times the frequency of a transmission signal to a ternary Johnson counter or ring counter,
A digit output is given to the base of the first NPN transistor whose emitter is grounded, a two digit output is given to the emitter of the PNP transistor, and a three digit output is applied to the collector of the second NPN transistor base. To the base of the PNP transistor, the collector of the PNP transistor and the first N
The collector of the PN transistor, the emitter of the second NPN transistor, one end of the capacitor and the input end of the comparison and inverting circuit are connected, the other end of the capacitor is grounded, and the pulse width modulation is performed from the output end of the comparison and inverting circuit. It is configured to output a signal.

[0006]

[Operation] The period of one transmission signal is divided into three by the output of Johnson counter or ring counter of ternary,
The pulse width is increased or decreased according to the voltage of the analog signal within the period of the second section.

[0007]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. 1 is a circuit diagram of an embodiment of a pulse width modulation signal output circuit of the present invention, and FIG. 2 is a time chart for explaining the operation of the circuit of FIG.

In FIG. 1, a clock pulse having a frequency three times the frequency of the transmission signal is applied to the clock input terminal 12 of the ternary Johnson counter 10. The 1-digit output end of the Johnson counter 10 is connected to the base of the first NPN transistor 16 via the resistor 14, the 2-digit output end is connected to the emitter of the PNP transistor 18, and the 3-digit output end is 2 is connected to the base of the NPN transistor 20. Further, a modulation signal input terminal 22 to which an analog signal as a modulation signal is given is connected to the base of the PNP transistor 18, and a diode 24 is further provided.
In the opposite direction to the base of the second NPN transistor 20. Then, the collector of the PNP transistor 18, the collector of the first NPN transistor 16, the emitter of the second NPN transistor 20, and the capacitor 2
One end of 6 and the input end of a Schmitt inverter 28 as a comparison inverting circuit are connected together. Also, the other end of the capacitor 26 is grounded, the base of the first NPN transistor 16 is grounded via the resistor 30, and the second NP is connected.
A voltage of, for example, + 5v is applied to the collector of the N transistor 20. Further, the output terminal of the Schmitt inverter 28 is connected to the output terminal 32.

The operation of the above arrangement will be described with reference to FIG. When the clock pulse of FIG. 2 (a) is applied to the clock input terminal 12, the one-digit output of the Johnson counter 10 is "1" in the first section which is divided into three periods of one transmission signal as shown in FIG. 2 (b). It becomes "H" and becomes "L" in the second and third divisions. The 2-digit output becomes "H" in the second section and becomes "L" in the first and third sections, as shown in FIG. 2 (c). Further, the output of three digits becomes "H" in the third section and becomes "L" in the first and second sections, as shown in FIG.
Therefore, in the first section, the first NPN transistor 16
Becomes conductive, the capacitor 26 is rapidly discharged and its terminal voltage becomes 0V. In the third division, the second NP
The N-transistor 20 is turned on, the capacitor 26 is rapidly charged, and its terminal voltage becomes an operating voltage of 5 v, for example. The output voltage of each digit of the Johnson counter 10 is the operating voltage of 5V. In the second section, the first and second NPN transistors 16 and 20 are both non-conductive, and the emitter of the PNP transistor 18 is applied with, for example, the 2-digit output of the 5v Johnson counter 10. The capacitor 26 is gradually charged according to the voltage of the analog signal applied to the modulation signal input terminal 22. If the voltage of the analog signal is in the center of the fluctuation range, the terminal voltage of the capacitor 26 is charged to exceed the threshold value v _s of the Schmitt inverter 28 in the center of the period of the second section, as shown in FIG. It If the voltage of the analog signal is low, as shown in FIG.
If the rate of rise of the terminal voltage of the capacitor 26 is large, and if it is high, the rate of rise will be small as shown in FIG.
Therefore, according to the voltage of the analog signal, the capacitor 2
The terminal voltage of 6 is the threshold value v of the Schmitt inverter 28.
The period until it exceeds _s changes. The Schmitt inverter 28 outputs a pulse width modulation signal as shown in FIG. 2 (f) to the output terminal 32. Here, if the voltage of the analog signal is in the center of the fluctuation range, the pulse width modulated signal w
₁ has a modulation factor of 1/2, and if the voltage of the analog signal is low, the pulse width modulation signal w ₂ has a modulation factor of 1/3 or more, but lower than 1/2, and the analog signal voltage is high. For example, the pulse width modulated signal w ₃ has a modulation degree of ⅔ or less, but higher than ½. Even if the voltage of the analog signal is abnormally low, the modulation degree of the pulse width modulation signal that is output is 1/3, and the modulation degree is not lower than this, and conversely, the pulse width modulation signal that is output even if it is abnormally high. The modulation degree of the signal is ⅔, which is not higher than this.

Therefore, regardless of the voltage of the analog signal, the output pulse width modulation signal has a modulation degree of 1/3 to 2/3. Therefore, if such a pulse width modulated signal is transmitted through a general telephone line, the occupied band is narrow, which is preferable.

Although the Johnson counter 10 is used in the above embodiment, the present invention is not limited to this, and the same applies to a ternary ring counter. Further, the comparison and inversion circuit is not limited to the Schmitt inverter 28, and may have any circuit configuration that exhibits the comparison operation and the operation of inverting its output.

[0012]

As described above, since the pulse width modulation signal output circuit of the present invention is constructed, the following special effects are obtained.

In the pulse width modulation signal output circuit of the present invention, the modulation degree of the output pulse width modulation signal is 1/3 to.
It is limited to 2/3, and when the analog signal is abnormally low or high voltage, the modulation degree is 1/3 or 2/3,
A narrow pulse width modulation signal in the occupied band is output. Therefore, a pulse width modulation signal suitable for transmission on a general telephone line or the like can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a pulse width modulation signal output circuit of the present invention.

FIG. 2 is a time chart explaining the operation of the circuit of FIG.

[Explanation of symbols]

 10 ternary Johnson counter 16 first NPN transistor 18 PNP transistor 20 second NPN transistor 22 modulation signal input terminal 26 capacitor 28 Schmidt inverter 32 output terminal

Claims (1)

[Claims] 1. An analog signal having a modulation degree of 1/3 to 2/3
A pulse width modulation signal output circuit for converting into a pulse width modulation signal, which is a circuit for supplying a ternary Johnson counter or ring counter with a clock pulse having a frequency three times the frequency of a transmission signal, and outputting a one-digit output thereof. Is applied to the base of the first NPN transistor which is grounded, a two-digit output is applied to the emitter of the PNP transistor, and a three-digit output is applied to the base of the second NPN transistor whose collector is applied with a voltage. A signal is applied to the base of the PNP transistor, the collector of the PNP transistor, the collector of the first NPN transistor, the emitter of the second NPN transistor, one end of the capacitor, and the input end of the comparison and inverting circuit are connected, The other end of the capacitor is grounded, and the pulse width modulation signal is output from the output end of the comparison and inverting circuit. Pulse width modulation signal output circuit, characterized by being configured to output.